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style: Organize and clean up layouts

main
Mathias Rasmussen 4 years ago
parent
23a88d73eb
commit
53ee4bc759
18 changed files with 109 additions and 108 deletions
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  1. 10
      Bluejay.asm
  2. 41
      Layouts/Base.inc
  3. 36
      Layouts/C.inc
  4. 2
      Layouts/D.inc
  5. 2
      Layouts/E.inc
  6. 2
      Layouts/G.inc
  7. 2
      Layouts/J.inc
  8. 4
      Layouts/L.inc
  9. 2
      Layouts/N.inc
  10. 19
      Layouts/O.inc
  11. 2
      Layouts/P.inc
  12. 36
      Layouts/Q.inc
  13. 4
      Layouts/R.inc
  14. 2
      Layouts/S.inc
  15. 2
      Layouts/U.inc
  16. 36
      Layouts/V.inc
  17. 1
      Layouts/W.inc
  18. 2
      Layouts/Z.inc

10
Bluejay.asm
View File

@ -75,13 +75,13 @@ H_ EQU 8 ; Cm Vn Bm Am __ __ __ RX Cc Bc Ac __ Cp Bp Ap __
I_ EQU 9 ; Vn Am Bm Cm __ RX __ __ Cp Bp Ap Cc Bc Ac __ __
J_ EQU 10 ; Am Cm Bm Vn RX L0 L1 L2 Ap Bp Cp Ac Bc Cc __ __ LEDs
K_ EQU 11 ; RX Am Vn Bm __ Cm __ __ Ac Bc Cc Cp Bp Ap __ __ Com fets inverted
L_ EQU 12 ; Cm Bm Am Vn __ RX __ __ Cp Bp Ap Cc Bc Ac __ __
L_ EQU 12 ; Cm Bm Am Vn __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ Like I with different mux pins
M_ EQU 13 ; __ __ L0 RX Bm Vn Cm Am __ Ap Bp Cp Ac Bc Cc __ LED
N_ EQU 14 ; Vn Am Bm Cm __ RX __ __ Ac Ap Bc Bp Cc Cp __ __
N_ EQU 14 ; Vn Am Bm Cm __ RX __ __ Ac Ap Bc Bp Cc Cp __ __ Like B, with A and C fets swapped
O_ EQU 15 ; Bm Cm Am Vn __ RX __ __ Ap Ac Bp Bc Cp Cc __ __ Like D, but low side pwm
P_ EQU 16 ; __ Cm Bm Vn Am RX __ __ __ Ap Bp Cp Ac Bc Cc __
P_ EQU 16 ; __ Cm Bm Vn Am RX __ __ __ Ap Bp Cp Ac Bc Cc __ Like M, without LEDs and different mux
Q_ EQU 17 ; __ RX __ L0 L1 Ap Bp Cp Ac Bc Cc Vn Cm Bm Am __ LEDs
R_ EQU 18 ; Vn Am Bm Cm __ RX __ __ Cp Bp Ap Cc Bc Ac __ __
R_ EQU 18 ; Vn Am Bm Cm __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ Like L, with different mux pins
S_ EQU 19 ; Bm Cm Am Vn __ RX __ __ Ap Ac Bp Bc Cp Cc __ __ Like O, but com fets inverted
T_ EQU 20 ; __ Cm Vn Bm __ Am __ RX Cc Bc Ac Ap Bp Cp __ __
U_ EQU 21 ; L2 L1 L0 RX Bm Vn Cm Am __ Ap Bp Cp Ac Bc Cc __ Like M, but with 3 LEDs
@ -89,7 +89,7 @@ V_ EQU 22 ; Am Bm Vn Cm __ RX __ Cc Cp Bc __ __ Bp Ac Ap __
W_ EQU 23 ; __ __ Am Vn __ Bm Cm RX __ __ __ __ Cp Bp Ap __ Tristate gate driver
X_ EQU 24
Y_ EQU 25
Z_ EQU 26 ; Bm Cm Am Vn __ RX __ __ Ac Ap Bc Bp Cc Cp __ __
Z_ EQU 26 ; Bm Cm Am Vn __ RX __ __ Ac Ap Bc Bp Cc Cp __ __ Pwm fets inverted
;**** **** **** **** ****
; Select the port mapping to use (or unselect all for use with external batch compile file)

41
Layouts/Base.inc
View File

@ -34,6 +34,7 @@
;**** **** **** **** ****
; Bootloader definitions
;**** **** **** **** ****
; Note: The RTX pin must be on port 0 because we use the IT01CF register for interrupts
RTX_PORT EQU P0 ; Receive/Transmit port
RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
@ -122,12 +123,12 @@ Initialize_Comparator MACRO
mov CMP_MD, #00h ;; Comparator response time 100ns
ENDM
$endif
Read_Comp_Out MACRO
mov A, CMP_CN0 ;; Read comparator output
ENDM
$endif
; Set comparator multiplexer to phase A
Set_Comp_Phase_A MACRO
mov CMP_MX, #((A_Mux SHL 4) + V_Mux)
@ -144,12 +145,30 @@ Set_Comp_Phase_C MACRO
ENDM
; Toggle FETs 'on' and 'off'
IF PWM_ACTIVE_HIGH == 1 ; PWM FET active high
pON LIT 'setb'
pOFF LIT 'clr'
ELSE ; PWM FET active low
pON LIT 'clr'
pOFF LIT 'setb'
ENDIF
IF COMPWM_ACTIVE_HIGH == 1 ; COM FET active high
cON LIT 'setb'
cOFF LIT 'clr'
ELSE ; COM FET active low
cON LIT 'clr'
cOFF LIT 'setb'
ENDIF
;**** **** **** **** ****
; PWM phase change
;**** **** **** **** ****
$if NOT CUSTOM_PWM_PHASE
; All pwm and com pins must be on port 1
; All pwm and complementary pwm pins must be on port 1 to use the base code below
P_ApwmFET EQU P1.A_pwm
P_AcomFET EQU P1.A_com
P_BpwmFET EQU P1.B_pwm
@ -196,22 +215,6 @@ $endif
;**** **** **** **** ****
$if NOT CUSTOM_FET_TOGGLING
IF PWM_ACTIVE_HIGH == 1 ; PWM FET active high
pON LIT 'setb'
pOFF LIT 'clr'
ELSE ; PWM FET active low
pON LIT 'clr'
pOFF LIT 'setb'
ENDIF
IF COMPWM_ACTIVE_HIGH == 1 ; COM FET active high
cON LIT 'setb'
cOFF LIT 'clr'
ELSE ; COM FET active low
cON LIT 'clr'
cOFF LIT 'setb'
ENDIF
ApwmFET_on MACRO
pON P_ApwmFET
IF FETON_DELAY == 0

36
Layouts/C.inc
View File

@ -83,6 +83,25 @@ B_com EQU 1
B_pwm EQU 0
P1_DIGITAL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com)
P1_INIT EQU 00h
P1_PUSHPULL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com)
P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; PWM Phase
;**** **** **** **** ****
P_ApwmFET EQU P0.A_pwm
P_AcomFET EQU P0.A_com
P_BpwmFET EQU P1.B_pwm
@ -90,13 +109,6 @@ P_BcomFET EQU P1.B_com
P_CpwmFET EQU P1.C_pwm
P_CcomFET EQU P1.C_com
P1_DIGITAL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com)
P1_INIT EQU 00h
P1_PUSHPULL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com)
P1_SKIP EQU 0FFh
Set_Pwm_A MACRO
IF FETON_DELAY == 0
cON P_AcomFET
@ -136,16 +148,6 @@ Set_Pwms_Off MACRO
ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; Inherit base layout
;**** **** **** **** ****

2
Layouts/D.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "D". Com fets are active low for H/L_N driver and EN_N/PWM driver
; Hardware definition file "D". Com fets are active low for H/L_N driver and EN_N/PWM driver. A with different comp
; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap
;
;**** **** **** **** ****

2
Layouts/E.inc
View File

@ -99,7 +99,7 @@ P2_SKIP EQU 0FFh
;**** **** **** **** ****
; MCU specific
; ESC specific
;**** **** **** **** ****
Initialize_Xbar MACRO
mov XBR2, #40h ;; Xbar enabled

2
Layouts/G.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "G"
; Hardware definition file "G". A with different comp ordering
; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap
;
;**** **** **** **** ****

2
Layouts/J.inc
View File

@ -69,8 +69,6 @@ P0_PUSHPULL EQU (1 SHL LED_0) + (1 SHL LED_1) + (1 SHL LED_2)
P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************

4
Layouts/L.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "L"
; Hardware definition file "L". I with different comp ordering
; X X RC X CC MA MB MC X X Ac Bc Cc Ap Bp Cp
;
;**** **** **** **** ****
@ -69,8 +69,6 @@ P0_PUSHPULL EQU 0
P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************

2
Layouts/N.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "N"
; Hardware definition file "N". B with A and C fets swapped
; X X RC X MC MB MA CC X X Cp Cc Bp Bc Ap Ac
;
;**** **** **** **** ****

19
Layouts/O.inc
View File

@ -88,16 +88,6 @@ P1_PUSHPULL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) +
P1_SKIP EQU 0FFh
Initialize_Comparator MACRO
mov CMP_CN0, #80h ;; Comparator enabled, no hysteresis
mov CMP_MD, #40h ;; Comparator response time 100ns, Output polarity inverted
ENDM
Read_Comp_Out MACRO
mov A, CMP_CN0 ;; Read comparator output
ENDM
;*********************
; PORT 2 definitions *
;*********************
@ -108,6 +98,15 @@ P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; Comparator setup
;**** **** **** **** ****
Initialize_Comparator MACRO
mov CMP_CN0, #80h ;; Comparator enabled, no hysteresis
mov CMP_MD, #40h ;; Comparator response time 100ns, Output polarity inverted
ENDM
;**** **** **** **** ****
; Inherit base layout
;**** **** **** **** ****

2
Layouts/P.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "P".
; Hardware definition file "P". M with different comp and no LEDs
; X X RC MA CC MB MC X X Cc Bc Ac Cp Bp Ap X
;
;**** **** **** **** ****

36
Layouts/Q.inc
View File

@ -83,6 +83,25 @@ B_com EQU 1
A_com EQU 0
P1_DIGITAL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
P1_INIT EQU 00h
P1_PUSHPULL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; PWM Phase
;**** **** **** **** ****
P_ApwmFET EQU P0.A_pwm
P_AcomFET EQU P1.A_com
P_BpwmFET EQU P0.B_pwm
@ -90,13 +109,6 @@ P_BcomFET EQU P1.B_com
P_CpwmFET EQU P0.C_pwm
P_CcomFET EQU P1.C_com
P1_DIGITAL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
P1_INIT EQU 00h
P1_PUSHPULL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
P1_SKIP EQU 0FFh
Set_Pwm_A MACRO
IF FETON_DELAY == 0
cON P_AcomFET
@ -136,16 +148,6 @@ Set_Pwms_Off MACRO
ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; LED configuration
;**** **** **** **** ****

4
Layouts/R.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "R".
; Hardware definition file "R". L with different comp
; X X RC X MC MB MA CC X X Ac Bc Cc Ap Bp Cp
;
;**** **** **** **** ****
@ -69,8 +69,6 @@ P0_PUSHPULL EQU 0
P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************

2
Layouts/S.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "S". like "O" but Com fets are active high, Pwm fets are active low
; Hardware definition file "S". like "O" but Com fets are active high, Pwm fets are active low. N with different comp
; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap
;
;**** **** **** **** ****

2
Layouts/U.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "U".
; Hardware definition file "U". Like M, but with 3 LEDs
; MA MC CC MB RC L0 L1 L2 X Cc Bc Ac Cp Bp Ap X
;
;**** **** **** **** ****

36
Layouts/V.inc
View File

@ -83,6 +83,25 @@ B_com EQU 1
C_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com)
P1_INIT EQU 00h
P1_PUSHPULL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com)
P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; PWM Phase
;**** **** **** **** ****
P_ApwmFET EQU P1.A_pwm
P_AcomFET EQU P1.A_com
P_BpwmFET EQU P1.B_pwm
@ -90,13 +109,6 @@ P_BcomFET EQU P1.B_com
P_CpwmFET EQU P1.C_pwm
P_CcomFET EQU P0.C_com
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com)
P1_INIT EQU 00h
P1_PUSHPULL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com)
P1_SKIP EQU 0FFh
Set_Pwm_A MACRO
IF FETON_DELAY == 0
cON P_AcomFET
@ -136,16 +148,6 @@ Set_Pwms_Off MACRO
ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)
P2_SKIP EQU 0FFh
;**** **** **** **** ****
; Inherit base layout
;**** **** **** **** ****

1
Layouts/W.inc
View File

@ -87,7 +87,6 @@ C_pwm EQU 4
P1_DIGITAL EQU NOT((1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm))
P1_INIT EQU 00h
P1_PUSHPULL EQU ((1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm))
;
P1_SKIP EQU 0FFh

2
Layouts/Z.inc
View File

@ -22,7 +22,7 @@
;
;**** **** **** **** ****
;
; Hardware definition file "Z"
; Hardware definition file "Z". N different comp and pwm active low
; X X RC X CC MA MC MB X X Cp Cc Bp Bc Ap Ac
;
;**** **** **** **** ****

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