From 53ee4bc75944672ac7ccaa2cd70c81aa2b1aea1a Mon Sep 17 00:00:00 2001 From: Mathias Rasmussen Date: Sat, 20 Feb 2021 00:09:53 +0100 Subject: [PATCH] style: Organize and clean up layouts --- Bluejay.asm | 10 +++++----- Layouts/Base.inc | 41 ++++++++++++++++++++++------------------- Layouts/C.inc | 36 +++++++++++++++++++----------------- Layouts/D.inc | 2 +- Layouts/E.inc | 2 +- Layouts/G.inc | 2 +- Layouts/J.inc | 2 -- Layouts/L.inc | 4 +--- Layouts/N.inc | 2 +- Layouts/O.inc | 19 +++++++++---------- Layouts/P.inc | 2 +- Layouts/Q.inc | 36 +++++++++++++++++++----------------- Layouts/R.inc | 4 +--- Layouts/S.inc | 2 +- Layouts/U.inc | 2 +- Layouts/V.inc | 36 +++++++++++++++++++----------------- Layouts/W.inc | 13 ++++++------- Layouts/Z.inc | 2 +- 18 files changed, 109 insertions(+), 108 deletions(-) diff --git a/Bluejay.asm b/Bluejay.asm index b76db73..35d82a3 100644 --- a/Bluejay.asm +++ b/Bluejay.asm @@ -75,13 +75,13 @@ H_ EQU 8 ; Cm Vn Bm Am __ __ __ RX Cc Bc Ac __ Cp Bp Ap __ I_ EQU 9 ; Vn Am Bm Cm __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ J_ EQU 10 ; Am Cm Bm Vn RX L0 L1 L2 Ap Bp Cp Ac Bc Cc __ __ LEDs K_ EQU 11 ; RX Am Vn Bm __ Cm __ __ Ac Bc Cc Cp Bp Ap __ __ Com fets inverted -L_ EQU 12 ; Cm Bm Am Vn __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ +L_ EQU 12 ; Cm Bm Am Vn __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ Like I with different mux pins M_ EQU 13 ; __ __ L0 RX Bm Vn Cm Am __ Ap Bp Cp Ac Bc Cc __ LED -N_ EQU 14 ; Vn Am Bm Cm __ RX __ __ Ac Ap Bc Bp Cc Cp __ __ +N_ EQU 14 ; Vn Am Bm Cm __ RX __ __ Ac Ap Bc Bp Cc Cp __ __ Like B, with A and C fets swapped O_ EQU 15 ; Bm Cm Am Vn __ RX __ __ Ap Ac Bp Bc Cp Cc __ __ Like D, but low side pwm -P_ EQU 16 ; __ Cm Bm Vn Am RX __ __ __ Ap Bp Cp Ac Bc Cc __ +P_ EQU 16 ; __ Cm Bm Vn Am RX __ __ __ Ap Bp Cp Ac Bc Cc __ Like M, without LEDs and different mux Q_ EQU 17 ; __ RX __ L0 L1 Ap Bp Cp Ac Bc Cc Vn Cm Bm Am __ LEDs -R_ EQU 18 ; Vn Am Bm Cm __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ +R_ EQU 18 ; Vn Am Bm Cm __ RX __ __ Cp Bp Ap Cc Bc Ac __ __ Like L, with different mux pins S_ EQU 19 ; Bm Cm Am Vn __ RX __ __ Ap Ac Bp Bc Cp Cc __ __ Like O, but com fets inverted T_ EQU 20 ; __ Cm Vn Bm __ Am __ RX Cc Bc Ac Ap Bp Cp __ __ U_ EQU 21 ; L2 L1 L0 RX Bm Vn Cm Am __ Ap Bp Cp Ac Bc Cc __ Like M, but with 3 LEDs @@ -89,7 +89,7 @@ V_ EQU 22 ; Am Bm Vn Cm __ RX __ Cc Cp Bc __ __ Bp Ac Ap __ W_ EQU 23 ; __ __ Am Vn __ Bm Cm RX __ __ __ __ Cp Bp Ap __ Tristate gate driver X_ EQU 24 Y_ EQU 25 -Z_ EQU 26 ; Bm Cm Am Vn __ RX __ __ Ac Ap Bc Bp Cc Cp __ __ +Z_ EQU 26 ; Bm Cm Am Vn __ RX __ __ Ac Ap Bc Bp Cc Cp __ __ Pwm fets inverted ;**** **** **** **** **** ; Select the port mapping to use (or unselect all for use with external batch compile file) diff --git a/Layouts/Base.inc b/Layouts/Base.inc index c1198ec..64bf781 100644 --- a/Layouts/Base.inc +++ b/Layouts/Base.inc @@ -34,6 +34,7 @@ ;**** **** **** **** **** ; Bootloader definitions ;**** **** **** **** **** +; Note: The RTX pin must be on port 0 because we use the IT01CF register for interrupts RTX_PORT EQU P0 ; Receive/Transmit port RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL @@ -122,12 +123,12 @@ Initialize_Comparator MACRO mov CMP_MD, #00h ;; Comparator response time 100ns ENDM +$endif + Read_Comp_Out MACRO mov A, CMP_CN0 ;; Read comparator output ENDM -$endif - ; Set comparator multiplexer to phase A Set_Comp_Phase_A MACRO mov CMP_MX, #((A_Mux SHL 4) + V_Mux) @@ -144,12 +145,30 @@ Set_Comp_Phase_C MACRO ENDM +; Toggle FETs 'on' and 'off' +IF PWM_ACTIVE_HIGH == 1 ; PWM FET active high +pON LIT 'setb' +pOFF LIT 'clr' +ELSE ; PWM FET active low +pON LIT 'clr' +pOFF LIT 'setb' +ENDIF + +IF COMPWM_ACTIVE_HIGH == 1 ; COM FET active high +cON LIT 'setb' +cOFF LIT 'clr' +ELSE ; COM FET active low +cON LIT 'clr' +cOFF LIT 'setb' +ENDIF + + ;**** **** **** **** **** ; PWM phase change ;**** **** **** **** **** $if NOT CUSTOM_PWM_PHASE -; All pwm and com pins must be on port 1 +; All pwm and complementary pwm pins must be on port 1 to use the base code below P_ApwmFET EQU P1.A_pwm P_AcomFET EQU P1.A_com P_BpwmFET EQU P1.B_pwm @@ -196,22 +215,6 @@ $endif ;**** **** **** **** **** $if NOT CUSTOM_FET_TOGGLING -IF PWM_ACTIVE_HIGH == 1 ; PWM FET active high -pON LIT 'setb' -pOFF LIT 'clr' -ELSE ; PWM FET active low -pON LIT 'clr' -pOFF LIT 'setb' -ENDIF - -IF COMPWM_ACTIVE_HIGH == 1 ; COM FET active high -cON LIT 'setb' -cOFF LIT 'clr' -ELSE ; COM FET active low -cON LIT 'clr' -cOFF LIT 'setb' -ENDIF - ApwmFET_on MACRO pON P_ApwmFET IF FETON_DELAY == 0 diff --git a/Layouts/C.inc b/Layouts/C.inc index 63eea99..d464ee7 100644 --- a/Layouts/C.inc +++ b/Layouts/C.inc @@ -83,6 +83,25 @@ B_com EQU 1 B_pwm EQU 0 +P1_DIGITAL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com) +P1_INIT EQU 00h +P1_PUSHPULL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com) +P1_SKIP EQU 0FFh + + +;********************* +; PORT 2 definitions * +;********************* +DebugPin EQU 0 + +P2_DIGITAL EQU (1 SHL DebugPin) +P2_PUSHPULL EQU (1 SHL DebugPin) +P2_SKIP EQU 0FFh + + +;**** **** **** **** **** +; PWM Phase +;**** **** **** **** **** P_ApwmFET EQU P0.A_pwm P_AcomFET EQU P0.A_com P_BpwmFET EQU P1.B_pwm @@ -90,13 +109,6 @@ P_BcomFET EQU P1.B_com P_CpwmFET EQU P1.C_pwm P_CcomFET EQU P1.C_com - -P1_DIGITAL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com) -P1_INIT EQU 00h -P1_PUSHPULL EQU (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL B_com) + (1 SHL C_com) -P1_SKIP EQU 0FFh - - Set_Pwm_A MACRO IF FETON_DELAY == 0 cON P_AcomFET @@ -136,16 +148,6 @@ Set_Pwms_Off MACRO ENDM -;********************* -; PORT 2 definitions * -;********************* -DebugPin EQU 0 - -P2_DIGITAL EQU (1 SHL DebugPin) -P2_PUSHPULL EQU (1 SHL DebugPin) -P2_SKIP EQU 0FFh - - ;**** **** **** **** **** ; Inherit base layout ;**** **** **** **** **** diff --git a/Layouts/D.inc b/Layouts/D.inc index 5109d1b..0725874 100644 --- a/Layouts/D.inc +++ b/Layouts/D.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "D". Com fets are active low for H/L_N driver and EN_N/PWM driver +; Hardware definition file "D". Com fets are active low for H/L_N driver and EN_N/PWM driver. A with different comp ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap ; ;**** **** **** **** **** diff --git a/Layouts/E.inc b/Layouts/E.inc index 590e663..6a3947f 100644 --- a/Layouts/E.inc +++ b/Layouts/E.inc @@ -99,7 +99,7 @@ P2_SKIP EQU 0FFh ;**** **** **** **** **** -; MCU specific +; ESC specific ;**** **** **** **** **** Initialize_Xbar MACRO mov XBR2, #40h ;; Xbar enabled diff --git a/Layouts/G.inc b/Layouts/G.inc index c301d73..0a1cc5b 100644 --- a/Layouts/G.inc +++ b/Layouts/G.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "G" +; Hardware definition file "G". A with different comp ordering ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap ; ;**** **** **** **** **** diff --git a/Layouts/J.inc b/Layouts/J.inc index 9f95cdd..5e704f8 100644 --- a/Layouts/J.inc +++ b/Layouts/J.inc @@ -69,8 +69,6 @@ P0_PUSHPULL EQU (1 SHL LED_0) + (1 SHL LED_1) + (1 SHL LED_2) P0_SKIP EQU 0FFh - - ;********************* ; PORT 1 definitions * ;********************* diff --git a/Layouts/L.inc b/Layouts/L.inc index e7fbf76..650ad78 100644 --- a/Layouts/L.inc +++ b/Layouts/L.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "L" +; Hardware definition file "L". I with different comp ordering ; X X RC X CC MA MB MC X X Ac Bc Cc Ap Bp Cp ; ;**** **** **** **** **** @@ -69,8 +69,6 @@ P0_PUSHPULL EQU 0 P0_SKIP EQU 0FFh - - ;********************* ; PORT 1 definitions * ;********************* diff --git a/Layouts/N.inc b/Layouts/N.inc index 13f495f..3a0aa5b 100644 --- a/Layouts/N.inc +++ b/Layouts/N.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "N" +; Hardware definition file "N". B with A and C fets swapped ; X X RC X MC MB MA CC X X Cp Cc Bp Bc Ap Ac ; ;**** **** **** **** **** diff --git a/Layouts/O.inc b/Layouts/O.inc index a5b7056..9a0597d 100644 --- a/Layouts/O.inc +++ b/Layouts/O.inc @@ -88,16 +88,6 @@ P1_PUSHPULL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + P1_SKIP EQU 0FFh -Initialize_Comparator MACRO - mov CMP_CN0, #80h ;; Comparator enabled, no hysteresis - mov CMP_MD, #40h ;; Comparator response time 100ns, Output polarity inverted -ENDM - -Read_Comp_Out MACRO - mov A, CMP_CN0 ;; Read comparator output -ENDM - - ;********************* ; PORT 2 definitions * ;********************* @@ -108,6 +98,15 @@ P2_PUSHPULL EQU (1 SHL DebugPin) P2_SKIP EQU 0FFh +;**** **** **** **** **** +; Comparator setup +;**** **** **** **** **** +Initialize_Comparator MACRO + mov CMP_CN0, #80h ;; Comparator enabled, no hysteresis + mov CMP_MD, #40h ;; Comparator response time 100ns, Output polarity inverted +ENDM + + ;**** **** **** **** **** ; Inherit base layout ;**** **** **** **** **** diff --git a/Layouts/P.inc b/Layouts/P.inc index 36e1431..86cf601 100644 --- a/Layouts/P.inc +++ b/Layouts/P.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "P". +; Hardware definition file "P". M with different comp and no LEDs ; X X RC MA CC MB MC X X Cc Bc Ac Cp Bp Ap X ; ;**** **** **** **** **** diff --git a/Layouts/Q.inc b/Layouts/Q.inc index 079c005..20a7ecb 100644 --- a/Layouts/Q.inc +++ b/Layouts/Q.inc @@ -83,6 +83,25 @@ B_com EQU 1 A_com EQU 0 +P1_DIGITAL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com) +P1_INIT EQU 00h +P1_PUSHPULL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com) +P1_SKIP EQU 0FFh + + +;********************* +; PORT 2 definitions * +;********************* +DebugPin EQU 0 + +P2_DIGITAL EQU (1 SHL DebugPin) +P2_PUSHPULL EQU (1 SHL DebugPin) +P2_SKIP EQU 0FFh + + +;**** **** **** **** **** +; PWM Phase +;**** **** **** **** **** P_ApwmFET EQU P0.A_pwm P_AcomFET EQU P1.A_com P_BpwmFET EQU P0.B_pwm @@ -90,13 +109,6 @@ P_BcomFET EQU P1.B_com P_CpwmFET EQU P0.C_pwm P_CcomFET EQU P1.C_com - -P1_DIGITAL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com) -P1_INIT EQU 00h -P1_PUSHPULL EQU (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com) -P1_SKIP EQU 0FFh - - Set_Pwm_A MACRO IF FETON_DELAY == 0 cON P_AcomFET @@ -136,16 +148,6 @@ Set_Pwms_Off MACRO ENDM -;********************* -; PORT 2 definitions * -;********************* -DebugPin EQU 0 - -P2_DIGITAL EQU (1 SHL DebugPin) -P2_PUSHPULL EQU (1 SHL DebugPin) -P2_SKIP EQU 0FFh - - ;**** **** **** **** **** ; LED configuration ;**** **** **** **** **** diff --git a/Layouts/R.inc b/Layouts/R.inc index 1d782cd..bdafb15 100644 --- a/Layouts/R.inc +++ b/Layouts/R.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "R". +; Hardware definition file "R". L with different comp ; X X RC X MC MB MA CC X X Ac Bc Cc Ap Bp Cp ; ;**** **** **** **** **** @@ -69,8 +69,6 @@ P0_PUSHPULL EQU 0 P0_SKIP EQU 0FFh - - ;********************* ; PORT 1 definitions * ;********************* diff --git a/Layouts/S.inc b/Layouts/S.inc index 79005e2..da79c10 100644 --- a/Layouts/S.inc +++ b/Layouts/S.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "S". like "O" but Com fets are active high, Pwm fets are active low +; Hardware definition file "S". like "O" but Com fets are active high, Pwm fets are active low. N with different comp ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap ; ;**** **** **** **** **** diff --git a/Layouts/U.inc b/Layouts/U.inc index c1d42ec..d83a192 100644 --- a/Layouts/U.inc +++ b/Layouts/U.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "U". +; Hardware definition file "U". Like M, but with 3 LEDs ; MA MC CC MB RC L0 L1 L2 X Cc Bc Ac Cp Bp Ap X ; ;**** **** **** **** **** diff --git a/Layouts/V.inc b/Layouts/V.inc index 2e62258..5dce934 100644 --- a/Layouts/V.inc +++ b/Layouts/V.inc @@ -83,6 +83,25 @@ B_com EQU 1 C_pwm EQU 0 +P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) +P1_INIT EQU 00h +P1_PUSHPULL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) +P1_SKIP EQU 0FFh + + +;********************* +; PORT 2 definitions * +;********************* +DebugPin EQU 0 + +P2_DIGITAL EQU (1 SHL DebugPin) +P2_PUSHPULL EQU (1 SHL DebugPin) +P2_SKIP EQU 0FFh + + +;**** **** **** **** **** +; PWM Phase +;**** **** **** **** **** P_ApwmFET EQU P1.A_pwm P_AcomFET EQU P1.A_com P_BpwmFET EQU P1.B_pwm @@ -90,13 +109,6 @@ P_BcomFET EQU P1.B_com P_CpwmFET EQU P1.C_pwm P_CcomFET EQU P0.C_com - -P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) -P1_INIT EQU 00h -P1_PUSHPULL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) -P1_SKIP EQU 0FFh - - Set_Pwm_A MACRO IF FETON_DELAY == 0 cON P_AcomFET @@ -136,16 +148,6 @@ Set_Pwms_Off MACRO ENDM -;********************* -; PORT 2 definitions * -;********************* -DebugPin EQU 0 - -P2_DIGITAL EQU (1 SHL DebugPin) -P2_PUSHPULL EQU (1 SHL DebugPin) -P2_SKIP EQU 0FFh - - ;**** **** **** **** **** ; Inherit base layout ;**** **** **** **** **** diff --git a/Layouts/W.inc b/Layouts/W.inc index f0e00a0..d8b50e4 100644 --- a/Layouts/W.inc +++ b/Layouts/W.inc @@ -87,12 +87,11 @@ C_pwm EQU 4 P1_DIGITAL EQU NOT((1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm)) P1_INIT EQU 00h P1_PUSHPULL EQU ((1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm)) -; P1_SKIP EQU 0FFh ApwmFET_on MACRO - setb P1.A_pwm ; set pin to high + setb P1.A_pwm ; set pin to high orl P1MDIN, #(1 SHL A_pwm) ; enable pin driver ENDM @@ -101,7 +100,7 @@ ApwmFET_off MACRO ENDM BpwmFET_on MACRO - setb P1.B_pwm ; set pin to high + setb P1.B_pwm ; set pin to high orl P1MDIN, #(1 SHL B_pwm) ; enable pin driver ENDM @@ -110,7 +109,7 @@ BpwmFET_off MACRO ENDM CpwmFET_on MACRO - setb P1.C_pwm ; set pin to high + setb P1.C_pwm ; set pin to high orl P1MDIN, #(1 SHL C_pwm) ; enable pin driver ENDM @@ -123,7 +122,7 @@ All_pwmFETs_Off MACRO ENDM AcomFET_on MACRO - clr P1.A_pwm ; set pin to low + clr P1.A_pwm ; set pin to low orl P1MDIN, #(1 SHL A_pwm) ; enable pin driver ENDM @@ -132,7 +131,7 @@ AcomFET_off MACRO ENDM BcomFET_on MACRO - clr P1.B_pwm ; set pin to low + clr P1.B_pwm ; set pin to low orl P1MDIN, #(1 SHL B_pwm) ; enable pin driver ENDM @@ -141,7 +140,7 @@ BcomFET_off MACRO ENDM CcomFET_on MACRO - clr P1.C_pwm ; set pin to low + clr P1.C_pwm ; set pin to low orl P1MDIN, #(1 SHL C_pwm) ; enable pin driver ENDM diff --git a/Layouts/Z.inc b/Layouts/Z.inc index cb9acf3..452a87f 100644 --- a/Layouts/Z.inc +++ b/Layouts/Z.inc @@ -22,7 +22,7 @@ ; ;**** **** **** **** **** ; -; Hardware definition file "Z" +; Hardware definition file "Z". N different comp and pwm active low ; X X RC X CC MA MC MB X X Cp Cc Bp Bc Ap Ac ; ;**** **** **** **** ****