Read Error
9 years ago
committed by
Konstantin Sharlaimov (DigitalEntity)
Konstantin Sharlaimov (DigitalEntity)
11 changed files with 639 additions and 8 deletions
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1.travis.yml
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18Makefile
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1fake_travis_build.sh
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2src/main/config/config.c
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4src/main/drivers/pwm_mapping.c
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2src/main/drivers/system.c
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2src/main/drivers/timer.c
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2src/main/sensors/initialisation.c
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372src/main/target/LUX_RACE/system_stm32f30x.c
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76src/main/target/LUX_RACE/system_stm32f30x.h
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167src/main/target/LUX_RACE/target.h
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/** |
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****************************************************************************** |
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* @file system_stm32f30x.c |
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* @author MCD Application Team |
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* @version V1.1.1 |
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* @date 28-March-2014 |
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
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* This file contains the system clock configuration for STM32F30x devices, |
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* and is generated by the clock configuration tool |
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* stm32f30x_Clock_Configuration_V1.0.0.xls |
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* |
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* 1. This file provides two functions and one global variable to be called from |
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* user application: |
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier |
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* and Divider factors, AHB/APBx prescalers and Flash settings), |
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* depending on the configuration made in the clock xls tool. |
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* This function is called at startup just after reset and |
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* before branch to main program. This call is made inside |
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* the "startup_stm32f30x.s" file. |
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* |
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
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* by the user application to setup the SysTick |
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* timer or configure other parameters. |
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* |
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
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* be called whenever the core clock is changed |
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* during program execution. |
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* |
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* 2. After each device reset the HSI (8 MHz) is used as system clock source. |
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* Then SystemInit() function is called, in "startup_stm32f30x.s" file, to |
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* configure the system clock before to branch to main program. |
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* |
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* 3. If the system clock source selected by user fails to startup, the SystemInit() |
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* function will do nothing and HSI still used as system clock source. User can |
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* add some code to deal with this issue inside the SetSysClock() function. |
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* |
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* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define |
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* in "stm32f30x.h" file. When HSE is used as system clock source, directly or |
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* through PLL, and you are using different crystal you have to adapt the HSE |
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* value to your own configuration. |
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* |
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* 5. This file configures the system clock as follows: |
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*============================================================================= |
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* Supported STM32F30x device |
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*----------------------------------------------------------------------------- |
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* System Clock source | PLL (HSE) |
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*----------------------------------------------------------------------------- |
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* SYSCLK(Hz) | 72000000 |
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*----------------------------------------------------------------------------- |
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* HCLK(Hz) | 72000000 |
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*----------------------------------------------------------------------------- |
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* AHB Prescaler | 1 |
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*----------------------------------------------------------------------------- |
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* APB2 Prescaler | 2 |
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*----------------------------------------------------------------------------- |
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* APB1 Prescaler | 2 |
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*----------------------------------------------------------------------------- |
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* HSE Frequency(Hz) | 8000000 |
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*---------------------------------------------------------------------------- |
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* PLLMUL | 9 |
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*----------------------------------------------------------------------------- |
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* PREDIV | 1 |
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*----------------------------------------------------------------------------- |
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* USB Clock | ENABLE |
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*----------------------------------------------------------------------------- |
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* Flash Latency(WS) | 2 |
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*----------------------------------------------------------------------------- |
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* Prefetch Buffer | ON |
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*----------------------------------------------------------------------------- |
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*============================================================================= |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
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* |
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
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* You may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at: |
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* |
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* http://www.st.com/software_license_agreement_liberty_v2 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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* |
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****************************************************************************** |
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*/ |
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/** @addtogroup CMSIS |
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* @{ |
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*/ |
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|
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/** @addtogroup stm32f30x_system |
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* @{ |
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*/ |
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|
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/** @addtogroup STM32F30x_System_Private_Includes |
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* @{ |
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*/ |
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|
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#include "stm32f30x.h" |
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|
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uint32_t hse_value = HSE_VALUE; |
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|
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/** |
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* @} |
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*/ |
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|
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/* Private typedef -----------------------------------------------------------*/ |
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|
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/** @addtogroup STM32F30x_System_Private_Defines |
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* @{ |
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*/ |
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/*!< Uncomment the following line if you need to relocate your vector Table in |
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Internal SRAM. */ |
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/* #define VECT_TAB_SRAM */ |
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
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This value must be a multiple of 0x200. */ |
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/** |
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* @} |
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*/ |
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|
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/* Private macro -------------------------------------------------------------*/ |
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|
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/** @addtogroup STM32F30x_System_Private_Variables |
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* @{ |
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*/ |
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|
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uint32_t SystemCoreClock = 72000000; |
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|
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
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|
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/** |
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* @} |
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*/ |
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|
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/** @addtogroup STM32F30x_System_Private_FunctionPrototypes |
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* @{ |
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*/ |
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|
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void SetSysClock(void); |
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|
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/** |
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* @} |
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*/ |
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|
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/** @addtogroup STM32F30x_System_Private_Functions |
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* @{ |
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*/ |
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|
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/** |
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* @brief Setup the microcontroller system |
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* Initialize the Embedded Flash Interface, the PLL and update the |
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* SystemFrequency variable. |
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* @param None |
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* @retval None |
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*/ |
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void SystemInit(void) |
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{ |
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/* FPU settings ------------------------------------------------------------*/ |
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
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#endif |
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|
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/* Reset the RCC clock configuration to the default reset state ------------*/ |
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/* Set HSION bit */ |
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RCC->CR |= (uint32_t)0x00000001; |
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|
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/* Reset CFGR register */ |
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RCC->CFGR &= 0xF87FC00C; |
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|
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/* Reset HSEON, CSSON and PLLON bits */ |
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RCC->CR &= (uint32_t)0xFEF6FFFF; |
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|
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/* Reset HSEBYP bit */ |
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RCC->CR &= (uint32_t)0xFFFBFFFF; |
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|
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ |
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RCC->CFGR &= (uint32_t)0xFF80FFFF; |
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|
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/* Reset PREDIV1[3:0] bits */ |
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; |
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|
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/* Reset USARTSW[1:0], I2CSW and TIMs bits */ |
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RCC->CFGR3 &= (uint32_t)0xFF00FCCC; |
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|
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/* Disable all interrupts */ |
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RCC->CIR = 0x00000000; |
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|
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/* Configure the System clock source, PLL Multiplier and Divider factors, |
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AHB/APBx prescalers and Flash settings ----------------------------------*/ |
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//SetSysClock(); // called from main() |
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|
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#ifdef VECT_TAB_SRAM |
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
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#else |
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
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#endif |
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} |
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|
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/** |
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* @brief Update SystemCoreClock variable according to Clock Register Values. |
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* The SystemCoreClock variable contains the core clock (HCLK), it can |
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* be used by the user application to setup the SysTick timer or configure |
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* other parameters. |
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* |
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* @note Each time the core clock (HCLK) changes, this function must be called |
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* to update SystemCoreClock variable value. Otherwise, any configuration |
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* based on this variable will be incorrect. |
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* |
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* @note - The system frequency computed by this function is not the real |
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* frequency in the chip. It is calculated based on the predefined |
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* constant and the selected clock source: |
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* |
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
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* |
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
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* |
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
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* or HSI_VALUE(*) multiplied/divided by the PLL factors. |
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* |
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* (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value |
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* 8 MHz) but the real value may vary depending on the variations |
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* in voltage and temperature. |
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* |
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* (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value |
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real |
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* frequency of the crystal used. Otherwise, this function may |
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* have wrong result. |
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* |
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* - The result of this function could be not correct when using fractional |
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* value for HSE crystal. |
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* |
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* @param None |
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* @retval None |
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*/ |
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void SystemCoreClockUpdate (void) |
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{ |
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; |
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|
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/* Get SYSCLK source -------------------------------------------------------*/ |
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tmp = RCC->CFGR & RCC_CFGR_SWS; |
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|
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switch (tmp) |
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{ |
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case 0x00: /* HSI used as system clock */ |
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SystemCoreClock = HSI_VALUE; |
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break; |
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case 0x04: /* HSE used as system clock */ |
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SystemCoreClock = HSE_VALUE; |
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break; |
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case 0x08: /* PLL used as system clock */ |
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/* Get PLL clock source and multiplication factor ----------------------*/ |
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pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
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pllmull = ( pllmull >> 18) + 2; |
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|
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if (pllsource == 0x00) |
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{ |
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/* HSI oscillator clock divided by 2 selected as PLL clock entry */ |
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
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} |
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else |
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{ |
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prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; |
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/* HSE oscillator clock selected as PREDIV1 clock entry */ |
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SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
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} |
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break; |
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default: /* HSI used as system clock */ |
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SystemCoreClock = HSI_VALUE; |
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break; |
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} |
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/* Compute HCLK clock frequency ----------------*/ |
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/* Get HCLK prescaler */ |
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
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/* HCLK clock frequency */ |
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SystemCoreClock >>= tmp; |
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} |
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|
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/** |
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* @brief Configures the System clock source, PLL Multiplier and Divider factors, |
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* AHB/APBx prescalers and Flash settings |
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* @note This function should be called only once the RCC clock configuration |
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* is reset to the default reset state (done in SystemInit() function). |
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* @param None |
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* @retval None |
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*/ |
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void SetSysClock(void) |
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{ |
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
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|
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/******************************************************************************/ |
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/* PLL (clocked by HSE) used as System clock source */ |
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/******************************************************************************/ |
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|
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/ |
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/* Enable HSE */ |
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RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
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|
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/* Wait till HSE is ready and if Time out is reached exit */ |
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do |
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{ |
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HSEStatus = RCC->CR & RCC_CR_HSERDY; |
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StartUpCounter++; |
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
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|
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if ((RCC->CR & RCC_CR_HSERDY) != RESET) |
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{ |
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HSEStatus = (uint32_t)0x01; |
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} |
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else |
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{ |
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HSEStatus = (uint32_t)0x00; |
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} |
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|
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if (HSEStatus == (uint32_t)0x01) |
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{ |
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/* Enable Prefetch Buffer and set Flash Latency */ |
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FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; |
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|
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/* HCLK = SYSCLK / 1 */ |
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RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
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|
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/* PCLK2 = HCLK / 1 */ |
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
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|
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/* PCLK1 = HCLK / 2 */ |
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RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
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|
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/* PLL configuration */ |
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9); |
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|
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/* Enable PLL */ |
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RCC->CR |= RCC_CR_PLLON; |
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|
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/* Wait till PLL is ready */ |
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while((RCC->CR & RCC_CR_PLLRDY) == 0) |
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{ |
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} |
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|
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/* Select PLL as system clock source */ |
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RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
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|
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/* Wait till PLL is used as system clock source */ |
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) |
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{ |
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} |
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} |
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else |
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{ /* If HSE fails to start-up, the application will have wrong clock |
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configuration. User can add here some code to deal with this error */ |
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} |
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} |
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|
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/** |
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* @} |
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*/ |
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|
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/** |
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* @} |
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*/ |
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|
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/** |
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* @} |
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*/ |
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|
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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|
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@ -0,0 +1,76 @@ |
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/** |
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****************************************************************************** |
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* @file system_stm32f30x.h |
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* @author MCD Application Team |
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* @version V1.1.1 |
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* @date 28-March-2014 |
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* @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices. |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
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* |
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
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* You may not use this file except in compliance with the License. |
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* You may obtain a copy of the License at: |
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* |
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* http://www.st.com/software_license_agreement_liberty_v2 |
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* |
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* Unless required by applicable law or agreed to in writing, software |
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* distributed under the License is distributed on an "AS IS" BASIS, |
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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* See the License for the specific language governing permissions and |
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* limitations under the License. |
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* |
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****************************************************************************** |
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*/ |
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|
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/** @addtogroup CMSIS |
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* @{ |
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*/ |
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|
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/** @addtogroup stm32f30x_system |
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* @{ |
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*/ |
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|
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/** |
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* @brief Define to prevent recursive inclusion |
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*/ |
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#ifndef __SYSTEM_STM32F30X_H |
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#define __SYSTEM_STM32F30X_H |
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|
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#ifdef __cplusplus |
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extern "C" { |
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#endif |
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|
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/* Exported types ------------------------------------------------------------*/ |
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ |
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/* Exported constants --------------------------------------------------------*/ |
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/* Exported macro ------------------------------------------------------------*/ |
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/* Exported functions ------------------------------------------------------- */ |
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|
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/** @addtogroup STM32F30x_System_Exported_Functions |
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* @{ |
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*/ |
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|
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extern void SystemInit(void); |
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extern void SystemCoreClockUpdate(void); |
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|
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/** |
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* @} |
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*/ |
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|
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#ifdef __cplusplus |
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} |
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#endif |
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|
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#endif /*__SYSTEM_STM32F30X_H */ |
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|
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/** |
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* @} |
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*/ |
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|
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/** |
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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@ -0,0 +1,167 @@ |
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/* |
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* This file is part of Cleanflight. |
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* |
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* Cleanflight is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* Cleanflight is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with Cleanflight. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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#pragma once |
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|
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#define TARGET_BOARD_IDENTIFIER "LUX" |
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#define BOARD_HAS_VOLTAGE_DIVIDER |
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|
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#define LED0_GPIO GPIOC |
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#define LED0_PIN Pin_15 |
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#define LED0_PERIPHERAL RCC_AHBPeriph_GPIOC |
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|
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#define LED1_GPIO GPIOC |
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#define LED1_PIN Pin_14 |
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#define LED1_PERIPHERAL RCC_AHBPeriph_GPIOC |
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|
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#define LED2_GPIO GPIOC |
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#define LED2_PIN Pin_13 |
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#define LED2_PERIPHERAL RCC_AHBPeriph_GPIOC |
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|
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#define BEEP_GPIO GPIOB |
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#define BEEP_PIN Pin_13 |
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#define BEEP_PERIPHERAL RCC_AHBPeriph_GPIOB |
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#define BEEPER_INVERTED |
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|
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#define MPU6500_CS_GPIO_CLK_PERIPHERAL RCC_AHBPeriph_GPIOA |
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#define MPU6500_CS_GPIO GPIOA |
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#define MPU6500_CS_PIN GPIO_Pin_4 |
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#define MPU6500_SPI_INSTANCE SPI1 |
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|
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#define USE_SPI |
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#define USE_SPI_DEVICE_1 |
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|
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#define SPI1_GPIO GPIOB |
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#define SPI1_GPIO_PERIPHERAL RCC_AHBPeriph_GPIOB |
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#define SPI1_SCK_PIN GPIO_Pin_3 |
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#define SPI1_SCK_PIN_SOURCE GPIO_PinSource3 |
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#define SPI1_MISO_PIN GPIO_Pin_4 |
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#define SPI1_MISO_PIN_SOURCE GPIO_PinSource4 |
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#define SPI1_MOSI_PIN GPIO_Pin_5 |
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#define SPI1_MOSI_PIN_SOURCE GPIO_PinSource5 |
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|
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#define USABLE_TIMER_CHANNEL_COUNT 11 |
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|
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#define EXTI_CALLBACK_HANDLER_COUNT 1 // MPU data ready |
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|
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#define GYRO |
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#define USE_GYRO_MPU6500 |
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#define USE_GYRO_SPI_MPU6500 |
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#define GYRO_MPU6500_ALIGN CW270_DEG |
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|
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#define ACC |
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#define USE_ACC_MPU6500 |
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#define USE_ACC_SPI_MPU6500 |
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#define ACC_MPU6500_ALIGN CW270_DEG |
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|
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#define BEEPER |
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#define LED0 |
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#define LED1 |
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#define LED2 |
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|
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#define USB_IO |
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|
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#define USE_VCP |
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#define USE_USART1 |
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#define USE_USART2 |
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#define USE_USART3 |
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#define SERIAL_PORT_COUNT 4 |
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|
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#define UART1_TX_PIN GPIO_Pin_4 |
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#define UART1_RX_PIN GPIO_Pin_5 |
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#define UART1_GPIO GPIOC |
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#define UART1_GPIO_AF GPIO_AF_7 |
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#define UART1_TX_PINSOURCE GPIO_PinSource4 |
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#define UART1_RX_PINSOURCE GPIO_PinSource5 |
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|
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#define UART2_TX_PIN GPIO_Pin_14 |
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#define UART2_RX_PIN GPIO_Pin_15 |
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#define UART2_GPIO GPIOA |
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#define UART2_GPIO_AF GPIO_AF_7 |
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#define UART2_TX_PINSOURCE GPIO_PinSource14 |
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#define UART2_RX_PINSOURCE GPIO_PinSource15 |
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|
|||
#define UART3_TX_PIN GPIO_Pin_10 |
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#define UART3_RX_PIN GPIO_Pin_11 |
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#define UART3_GPIO GPIOB |
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#define UART3_GPIO_AF GPIO_AF_7 |
|||
#define UART3_TX_PINSOURCE GPIO_PinSource10 |
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#define UART3_RX_PINSOURCE GPIO_PinSource11 |
|||
|
|||
#define USE_ADC |
|||
|
|||
#define ADC_INSTANCE ADC1 |
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#define ADC_AHB_PERIPHERAL RCC_AHBPeriph_DMA1 |
|||
#define ADC_DMA_CHANNEL DMA1_Channel1 |
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|
|||
#define VBAT_ADC_GPIO GPIOC |
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#define VBAT_ADC_GPIO_PIN GPIO_Pin_0 |
|||
#define VBAT_ADC_CHANNEL ADC_Channel_6 |
|||
|
|||
#define CURRENT_METER_ADC_GPIO GPIOC |
|||
#define CURRENT_METER_ADC_GPIO_PIN GPIO_Pin_1 |
|||
#define CURRENT_METER_ADC_CHANNEL ADC_Channel_7 |
|||
|
|||
#define RSSI_ADC_GPIO GPIOC |
|||
#define RSSI_ADC_GPIO_PIN GPIO_Pin_2 |
|||
#define RSSI_ADC_CHANNEL ADC_Channel_8 |
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|
|||
#define EXTERNAL1_ADC_GPIO GPIOC |
|||
#define EXTERNAL1_ADC_GPIO_PIN GPIO_Pin_3 |
|||
#define EXTERNAL1_ADC_CHANNEL ADC_Channel_9 |
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|
|||
#define BLACKBOX |
|||
#define GPS |
|||
#define GTUNE |
|||
#define LED_STRIP |
|||
|
|||
#define LED_STRIP_TIMER TIM16 |
|||
|
|||
#define WS2811_GPIO GPIOA |
|||
#define WS2811_GPIO_AHB_PERIPHERAL RCC_AHBPeriph_GPIOA |
|||
#define WS2811_GPIO_AF GPIO_AF_1 |
|||
#define WS2811_PIN GPIO_Pin_6 // TIM16_CH1 |
|||
#define WS2811_PIN_SOURCE GPIO_PinSource6 |
|||
#define WS2811_TIMER TIM16 |
|||
#define WS2811_TIMER_APB2_PERIPHERAL RCC_APB2Periph_TIM16 |
|||
#define WS2811_DMA_CHANNEL DMA1_Channel3 |
|||
#define WS2811_IRQ DMA1_Channel3_IRQn |
|||
#define WS2811_DMA_TC_FLAG DMA1_FLAG_TC3 |
|||
#define WS2811_DMA_HANDLER_IDENTIFER DMA1_CH3_HANDLER |
|||
|
|||
|
|||
// MPU6500 interrupt |
|||
//#define DEBUG_MPU_DATA_READY_INTERRUPT |
|||
#define USE_MPU_DATA_READY_SIGNAL |
|||
#define ENSURE_MPU_DATA_READY_IS_LOW |
|||
|
|||
#define TELEMETRY |
|||
#define SERIAL_RX |
|||
#define USE_SERVOS |
|||
#define USE_CLI |
|||
|
|||
#define SPEKTRUM_BIND |
|||
// USART1, PC5 |
|||
#define BIND_PORT GPIOC |
|||
#define BIND_PIN Pin_5 |
|||
|
|||
#define USE_SERIAL_1WIRE |
|||
// Untested |
|||
#define S1W_TX_GPIO GPIOB |
|||
#define S1W_TX_PIN GPIO_Pin_10 |
|||
#define S1W_RX_GPIO GPIOB |
|||
#define S1W_RX_PIN GPIO_Pin_11 |
|||
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