diff --git a/.travis.yml b/.travis.yml
index 0c6d16ae8..68573a2e5 100755
--- a/.travis.yml
+++ b/.travis.yml
@@ -8,6 +8,7 @@ env:
- TARGET=CJMCU
- TARGET=EUSTM32F103RC
- TARGET=SPRACINGF3
+ - TARGET=LUX_RACE
- TARGET=MOTOLAB
- TARGET=NAZE
- TARGET=NAZE32PRO
diff --git a/Makefile b/Makefile
index d272d6545..ce2756006 100755
--- a/Makefile
+++ b/Makefile
@@ -36,6 +36,7 @@ FLASH_SIZE ?=
FORKNAME = inav
VALID_TARGETS = ALIENWIIF1 ALIENWIIF3 CC3D CHEBUZZF3 CJMCU COLIBRI_RACE EUSTM32F103RC MOTOLAB NAZE NAZE32PRO OLIMEXINO PORT103R RMDO SPARKY SPRACINGF3 STM32F3DISCOVERY
+VALID_TARGETS = ALIENWIIF1 ALIENWIIF3 CC3D CHEBUZZF3 CJMCU COLIBRI_RACE LUX_RACE EUSTM32F103RC MOTOLAB NAZE NAZE32PRO OLIMEXINO PORT103R RMDO SPARKY SPRACINGF3 STM32F3DISCOVERY
# Configure default flash sizes for the targets
ifeq ($(FLASH_SIZE),)
@@ -43,7 +44,7 @@ ifeq ($(TARGET),$(filter $(TARGET),CJMCU))
FLASH_SIZE = 64
else ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF1 CC3D NAZE OLIMEXINO RMDO))
FLASH_SIZE = 128
-else ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE EUSTM32F103RC MOTOLAB NAZE32PRO PORT103R SPARKY SPRACINGF3 STM32F3DISCOVERY))
+else ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE LUX_RACE EUSTM32F103RC MOTOLAB NAZE32PRO PORT103R SPARKY SPRACINGF3 STM32F3DISCOVERY))
FLASH_SIZE = 256
else
$(error FLASH_SIZE not configured for target)
@@ -68,7 +69,7 @@ USBPERIPH_SRC = $(notdir $(wildcard $(USBFS_DIR)/src/*.c))
CSOURCES := $(shell find $(SRC_DIR) -name '*.c')
-ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE MOTOLAB NAZE32PRO RMDO SPARKY SPRACINGF3 STM32F3DISCOVERY))
+ifeq ($(TARGET),$(filter $(TARGET),ALIENWIIF3 CHEBUZZF3 COLIBRI_RACE LUX_RACE MOTOLAB NAZE32PRO RMDO SPARKY SPRACINGF3 STM32F3DISCOVERY))
STDPERIPH_DIR = $(ROOT)/lib/main/STM32F30x_StdPeriph_Driver
@@ -553,6 +554,19 @@ COLIBRI_RACE_SRC = \
$(HIGHEND_SRC) \
$(COMMON_SRC) \
$(VCP_SRC)
+
+LUX_RACE_SRC = \
+ $(STM32F30x_COMMON_SRC) \
+ drivers/accgyro_mpu.c \
+ drivers/accgyro_mpu6500.c \
+ drivers/accgyro_spi_mpu6500.c \
+ drivers/accgyro_mpu6500.c \
+ drivers/light_ws2811strip.c \
+ drivers/light_ws2811strip_stm32f30x.c \
+ drivers/serial_usb_vcp.c \
+ $(HIGHEND_SRC) \
+ $(COMMON_SRC) \
+ $(VCP_SRC)
SPARKY_SRC = \
$(STM32F30x_COMMON_SRC) \
diff --git a/fake_travis_build.sh b/fake_travis_build.sh
index ae7d5119d..bfdc8ac4d 100755
--- a/fake_travis_build.sh
+++ b/fake_travis_build.sh
@@ -8,6 +8,7 @@ targets=("PUBLISHMETA=True" \
"TARGET=COLIBRI_RACE" \
"TARGET=EUSTM32F103RC" \
"TARGET=SPRACINGF3" \
+ "TARGET=LUX_RACE" \
"TARGET=MOTOLAB" \
"TARGET=NAZE" \
"TARGET=NAZE32PRO" \
diff --git a/src/main/config/config.c b/src/main/config/config.c
index be1467802..232481482 100755
--- a/src/main/config/config.c
+++ b/src/main/config/config.c
@@ -436,7 +436,7 @@ static void resetConf(void)
masterConfig.mixerMode = MIXER_QUADX;
featureClearAll();
persistentFlagClearAll();
-#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) || defined(MOTOLAB)
+#if defined(CJMCU) || defined(SPARKY) || defined(COLIBRI_RACE) || defined(MOTOLAB) || defined(LUX_RACE)
featureSet(FEATURE_RX_PPM);
#endif
diff --git a/src/main/drivers/pwm_mapping.c b/src/main/drivers/pwm_mapping.c
index c564496d3..3dd6996a8 100644
--- a/src/main/drivers/pwm_mapping.c
+++ b/src/main/drivers/pwm_mapping.c
@@ -241,7 +241,7 @@ static const uint16_t airPWM[] = {
};
#endif
-#ifdef COLIBRI_RACE
+#if defined(COLIBRI_RACE) || defined(LUX_RACE)
static const uint16_t multiPPM[] = {
PWM1 | (MAP_TO_PPM_INPUT << 8), // PPM input
PWM2 | (MAP_TO_MOTOR_OUTPUT << 8),
@@ -561,7 +561,7 @@ pwmOutputConfiguration_t *pwmInit(drv_pwm_config_t *init)
type = MAP_TO_SERVO_OUTPUT;
#endif
-#if defined(COLIBRI_RACE)
+#if defined(COLIBRI_RACE) || defined(LUX_RACE)
// remap PWM1+2 as servos
if ((timerIndex == PWM6 || timerIndex == PWM7 || timerIndex == PWM8 || timerIndex == PWM9) && timerHardwarePtr->tim == TIM2)
type = MAP_TO_SERVO_OUTPUT;
diff --git a/src/main/drivers/system.c b/src/main/drivers/system.c
index 8bc60f65b..7c11ff7d1 100644
--- a/src/main/drivers/system.c
+++ b/src/main/drivers/system.c
@@ -90,7 +90,7 @@ void EXTI15_10_IRQHandler(void)
}
#endif
-#if defined (COLIBRI_RACE)
+#if defined(COLIBRI_RACE) || defined(LUX_RACE)
void EXTI9_5_IRQHandler(void)
{
extiHandler(EXTI9_5_IRQn);
diff --git a/src/main/drivers/timer.c b/src/main/drivers/timer.c
index fdc314156..f7778c9f6 100755
--- a/src/main/drivers/timer.c
+++ b/src/main/drivers/timer.c
@@ -115,7 +115,7 @@ const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
#endif
-#ifdef COLIBRI_RACE
+#if defined(COLIBRI_RACE) || defined(LUX_RACE)
const timerHardware_t timerHardware[USABLE_TIMER_CHANNEL_COUNT] = {
{ TIM1, GPIOA, Pin_8, TIM_Channel_1, TIM1_CC_IRQn, 0, Mode_AF_PP_PD, GPIO_PinSource8, GPIO_AF_6}, // PWM1 - PA8
diff --git a/src/main/sensors/initialisation.c b/src/main/sensors/initialisation.c
index 9191e1aaa..6a160b1e5 100755
--- a/src/main/sensors/initialisation.c
+++ b/src/main/sensors/initialisation.c
@@ -156,7 +156,7 @@ const extiConfig_t *selectMPUIntExtiConfig(void)
return &MotolabF3MPUIntExtiConfig;
#endif
-#if defined(COLIBRI_RACE)
+#if defined(COLIBRI_RACE) || defined(LUX_RACE)
static const extiConfig_t colibriRaceMPUIntExtiConfig = {
.gpioAHBPeripherals = RCC_AHBPeriph_GPIOA,
.gpioPort = GPIOA,
diff --git a/src/main/target/LUX_RACE/system_stm32f30x.c b/src/main/target/LUX_RACE/system_stm32f30x.c
new file mode 100644
index 000000000..fca696982
--- /dev/null
+++ b/src/main/target/LUX_RACE/system_stm32f30x.c
@@ -0,0 +1,372 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.c
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 28-March-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32F30x devices,
+ * and is generated by the clock configuration tool
+ * stm32f30x_Clock_Configuration_V1.0.0.xls
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f30x.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the HSI (8 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and HSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+ * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ * Supported STM32F30x device
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 72000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *----------------------------------------------------------------------------
+ * PLLMUL | 9
+ *-----------------------------------------------------------------------------
+ * PREDIV | 1
+ *-----------------------------------------------------------------------------
+ * USB Clock | ENABLE
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 2
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | ON
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/** @addtogroup STM32F30x_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f30x.h"
+
+uint32_t hse_value = HSE_VALUE;
+
+/**
+ * @}
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/** @addtogroup STM32F30x_System_Private_Defines
+ * @{
+ */
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @addtogroup STM32F30x_System_Private_Variables
+ * @{
+ */
+
+ uint32_t SystemCoreClock = 72000000;
+
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_FunctionPrototypes
+ * @{
+ */
+
+void SetSysClock(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F30x_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemFrequency variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure the System clock source, PLL Multiplier and Divider factors,
+ AHB/APBx prescalers and Flash settings ----------------------------------*/
+ //SetSysClock(); // called from main()
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = ( pllmull >> 18) + 2;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ }
+ else
+ {
+ prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
+ }
+ break;
+ default: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK clock frequency ----------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+void SetSysClock(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable Prefetch Buffer and set Flash Latency */
+ FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
+
+ /* HCLK = SYSCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK / 1 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK / 2 */
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+ /* PLL configuration */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+ }
+ else
+ { /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/src/main/target/LUX_RACE/system_stm32f30x.h b/src/main/target/LUX_RACE/system_stm32f30x.h
new file mode 100644
index 000000000..4f999d305
--- /dev/null
+++ b/src/main/target/LUX_RACE/system_stm32f30x.h
@@ -0,0 +1,76 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f30x.h
+ * @author MCD Application Team
+ * @version V1.1.1
+ * @date 28-March-2014
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F30x devices.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f30x_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F30X_H
+#define __SYSTEM_STM32F30X_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/** @addtogroup STM32F30x_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F30X_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/src/main/target/LUX_RACE/target.h b/src/main/target/LUX_RACE/target.h
new file mode 100644
index 000000000..46b8122db
--- /dev/null
+++ b/src/main/target/LUX_RACE/target.h
@@ -0,0 +1,167 @@
+/*
+ * This file is part of Cleanflight.
+ *
+ * Cleanflight is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Cleanflight is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Cleanflight. If not, see .
+ */
+
+#pragma once
+
+#define TARGET_BOARD_IDENTIFIER "LUX"
+#define BOARD_HAS_VOLTAGE_DIVIDER
+
+#define LED0_GPIO GPIOC
+#define LED0_PIN Pin_15
+#define LED0_PERIPHERAL RCC_AHBPeriph_GPIOC
+
+#define LED1_GPIO GPIOC
+#define LED1_PIN Pin_14
+#define LED1_PERIPHERAL RCC_AHBPeriph_GPIOC
+
+#define LED2_GPIO GPIOC
+#define LED2_PIN Pin_13
+#define LED2_PERIPHERAL RCC_AHBPeriph_GPIOC
+
+#define BEEP_GPIO GPIOB
+#define BEEP_PIN Pin_13
+#define BEEP_PERIPHERAL RCC_AHBPeriph_GPIOB
+#define BEEPER_INVERTED
+
+#define MPU6500_CS_GPIO_CLK_PERIPHERAL RCC_AHBPeriph_GPIOA
+#define MPU6500_CS_GPIO GPIOA
+#define MPU6500_CS_PIN GPIO_Pin_4
+#define MPU6500_SPI_INSTANCE SPI1
+
+#define USE_SPI
+#define USE_SPI_DEVICE_1
+
+#define SPI1_GPIO GPIOB
+#define SPI1_GPIO_PERIPHERAL RCC_AHBPeriph_GPIOB
+#define SPI1_SCK_PIN GPIO_Pin_3
+#define SPI1_SCK_PIN_SOURCE GPIO_PinSource3
+#define SPI1_MISO_PIN GPIO_Pin_4
+#define SPI1_MISO_PIN_SOURCE GPIO_PinSource4
+#define SPI1_MOSI_PIN GPIO_Pin_5
+#define SPI1_MOSI_PIN_SOURCE GPIO_PinSource5
+
+#define USABLE_TIMER_CHANNEL_COUNT 11
+
+#define EXTI_CALLBACK_HANDLER_COUNT 1 // MPU data ready
+
+#define GYRO
+#define USE_GYRO_MPU6500
+#define USE_GYRO_SPI_MPU6500
+#define GYRO_MPU6500_ALIGN CW270_DEG
+
+#define ACC
+#define USE_ACC_MPU6500
+#define USE_ACC_SPI_MPU6500
+#define ACC_MPU6500_ALIGN CW270_DEG
+
+#define BEEPER
+#define LED0
+#define LED1
+#define LED2
+
+#define USB_IO
+
+#define USE_VCP
+#define USE_USART1
+#define USE_USART2
+#define USE_USART3
+#define SERIAL_PORT_COUNT 4
+
+#define UART1_TX_PIN GPIO_Pin_4
+#define UART1_RX_PIN GPIO_Pin_5
+#define UART1_GPIO GPIOC
+#define UART1_GPIO_AF GPIO_AF_7
+#define UART1_TX_PINSOURCE GPIO_PinSource4
+#define UART1_RX_PINSOURCE GPIO_PinSource5
+
+#define UART2_TX_PIN GPIO_Pin_14
+#define UART2_RX_PIN GPIO_Pin_15
+#define UART2_GPIO GPIOA
+#define UART2_GPIO_AF GPIO_AF_7
+#define UART2_TX_PINSOURCE GPIO_PinSource14
+#define UART2_RX_PINSOURCE GPIO_PinSource15
+
+#define UART3_TX_PIN GPIO_Pin_10
+#define UART3_RX_PIN GPIO_Pin_11
+#define UART3_GPIO GPIOB
+#define UART3_GPIO_AF GPIO_AF_7
+#define UART3_TX_PINSOURCE GPIO_PinSource10
+#define UART3_RX_PINSOURCE GPIO_PinSource11
+
+#define USE_ADC
+
+#define ADC_INSTANCE ADC1
+#define ADC_AHB_PERIPHERAL RCC_AHBPeriph_DMA1
+#define ADC_DMA_CHANNEL DMA1_Channel1
+
+#define VBAT_ADC_GPIO GPIOC
+#define VBAT_ADC_GPIO_PIN GPIO_Pin_0
+#define VBAT_ADC_CHANNEL ADC_Channel_6
+
+#define CURRENT_METER_ADC_GPIO GPIOC
+#define CURRENT_METER_ADC_GPIO_PIN GPIO_Pin_1
+#define CURRENT_METER_ADC_CHANNEL ADC_Channel_7
+
+#define RSSI_ADC_GPIO GPIOC
+#define RSSI_ADC_GPIO_PIN GPIO_Pin_2
+#define RSSI_ADC_CHANNEL ADC_Channel_8
+
+#define EXTERNAL1_ADC_GPIO GPIOC
+#define EXTERNAL1_ADC_GPIO_PIN GPIO_Pin_3
+#define EXTERNAL1_ADC_CHANNEL ADC_Channel_9
+
+#define BLACKBOX
+#define GPS
+#define GTUNE
+#define LED_STRIP
+
+#define LED_STRIP_TIMER TIM16
+
+#define WS2811_GPIO GPIOA
+#define WS2811_GPIO_AHB_PERIPHERAL RCC_AHBPeriph_GPIOA
+#define WS2811_GPIO_AF GPIO_AF_1
+#define WS2811_PIN GPIO_Pin_6 // TIM16_CH1
+#define WS2811_PIN_SOURCE GPIO_PinSource6
+#define WS2811_TIMER TIM16
+#define WS2811_TIMER_APB2_PERIPHERAL RCC_APB2Periph_TIM16
+#define WS2811_DMA_CHANNEL DMA1_Channel3
+#define WS2811_IRQ DMA1_Channel3_IRQn
+#define WS2811_DMA_TC_FLAG DMA1_FLAG_TC3
+#define WS2811_DMA_HANDLER_IDENTIFER DMA1_CH3_HANDLER
+
+
+// MPU6500 interrupt
+//#define DEBUG_MPU_DATA_READY_INTERRUPT
+#define USE_MPU_DATA_READY_SIGNAL
+#define ENSURE_MPU_DATA_READY_IS_LOW
+
+#define TELEMETRY
+#define SERIAL_RX
+#define USE_SERVOS
+#define USE_CLI
+
+#define SPEKTRUM_BIND
+// USART1, PC5
+#define BIND_PORT GPIOC
+#define BIND_PIN Pin_5
+
+#define USE_SERIAL_1WIRE
+// Untested
+#define S1W_TX_GPIO GPIOB
+#define S1W_TX_PIN GPIO_Pin_10
+#define S1W_RX_GPIO GPIOB
+#define S1W_RX_PIN GPIO_Pin_11