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style: Remove layout i/o comments

main
Mathias Rasmussen 4 years ago
parent
commit
23a88d73eb
  1. 34
      Layouts/A.inc
  2. 34
      Layouts/B.inc
  3. 34
      Layouts/C.inc
  4. 34
      Layouts/D.inc
  5. 34
      Layouts/E.inc
  6. 34
      Layouts/F.inc
  7. 34
      Layouts/G.inc
  8. 34
      Layouts/H.inc
  9. 34
      Layouts/I.inc
  10. 34
      Layouts/J.inc
  11. 34
      Layouts/K.inc
  12. 34
      Layouts/L.inc
  13. 34
      Layouts/M.inc
  14. 34
      Layouts/N.inc
  15. 34
      Layouts/O.inc
  16. 34
      Layouts/P.inc
  17. 34
      Layouts/Q.inc
  18. 34
      Layouts/R.inc
  19. 34
      Layouts/S.inc
  20. 34
      Layouts/T.inc
  21. 34
      Layouts/U.inc
  22. 34
      Layouts/V.inc
  23. 34
      Layouts/W.inc
  24. 34
      Layouts/Z.inc

34
Layouts/A.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
B_Mux EQU 2 ;i
A_Mux EQU 1 ;i
V_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
B_Mux EQU 2
A_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_com EQU 5 ;o
C_pwm EQU 4 ;o
B_com EQU 3 ;o
B_pwm EQU 2 ;o
A_com EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
; EQU 6
C_com EQU 5
C_pwm EQU 4
B_com EQU 3
B_pwm EQU 2
A_com EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/B.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
B_Mux EQU 2 ;i
A_Mux EQU 1 ;i
V_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
B_Mux EQU 2
A_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
A_pwm EQU 5 ;o
A_com EQU 4 ;o
B_pwm EQU 3 ;o
B_com EQU 2 ;o
C_pwm EQU 1 ;o
C_com EQU 0 ;o
; EQU 7
; EQU 6
A_pwm EQU 5
A_com EQU 4
B_pwm EQU 3
B_com EQU 2
C_pwm EQU 1
C_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/C.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
A_com EQU 7 ;o
A_pwm EQU 6 ;o
C_Mux EQU 5 ;i
B_Mux EQU 4 ;i
A_Mux EQU 3 ;i
V_Mux EQU 2 ;i
; EQU 1 ;i
Rcp_In EQU 0 ;i
A_com EQU 7
A_pwm EQU 6
C_Mux EQU 5
B_Mux EQU 4
A_Mux EQU 3
V_Mux EQU 2
; EQU 1
Rcp_In EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
@ -73,14 +73,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
; EQU 5 ;i
; EQU 4 ;i
C_com EQU 3 ;o
C_pwm EQU 2 ;o
B_com EQU 1 ;o
B_pwm EQU 0 ;o
; EQU 7
; EQU 6
; EQU 5
; EQU 4
C_com EQU 3
C_pwm EQU 2
B_com EQU 1
B_pwm EQU 0
P_ApwmFET EQU P0.A_pwm
@ -139,7 +139,7 @@ ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/D.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
C_Mux EQU 1 ;i
B_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
C_Mux EQU 1
B_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_com EQU 5 ;o
C_pwm EQU 4 ;o
B_com EQU 3 ;o
B_pwm EQU 2 ;o
A_com EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
; EQU 6
C_com EQU 5
C_pwm EQU 4
B_com EQU 3
B_pwm EQU 2
A_com EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/E.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
LED_1 EQU 7 ;o
LED_0 EQU 6 ;o
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
B_Mux EQU 2 ;i
A_Mux EQU 1 ;i
V_Mux EQU 0 ;i
LED_1 EQU 7
LED_0 EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
B_Mux EQU 2
A_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU NOT((1 SHL LED_0) + (1 SHL LED_1))
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
LED_2 EQU 6 ;o
C_com EQU 5 ;o
C_pwm EQU 4 ;o
B_com EQU 3 ;o
B_pwm EQU 2 ;o
A_com EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
LED_2 EQU 6
C_com EQU 5
C_pwm EQU 4
B_com EQU 3
B_pwm EQU 2
A_com EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com) + (1 SHL LED_2)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/F.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
A_Mux EQU 3 ;i
B_Mux EQU 2 ;i
C_Mux EQU 1 ;i
V_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
A_Mux EQU 3
B_Mux EQU 2
C_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_com EQU 5 ;o
C_pwm EQU 4 ;o
B_com EQU 3 ;o
B_pwm EQU 2 ;o
A_com EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
; EQU 6
C_com EQU 5
C_pwm EQU 4
B_com EQU 3
B_pwm EQU 2
A_com EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/G.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
C_Mux EQU 1 ;i
B_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
C_Mux EQU 1
B_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_com EQU 5 ;o
C_pwm EQU 4 ;o
B_com EQU 3 ;o
B_pwm EQU 2 ;o
A_com EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
; EQU 6
C_com EQU 5
C_pwm EQU 4
B_com EQU 3
B_pwm EQU 2
A_com EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/H.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
Rcp_In EQU 7 ;i
; EQU 6 ;i
; EQU 5 ;i
; EQU 4 ;i
A_Mux EQU 3 ;i
B_Mux EQU 2 ;i
V_Mux EQU 1 ;i
C_Mux EQU 0 ;i
Rcp_In EQU 7
; EQU 6
; EQU 5
; EQU 4
A_Mux EQU 3
B_Mux EQU 2
V_Mux EQU 1
C_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
A_pwm EQU 6 ;o
B_pwm EQU 5 ;o
C_pwm EQU 4 ;o
; EQU 3 ;i
A_com EQU 2 ;o
B_com EQU 1 ;o
C_com EQU 0 ;o
; EQU 7
A_pwm EQU 6
B_pwm EQU 5
C_pwm EQU 4
; EQU 3
A_com EQU 2
B_com EQU 1
C_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/I.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
B_Mux EQU 2 ;i
A_Mux EQU 1 ;i
V_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
B_Mux EQU 2
A_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -74,14 +74,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
A_com EQU 5 ;o
B_com EQU 4 ;o
C_com EQU 3 ;o
A_pwm EQU 2 ;o
B_pwm EQU 1 ;o
C_pwm EQU 0 ;o
; EQU 7
; EQU 6
A_com EQU 5
B_com EQU 4
C_com EQU 3
A_pwm EQU 2
B_pwm EQU 1
C_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -93,7 +93,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/J.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
LED_2 EQU 7 ;o
LED_1 EQU 6 ;o
LED_0 EQU 5 ;o
Rcp_In EQU 4 ;i
V_Mux EQU 3 ;i
B_Mux EQU 2 ;i
C_Mux EQU 1 ;i
A_Mux EQU 0 ;i
LED_2 EQU 7
LED_1 EQU 6
LED_0 EQU 5
Rcp_In EQU 4
V_Mux EQU 3
B_Mux EQU 2
C_Mux EQU 1
A_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -74,14 +74,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_com EQU 5 ;o
B_com EQU 4 ;o
A_com EQU 3 ;o
C_pwm EQU 2 ;o
B_pwm EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
; EQU 6
C_com EQU 5
B_com EQU 4
A_com EQU 3
C_pwm EQU 2
B_pwm EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -93,7 +93,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/K.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_Mux EQU 5 ;i
; EQU 4 ;i
B_Mux EQU 3 ;i
V_Mux EQU 2 ;i
A_Mux EQU 1 ;i
Rcp_In EQU 0 ;i
; EQU 7
; EQU 6
C_Mux EQU 5
; EQU 4
B_Mux EQU 3
V_Mux EQU 2
A_Mux EQU 1
Rcp_In EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
A_pwm EQU 5 ;o
B_pwm EQU 4 ;o
C_pwm EQU 3 ;o
C_com EQU 2 ;o
B_com EQU 1 ;o
A_com EQU 0 ;o
; EQU 7
; EQU 6
A_pwm EQU 5
B_pwm EQU 4
C_pwm EQU 3
C_com EQU 2
B_com EQU 1
A_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/L.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
B_Mux EQU 1 ;i
C_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
B_Mux EQU 1
C_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -74,14 +74,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
A_com EQU 5 ;o
B_com EQU 4 ;o
C_com EQU 3 ;o
A_pwm EQU 2 ;o
B_pwm EQU 1 ;o
C_pwm EQU 0 ;o
; EQU 7
; EQU 6
A_com EQU 5
B_com EQU 4
C_com EQU 3
A_pwm EQU 2
B_pwm EQU 1
C_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -93,7 +93,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/M.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
A_Mux EQU 7 ;i
C_Mux EQU 6 ;i
V_Mux EQU 5 ;i
B_Mux EQU 4 ;i
Rcp_In EQU 3 ;i
LED_0 EQU 2 ;i
; EQU 1 ;i
; EQU 0 ;i
A_Mux EQU 7
C_Mux EQU 6
V_Mux EQU 5
B_Mux EQU 4
Rcp_In EQU 3
LED_0 EQU 2
; EQU 1
; EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU NOT(1 SHL LED_0)
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
C_com EQU 6 ;o
B_com EQU 5 ;o
A_com EQU 4 ;o
C_pwm EQU 3 ;i
B_pwm EQU 2 ;o
A_pwm EQU 1 ;o
; EQU 0 ;o
; EQU 7
C_com EQU 6
B_com EQU 5
A_com EQU 4
C_pwm EQU 3
B_pwm EQU 2
A_pwm EQU 1
; EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/N.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
B_Mux EQU 2 ;i
A_Mux EQU 1 ;i
V_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
B_Mux EQU 2
A_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_pwm EQU 5 ;o
C_com EQU 4 ;o
B_pwm EQU 3 ;o
B_com EQU 2 ;o
A_pwm EQU 1 ;o
A_com EQU 0 ;o
; EQU 7
; EQU 6
C_pwm EQU 5
C_com EQU 4
B_pwm EQU 3
B_com EQU 2
A_pwm EQU 1
A_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/O.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
C_Mux EQU 1 ;i
B_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
C_Mux EQU 1
B_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_com EQU 5 ;o
C_pwm EQU 4 ;o
B_com EQU 3 ;o
B_pwm EQU 2 ;o
A_com EQU 1 ;o
A_pwm EQU 0 ;o
; EQU 7
; EQU 6
C_com EQU 5
C_pwm EQU 4
B_com EQU 3
B_pwm EQU 2
A_com EQU 1
A_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -101,7 +101,7 @@ ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/P.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
A_Mux EQU 4 ;i
V_Mux EQU 3 ;i
B_Mux EQU 2 ;i
C_Mux EQU 1 ;i
; EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
A_Mux EQU 4
V_Mux EQU 3
B_Mux EQU 2
C_Mux EQU 1
; EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
C_com EQU 6 ;o
B_com EQU 5 ;o
A_com EQU 4 ;o
C_pwm EQU 3 ;i
B_pwm EQU 2 ;o
A_pwm EQU 1 ;o
; EQU 0 ;o
; EQU 7
C_com EQU 6
B_com EQU 5
A_com EQU 4
C_pwm EQU 3
B_pwm EQU 2
A_pwm EQU 1
; EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/Q.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
C_pwm EQU 7 ;o
B_pwm EQU 6 ;o
A_pwm EQU 5 ;o
LED_1 EQU 4 ;i
LED_0 EQU 3 ;i
; EQU 2 ;i
Rcp_In EQU 1 ;i
; EQU 0 ;i
C_pwm EQU 7
B_pwm EQU 6
A_pwm EQU 5
LED_1 EQU 4
LED_0 EQU 3
; EQU 2
Rcp_In EQU 1
; EQU 0
P0_DIGITAL EQU 0FFh
@ -73,14 +73,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
A_Mux EQU 6 ;i
B_Mux EQU 5 ;i
C_Mux EQU 4 ;i
V_Mux EQU 3 ;o
C_com EQU 2 ;o
B_com EQU 1 ;o
A_com EQU 0 ;o
; EQU 7
A_Mux EQU 6
B_Mux EQU 5
C_Mux EQU 4
V_Mux EQU 3
C_com EQU 2
B_com EQU 1
A_com EQU 0
P_ApwmFET EQU P0.A_pwm
@ -139,7 +139,7 @@ ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/R.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
B_Mux EQU 2 ;i
A_Mux EQU 1 ;i
V_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
B_Mux EQU 2
A_Mux EQU 1
V_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -74,14 +74,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
A_com EQU 5 ;o
B_com EQU 4 ;o
C_com EQU 3 ;o
A_pwm EQU 2 ;o
B_pwm EQU 1 ;o
C_pwm EQU 0 ;o
; EQU 7
; EQU 6
A_com EQU 5
B_com EQU 4
C_com EQU 3
A_pwm EQU 2
B_pwm EQU 1
C_pwm EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -93,7 +93,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/S.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
C_Mux EQU 1 ;i
B_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
C_Mux EQU 1
B_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_pwm EQU 5 ;o
C_com EQU 4 ;o
B_pwm EQU 3 ;o
B_com EQU 2 ;o
A_pwm EQU 1 ;o
A_com EQU 0 ;o
; EQU 7
; EQU 6
C_pwm EQU 5
C_com EQU 4
B_pwm EQU 3
B_com EQU 2
A_pwm EQU 1
A_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/T.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
Rcp_In EQU 7 ;i
; EQU 6 ;i
A_Mux EQU 5 ;i
; EQU 4 ;i
B_Mux EQU 3 ;i
V_Mux EQU 2 ;i
C_Mux EQU 1 ;i
; EQU 0 ;i
Rcp_In EQU 7
; EQU 6
A_Mux EQU 5
; EQU 4
B_Mux EQU 3
V_Mux EQU 2
C_Mux EQU 1
; EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_pwm EQU 5 ;o
B_pwm EQU 4 ;o
A_pwm EQU 3 ;o
A_com EQU 2 ;o
B_com EQU 1 ;o
C_com EQU 0 ;o
; EQU 7
; EQU 6
C_pwm EQU 5
B_pwm EQU 4
A_pwm EQU 3
A_com EQU 2
B_com EQU 1
C_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/U.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
A_Mux EQU 7 ;i
C_Mux EQU 6 ;i
V_Mux EQU 5 ;i
B_Mux EQU 4 ;i
Rcp_In EQU 3 ;i
LED_0 EQU 2 ;i
LED_1 EQU 1 ;i
LED_2 EQU 0 ;i
A_Mux EQU 7
C_Mux EQU 6
V_Mux EQU 5
B_Mux EQU 4
Rcp_In EQU 3
LED_0 EQU 2
LED_1 EQU 1
LED_2 EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
C_com EQU 6 ;o
B_com EQU 5 ;o
A_com EQU 4 ;o
C_pwm EQU 3 ;i
B_pwm EQU 2 ;o
A_pwm EQU 1 ;o
; EQU 0 ;o
; EQU 7
C_com EQU 6
B_com EQU 5
A_com EQU 4
C_pwm EQU 3
B_pwm EQU 2
A_pwm EQU 1
; EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/V.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
C_com EQU 7 ;o
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
C_Mux EQU 3 ;i
V_Mux EQU 2 ;i
B_Mux EQU 1 ;i
A_Mux EQU 0 ;i
C_com EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
C_Mux EQU 3
V_Mux EQU 2
B_Mux EQU 1
A_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
@ -73,14 +73,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
A_pwm EQU 6 ;i
A_com EQU 5 ;i
B_pwm EQU 4 ;o
; EQU 3 ;o
; EQU 2 ;o
B_com EQU 1 ;o
C_pwm EQU 0 ;o
; EQU 7
A_pwm EQU 6
A_com EQU 5
B_pwm EQU 4
; EQU 3
; EQU 2
B_com EQU 1
C_pwm EQU 0
P_ApwmFET EQU P1.A_pwm
@ -139,7 +139,7 @@ ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/W.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
Rcp_In EQU 7 ;i
C_Mux EQU 6 ;i
B_Mux EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
; EQU 1 ;i
; EQU 0 ;i
Rcp_In EQU 7
C_Mux EQU 6
B_Mux EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
; EQU 1
; EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
A_pwm EQU 6 ;o
B_pwm EQU 5 ;o
C_pwm EQU 4 ;o
; EQU 3 ;i
; EQU 2 ;i
; EQU 1 ;i
; EQU 0 ;i
; EQU 7
A_pwm EQU 6
B_pwm EQU 5
C_pwm EQU 4
; EQU 3
; EQU 2
; EQU 1
; EQU 0
; pwm outputs start as analog in -> floating
@ -176,7 +176,7 @@ ENDM
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

34
Layouts/Z.inc

@ -54,14 +54,14 @@ ENDIF
;*********************
; PORT 0 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
Rcp_In EQU 5 ;i
; EQU 4 ;i
V_Mux EQU 3 ;i
A_Mux EQU 2 ;i
C_Mux EQU 1 ;i
B_Mux EQU 0 ;i
; EQU 7
; EQU 6
Rcp_In EQU 5
; EQU 4
V_Mux EQU 3
A_Mux EQU 2
C_Mux EQU 1
B_Mux EQU 0
P0_DIGITAL EQU NOT((1 SHL A_Mux) + (1 SHL B_Mux) + (1 SHL C_Mux) + (1 SHL V_Mux))
P0_INIT EQU 0FFh
@ -72,14 +72,14 @@ P0_SKIP EQU 0FFh
;*********************
; PORT 1 definitions *
;*********************
; EQU 7 ;i
; EQU 6 ;i
C_pwm EQU 5 ;o
C_com EQU 4 ;o
B_pwm EQU 3 ;o
B_com EQU 2 ;o
A_pwm EQU 1 ;o
A_com EQU 0 ;o
; EQU 7
; EQU 6
C_pwm EQU 5
C_com EQU 4
B_pwm EQU 3
B_com EQU 2
A_pwm EQU 1
A_com EQU 0
P1_DIGITAL EQU (1 SHL A_pwm) + (1 SHL B_pwm) + (1 SHL C_pwm) + (1 SHL A_com) + (1 SHL B_com) + (1 SHL C_com)
@ -91,7 +91,7 @@ P1_SKIP EQU 0FFh
;*********************
; PORT 2 definitions *
;*********************
DebugPin EQU 0 ;o
DebugPin EQU 0
P2_DIGITAL EQU (1 SHL DebugPin)
P2_PUSHPULL EQU (1 SHL DebugPin)

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