New revision 2.4 with changes in 2.1 to 2.3 (by 4712) integrated

SiLabs/BLHeli.asm

@@ -35,8 +35,8 @@ $NOMOD51
 ; The code adapts itself to one of the three pwm frequencies
 ;
 ; The first lines of the software must be modified according to the chosen environment:
-; - $include ("ESC".inc)		; Select ESC pinout
-; - TAIL		EQU 0		; Choose main or tail mode
+; Uncomment the selected ESC and main/tail mode
+; BESC EQU "ESC"_"mode" 						
 ; 
 ;**** **** **** **** ****
 ; Revision history:
@@ -47,6 +47,16 @@ $NOMOD51
 ;           Added programmable low voltage limit
 ;           Added programmable damped tail mode (only for 1S ESCs)
 ;           Added programmable motor rotation direction
+; - Rev2.1: (minor changes by 4712)
+;		  Added Disable TX Programming by PC Setup Application 
+;		  therfore changed EEPROM_LAYOUT_REVISION = 8					
+;		  Âdded Vdd Monitor as reset source when writing to "EEProm"
+;		  Changed for use of batch file to assemble, link and make hex files	
+; - Rev2.2: (minor changes by 4712)
+;           Added Disable Throttle Re-Arming every motor start by PC Setup Application 
+; - Rev2.3: (minor changes by 4712)
+;           Added bugfixed (2x CLR C before j(n)c operations)thx Steffen!			
+; - Rev2.4: Revisions 2.1 to 2.3 integrated
 ;
 ;**** **** **** **** ****
 ; Up to 8K Bytes of In-System Self-Programmable Flash
@@ -93,15 +103,96 @@ $NOMOD51
 ; Aquisition phase is the final phase, for stabilisation before normal bemf commutation run begins.
 ;
 ;**** **** **** **** ****
+; List of enumerated supported ESCs and modes  (main or tail)
+DP_3A_Main 			EQU 1
+DP_3A_Tail  			EQU 2
+Supermicro_3p5A_Main 	EQU 3
+Supermicro_3p5A_Tail 	EQU 4   
+Turnigy6A_Main 		EQU 5
+Turnigy6A_Tail 		EQU 6   
+XP_3A_Main 			EQU 7
+XP_3A_Tail 			EQU 8
+XP_7A_Main 			EQU 9
+XP_7A_Tail 			EQU 10
+XP_12A_Main 			EQU 11
+XP_12A_Tail 			EQU 12
 
-;$include (DP_3A.inc)			; Select DP 3A pinout
-;$include (Supermicro_3p5A.inc)	; Select Supermicro 3.5A pinout
+;**** **** **** **** ****
+; Select the ESC and mode to use (or unselect all for use with external batch compile file)
+;BESC EQU DP_3A_Main 						
+;BESC EQU DP_3A_Tail  				
+;BESC EQU Supermicro_3p5A_Main
+;BESC EQU Supermicro_3p5A_Tail
+;BESC EQU Turnigy6A_Main 
+;BESC EQU Turnigy6A_Tail 
+;BESC EQU XP_3A_Main 
+;BESC EQU XP_3A_Tail 
+;BESC EQU XP_7A_Main 
+;BESC EQU XP_7A_Tail 
+;BESC EQU XP_12A_Main 
+;BESC EQU XP_12A_Tail 
+
+;**** **** **** **** ****
+; ESC selection statements
+IF BESC == DP_3A_Main
+TAIL 	EQU 	0			; Choose mode. Set to 0 for main motor
+$include (DP_3A.inc)		; Select DP 3A pinout
+ENDIF
+
+IF BESC == DP_3A_Tail
+TAIL 	EQU 	1			; Choose mode. Set to 1 for tail motor
+$include (DP_3A.inc)		; Select DP 3A pinout
+ENDIF
+
+IF BESC == Supermicro_3p5A_Main
+TAIL 	EQU 	0			; Choose mode. Set to 0 for main motor
+$include (Supermicro_3p5A.inc); Select Supermicro 3.5A pinout
+ENDIF
+
+IF BESC == Supermicro_3p5A_Tail
+TAIL 	EQU 	1			; Choose mode. Set to 1 for tail motor
+$include (Supermicro_3p5A.inc); Select Supermicro 3.5A pinout
+ENDIF
+
+IF BESC == Turnigy6A_Main
+TAIL 	EQU 	0			; Choose mode. Set to 0 for main motor
+$include (Turnigy6A.inc)		; Select Turnigy 6A pinout
+ENDIF
+
+IF BESC == Turnigy6A_Tail
+TAIL 	EQU 	1			; Choose mode. Set to 1 for tail motor
+$include (Turnigy6A.inc)		; Select Turnigy 6A pinout
+ENDIF
+
+IF BESC == XP_3A_Main
+TAIL 	EQU 	0			; Choose mode. Set to 0 for main motor
 $include (XP_3A.inc)		; Select XP 3A pinout
-;$include (XP_7A.inc)			; Select XP 7A pinout
-;$include (XP_12A.inc)			; Select XP 12A pinout
-;$include (Turnigy6A.inc)	  	; Select Turnigy 6A pinout
+ENDIF
+
+IF BESC == XP_3A_Tail
+TAIL 	EQU 	1			; Choose mode. Set to 1 for tail motor
+$include (XP_3A.inc)		; Select XP 3A pinout
+ENDIF
+
+IF BESC == XP_7A_Main
+TAIL 	EQU 	0			; Choose mode. Set to 0 for main motor
+$include (XP_7A.inc)		; Select XP 7A pinout
+ENDIF
+
+IF BESC == XP_7A_Tail
+TAIL 	EQU 	1			; Choose mode. Set to 1 for tail motor
+$include (XP_7A.inc)		; Select XP 7A pinout
+ENDIF
+
+IF BESC == XP_12A_Main
+TAIL 	EQU 	0			; Choose mode. Set to 0 for main motor
+$include (XP_12A.inc)		; Select XP 12A pinout
+ENDIF
 
-TAIL 		EQU 	1			; Choose mode. Set to 0 for main motor and 1 for tail motor
+IF BESC == XP_12A_Tail
+TAIL 	EQU 	1			; Choose mode. Set to 1 for tail motor
+$include (XP_12A.inc)		; Select XP 12A pinout
+ENDIF
 
 ;**** **** **** **** ****
 
@@ -129,6 +220,9 @@ ENDIF
 DEFAULT_PGM_TAIL_DIRECTION_REV	EQU 1 ; 1=Normal 	2=Reversed
 DEFAULT_PGM_TAIL_RCP_PWM_POL 		EQU 1 ; 1=Positive 	2=Negative
 
+DEFAULT_ENABLE_TX_PGM 			EQU 1 ; 1=Enabled 	0=Disabled
+DEFAULT_MAIN_REARM_START			EQU 1 ; 1=Enabled 	0=Disabled
+
 ;**** **** **** **** ****
 ; Constant definitions for main
 IF TAIL == 0
@@ -304,6 +398,9 @@ Pgm_Tail_Gain:		DS	1		; Programmed tail gain
 Pgm_Tail_Idle:			DS	1		; Programmed tail idle speed
 Pgm_Startup_Pwr:		DS	1		; Programmed startup power
 
+Pgm_Enable_TX_Pgm:		DS 	1		; Programmed enable/disable value for TX programming
+Pgm_Main_Rearm_Start:	DS 	1		; Programmed enable/disable re-arming main every start 
+
 DSEG AT 80h					
 Tag_Temporary_Storage:	DS	48	; Temporary storage for tags when updating "Eeprom"
 
@@ -311,8 +408,8 @@ Tag_Temporary_Storage:	DS	48	; Temporary storage for tags when updating "Eeprom"
 CSEG AT 1A00h			; "Eeprom" segment
 
 EEPROM_FW_MAIN_REVISION	EQU 	2 	; Main revision of the firmware
-EEPROM_FW_SUB_REVISION	EQU 	0 	; Sub revision of the firmware
-EEPROM_LAYOUT_REVISION	EQU 	7 	; Revision of the EEPROM layout
+EEPROM_FW_SUB_REVISION	EQU 	4 	; Sub revision of the firmware
+EEPROM_LAYOUT_REVISION	EQU 	9 	; Revision of the EEPROM layout
 
 Eep_FW_Main_Revision:	DB	EEPROM_FW_MAIN_REVISION			; EEPROM firmware main revision number
 Eep_FW_Sub_Revision:	DB	EEPROM_FW_SUB_REVISION 			; EEPROM firmware sub revision number
@@ -338,6 +435,9 @@ Eep_Pgm_Input_Pol:		DB	DEFAULT_PGM_TAIL_RCP_PWM_POL		; EEPROM copy of programmed
 Eep_Initialized_L:		DB	05Ah							; EEPROM initialized signature low byte
 Eep_Initialized_H:		DB	0A5h							; EEPROM initialized signature high byte
 ENDIF
+Eep_Enable_TX_Pgm: 		DB 	DEFAULT_ENABLE_TX_PGM 			; EEPROM TX programming enable
+Eep_Main_Rearm_Start:	DB 	DEFAULT_MAIN_REARM_START			; EEPROM re-arming main enable
+Eep_Dummy:			DB	0FFh							; EEPROM address for safety reason
 
 CSEG AT 1A50h
 Eep_ESC_MCU:			DB	"#BLHELI#F330#   "	; Project and MCU tag (16 Bytes)
@@ -2385,6 +2485,8 @@ ELSE
 	setb	Flags2.PGM_RCP_PWM_POL
 	mov	Pgm_Gov_Mode, #3
 ENDIF
+	mov 	Pgm_Enable_TX_Pgm, #DEFAULT_ENABLE_TX_PGM
+	mov 	Pgm_Main_Rearm_Start, #DEFAULT_MAIN_REARM_START 
 	ret
 
 
@@ -2411,6 +2513,9 @@ reset:
 	anl	PCA0MD, #NOT(40h)	; Clear watchdog enable bit
 	; Initialize stack
 	mov	SP, #0c0h			; Stack = 64 upper bytes of RAM
+	; Initialize VDD monitor
+	orl	VDM0CN, #080h    	; Enable the VDD monitor
+	call	wait1ms			; Wait at least 100us
 	; Set clock frequency
 	orl	OSCICN, #03h		; Set clock divider to 1
 	mov	A, OSCICL				
@@ -2530,7 +2635,11 @@ arming_start:
 	jc	program_by_tx_checked	; No - branch
 
 IF TX_PGM == 1
-	jmp program_by_tx			; Yes - start programming mode entry
+	mov 	A, Pgm_Enable_TX_Pgm	; Yes - start programming mode entry if enabled
+	clr	C
+	subb	A, #1				; Is TX programming enabled?
+	jc 	program_by_tx_checked	; No - branch
+	jmp	program_by_tx			; Yes - enter programming mode
 ENDIF
 
 program_by_tx_checked:
@@ -2587,19 +2696,6 @@ init_start:
 	mov	Flags0, A				; Clear flags0
 	mov	Rcp_Stop_Cnt, A		; Set RC pulse stop count to zero
 	call initialize_all_timings	; Initialize timing
-
-;stsk
-setb	Flags1.RUN_PWM_OFF_DAMPED	; Set damped operation
-call comm1comm2				; Initialize commutation
-call comm2comm3				; Initialize commutation
-runbrushed:
-call wait1ms
-clr	C
-mov	A, Rcp_Stop_Cnt			; Load stop RC pulse counter value
-subb	A, #RCP_STOP_LIMIT			; Is number of stop RC pulses above limit?
-jc	runbrushed
-jmp	run_to_wait_for_power_on		; Yes, go back to wait for poweron
-
 	;**** **** **** **** ****
 	; Settle mode beginning
 	;**** **** **** **** **** 
@@ -2987,7 +3083,15 @@ run_to_wait_for_power_on:
 IF TAIL == 1
 	jmp	wait_for_power_on		; Tail - Go back to wait for power on
 ELSE
-	jmp	validate_rcp_start		; Main - Go back to validate RC pulse
+	mov 	A, Pgm_Main_Rearm_Start
+	clr	C
+	subb	A, #1				; Is re-armed start enabled?
+	jc 	jmp_wait_for_power_on	; No - do like tail and start immediately
+
+	jmp	validate_rcp_start		; Yes - go back to validate RC pulse
+
+jmp_wait_for_power_on:
+	jmp	wait_for_power_on		; Go back to wait for power on
 ENDIF
 
 

SiLabs/BLHeliTxPgm.inc

@@ -57,6 +57,7 @@ read_eeprom_byte:
 write_eeprom_byte:
 	orl	PSCTL, #01h			; Set the PSWE bit
 	anl	PSCTL, #0FDh			; Clear the PSEE bit
+	mov 	RSTSRC, #02h   		; Set VDD monitor as a reset source (PORSF)                                
 	mov	FLKEY, #0A5h			; First key code
 	mov	FLKEY, #0F1h			; Second key code
 	mov	A, Temp1				; Load value to be written
@@ -76,6 +77,7 @@ clear_eeprom_signature:
 	; Erase flash
 	orl	PSCTL, #02h			; Set the PSEE bit
 	orl	PSCTL, #01h			; Set the PSWE bit
+	mov 	RSTSRC, #02h   		; Set VDD monitor as a reset source (PORSF)                                
 	mov	FLKEY, #0A5h			; First key code
 	mov	FLKEY, #0F1h			; Second key code
 	mov	DPTR, #Eep_Initialized_L	
@@ -235,6 +237,16 @@ ELSE
 
 	mov	Pgm_Gov_Mode, #3
 ENDIF
+	mov	DPTR, #Eep_Enable_TX_Pgm
+	call read_eeprom_byte
+	mov	Pgm_Enable_TX_Pgm, Temp1
+
+	mov	DPTR, #Eep_Main_Rearm_Start
+	call read_eeprom_byte
+	mov	Pgm_Main_Rearm_Start, Temp1
+
+	mov	DPTR, #Eep_Dummy 			; Set pointer to uncritical area
+
 	jmp	read_eeprom_exit
 
 read_eeprom_store_defaults:
@@ -381,8 +393,17 @@ ELSE
 	mov	Temp1, #2
 	call write_eeprom_byte
 ENDIF
+	mov	DPTR, #Eep_Enable_TX_Pgm
+	mov	Temp1, Pgm_Enable_TX_Pgm
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Main_Rearm_Start
+	mov	Temp1, Pgm_Main_Rearm_Start
+	call write_eeprom_byte
+
 	call	write_tags
 	call write_eeprom_signature
+	mov	DPTR, #Eep_Dummy 			; Set pointer to uncritical area
 	ret	
 
 
@@ -663,6 +684,7 @@ func_paraval_wait:
 	call	store_all_in_eeprom		; Store all values in EEPROM
 	call success_beep			; Beep success
 	clr	EA					; Disable all interrupts
+	mov 	RSTSRC, #00h   		; Clear VDD monitor as a reset source (PORSF)                                
 	orl	RSTSRC, #10h			; Generate hardware reset
 	call wait1s
 
@@ -738,6 +760,7 @@ ENDIF
 
 program_by_tx_exit:
 	clr	EA					; Disable all interrupts
+	mov 	RSTSRC, #00h   		; Clear VDD monitor as a reset source (PORSF)                                
 	orl	RSTSRC, #10h			; Generate hardware reset
 	call wait1s