Initial commit of BLHeli

Matching published Rev2.0 of SiLabs and Rev3.0 of Atmel

Add GPL License file.

Atmel/BLHeliTxPgm.inc

@@ -0,0 +1,625 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; BLHeliTxPgm Atmel
+;                                                         
+;**** **** **** **** ****
+
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read eeprom byte routine
+;
+; Assumes data in Temp1 and address in X 
+; Also assumes address high byte to be zero
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_eeprom_byte:
+	; Wait for completion of previous write
+	Check_Eeprom_Ready
+	rjmp read_eeprom_byte
+
+	; Set up address in address register
+	Set_Eeprom_Address Temp2, Temp3
+	; Start eeprom read
+	sbi  EECR, EERE
+	in 	Temp1, EEDR			
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write eeprom byte routine
+;
+; Assumes data in Temp1 and address in Temp2/Temp3 
+; Also assumes address high byte to be zero
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_eeprom_byte:
+	; Wait for completion of previous write
+	Check_Eeprom_Ready
+	rjmp write_eeprom_byte   
+
+	; Set up address in address register
+	out 	EEDR, Temp1		
+	Set_Eeprom_Address Temp2, Temp3
+	; Set write enables and start writing
+	cli				; Disable interrupts	
+	Start_Eeprom_Write
+	sei				; Enable interrupts
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Clear eeprom signature routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+clear_eeprom_signature:	
+	ldi	Temp2, low(Eep_Initialized_L)
+	ldi	Temp3, high(Eep_Initialized_L)
+	ldi	Temp1, 0xFF
+	rcall write_eeprom_byte
+
+	ldi	Temp2, low(Eep_Initialized_H)
+	ldi	Temp3, high(Eep_Initialized_H)
+	ldi	Temp1, 0xFF
+	rcall write_eeprom_byte
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write eeprom signature routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_eeprom_signature:	
+.if TAIL == 0
+	ldi	Temp2, low(Eep_Initialized_L)
+	ldi	Temp3, high(Eep_Initialized_L)
+	ldi	Temp1, 0xA5
+	rcall write_eeprom_byte
+
+	ldi	Temp2, low(Eep_Initialized_H)
+	ldi	Temp3, high(Eep_Initialized_H)
+	ldi	Temp1, 0x5A
+	rcall write_eeprom_byte
+.else
+	ldi	Temp2, low(Eep_Initialized_L)
+	ldi	Temp3, high(Eep_Initialized_L)
+	ldi	Temp1, 0x5A
+	rcall write_eeprom_byte
+
+	ldi	Temp2, low(Eep_Initialized_H)
+	ldi	Temp3, high(Eep_Initialized_H)
+	ldi	Temp1, 0xA5
+	rcall write_eeprom_byte
+.endif
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read eeprom perameters routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_eeprom_parameters:	
+.if TAIL == 0
+	; Check initialized signature
+	ldi	Temp2, low(Eep_Initialized_L)
+	ldi	Temp3, high(Eep_Initialized_L)
+	rcall read_eeprom_byte
+	cpi	Temp1, 0xA5
+	brne	read_eeprom_store_defaults
+
+	ldi	Temp2, low(Eep_Initialized_H)
+	ldi	Temp3, high(Eep_Initialized_H)
+	rcall read_eeprom_byte
+	cpi	Temp1, 0x5A
+	brne	read_eeprom_store_defaults
+
+	; Read eeprom
+	ldi	Temp2, low(Eep_Pgm_Gov_P_Gain)
+	ldi	Temp3, high(Eep_Pgm_Gov_P_Gain)
+	rcall read_eeprom_byte
+	sts	Pgm_Gov_P_Gain, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Gov_I_Gain)
+	ldi	Temp3, high(Eep_Pgm_Gov_I_Gain)
+	rcall read_eeprom_byte
+	sts	Pgm_Gov_I_Gain, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Gov_Mode)
+	ldi	Temp3, high(Eep_Pgm_Gov_Mode)
+	rcall read_eeprom_byte
+	sts	Pgm_Gov_Mode, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Startup_Pwr)
+	ldi	Temp3, high(Eep_Pgm_Startup_Pwr)
+	rcall read_eeprom_byte
+	sts	Pgm_Startup_Pwr, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Pwm_Freq)
+	ldi	Temp3, high(Eep_Pgm_Pwm_Freq)
+	rcall read_eeprom_byte
+	sbr	Flags2, (1<<PGM_PWM_HIGH_FREQ)
+	sbrc	Temp1, 1
+	cbr	Flags2, (1<<PGM_PWM_HIGH_FREQ)
+
+	ldi	Temp2, low(Eep_Pgm_Input_Pol)
+	ldi	Temp3, high(Eep_Pgm_Input_Pol)
+	rcall read_eeprom_byte
+	cbr	Flags2, (1<<PGM_RCP_PWM_POL)
+	sbrc	Temp1, 1
+	sbr	Flags2, (1<<PGM_RCP_PWM_POL)
+.else
+	; Check initialized signature
+	ldi	Temp2, low(Eep_Initialized_L)
+	ldi	Temp3, high(Eep_Initialized_L)
+	rcall read_eeprom_byte
+	cpi	Temp1, 0x5A
+	brne	read_eeprom_store_defaults
+
+	ldi	Temp2, low(Eep_Initialized_H)
+	ldi	Temp3, high(Eep_Initialized_H)
+	rcall read_eeprom_byte
+	cpi	Temp1, 0xA5
+	brne	read_eeprom_store_defaults
+
+	; Read eeprom
+	ldi	Temp2, low(Eep_Pgm_Tail_Gain)
+	ldi	Temp3, high(Eep_Pgm_Tail_Gain)
+	rcall read_eeprom_byte
+	sts	Pgm_Tail_Gain, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Tail_Idle)
+	ldi	Temp3, high(Eep_Pgm_Tail_Idle)
+	rcall read_eeprom_byte
+	sts	Pgm_Tail_Idle, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Startup_Pwr)
+	ldi	Temp3, high(Eep_Pgm_Startup_Pwr)
+	rcall read_eeprom_byte
+	sts	Pgm_Startup_Pwr, Temp1
+
+	ldi	Temp2, low(Eep_Pgm_Pwm_Freq)
+	ldi	Temp3, high(Eep_Pgm_Pwm_Freq)
+	rcall read_eeprom_byte
+	sbr	Flags2, (1<<PGM_PWM_HIGH_FREQ)
+	sbrc	Temp1, 1
+	cbr	Flags2, (1<<PGM_PWM_HIGH_FREQ)
+
+	ldi	Temp2, low(Eep_Pgm_Input_Pol)
+	ldi	Temp3, high(Eep_Pgm_Input_Pol)
+	rcall read_eeprom_byte
+	cbr	Flags2, (1<<PGM_RCP_PWM_POL)
+	sbrc	Temp1, 1
+	sbr	Flags2, (1<<PGM_RCP_PWM_POL)
+
+	ldi	Temp1, 3
+	sts	Pgm_Gov_Mode, Temp1
+.endif
+	rjmp	read_eeprom_exit
+
+read_eeprom_store_defaults:
+	rcall set_default_parameters	
+	rcall store_eeprom_defaults	
+read_eeprom_exit:
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Store default parameter value in EEPROM routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+store_eeprom_defaults:
+	rcall clear_eeprom_signature
+.if TAIL == 0
+	ldi	Temp1, 1
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Gov_P_Gain
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 2
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Gov_I_Gain
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 3
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Gov_Mode
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 4
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Startup_Pwr
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 5
+	sts	Tx_Pgm_Func_No, Temp1
+	ldi	Temp1, 1
+	sbrs	Flags2, PGM_PWM_HIGH_FREQ
+	ldi	Temp1, 2
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 6
+	sts	Tx_Pgm_Func_No, Temp1
+	ldi	Temp1, 1
+	sbrc	Flags2, PGM_RCP_PWM_POL
+	ldi	Temp1, 2
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	rcall write_eeprom_signature
+.else
+	ldi	Temp1, 1
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Tail_Gain
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 2
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Tail_Idle
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 3
+	sts	Tx_Pgm_Func_No, Temp1
+	lds	Temp1, Pgm_Startup_Pwr
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 4
+	sts	Tx_Pgm_Func_No, Temp1
+	ldi	Temp1, 1
+	sbrs	Flags2, PGM_PWM_HIGH_FREQ
+	ldi	Temp1, 2
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	ldi	Temp1, 5
+	sts	Tx_Pgm_Func_No, Temp1
+	ldi	Temp1, 1
+	sbrc	Flags2, PGM_RCP_PWM_POL
+	ldi	Temp1, 2
+	sts	Tx_Pgm_Paraval_No, Temp1
+	rcall store_in_eeprom
+
+	rcall write_eeprom_signature
+.endif
+	ret	
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Store new parameter value in EEPROM routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+store_in_eeprom:	
+	lds	Temp4, Tx_Pgm_Func_No	; Function no
+	lds	Temp1, Tx_Pgm_Paraval_No	; Parameter value no
+.if TAIL == 0
+	cpi	Temp4, 1
+	breq	store_main_func_1
+	cpi	Temp4, 2
+	breq	store_main_func_2
+	cpi	Temp4, 3
+	breq	store_main_func_3
+	cpi	Temp4, 4
+	breq	store_main_func_4
+	cpi	Temp4, 5
+	breq	store_main_func_5
+	cpi	Temp4, 6
+	breq	store_main_func_6
+
+store_main_func_1:
+	ldi	Temp2, low(Eep_Pgm_Gov_P_Gain)
+	ldi	Temp3, high(Eep_Pgm_Gov_P_Gain)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_main_func_2:
+	ldi	Temp2, low(Eep_Pgm_Gov_I_Gain)
+	ldi	Temp3, high(Eep_Pgm_Gov_I_Gain)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_main_func_3:
+	ldi	Temp2, low(Eep_Pgm_Gov_Mode)
+	ldi	Temp3, high(Eep_Pgm_Gov_Mode)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_main_func_4:
+	ldi	Temp2, low(Eep_Pgm_Startup_Pwr)
+	ldi	Temp3, high(Eep_Pgm_Startup_Pwr)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_main_func_5:
+	ldi	Temp2, low(Eep_Pgm_Pwm_Freq)
+	ldi	Temp3, high(Eep_Pgm_Pwm_Freq)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_main_func_6:
+	ldi	Temp2, low(Eep_Pgm_Input_Pol)
+	ldi	Temp3, high(Eep_Pgm_Input_Pol)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+.else
+	cpi	Temp4, 1
+	breq	store_tail_func_1
+	cpi	Temp4, 2
+	breq	store_tail_func_2
+	cpi	Temp4, 3
+	breq	store_tail_func_3
+	cpi	Temp4, 4
+	breq	store_tail_func_4
+	cpi	Temp4, 5
+	breq	store_tail_func_5
+
+store_tail_func_1:
+	ldi	Temp2, low(Eep_Pgm_Tail_Gain)
+	ldi	Temp3, high(Eep_Pgm_Tail_Gain)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_tail_func_2:
+	ldi	Temp2, low(Eep_Pgm_Tail_Idle)
+	ldi	Temp3, high(Eep_Pgm_Tail_Idle)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_tail_func_3:
+	ldi	Temp2, low(Eep_Pgm_Startup_Pwr)
+	ldi	Temp3, high(Eep_Pgm_Startup_Pwr)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_tail_func_4:
+	ldi	Temp2, low(Eep_Pgm_Pwm_Freq)
+	ldi	Temp3, high(Eep_Pgm_Pwm_Freq)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+
+store_tail_func_5:
+	ldi	Temp2, low(Eep_Pgm_Input_Pol)
+	ldi	Temp3, high(Eep_Pgm_Input_Pol)
+	rcall write_eeprom_byte
+	rjmp	store_in_eeprom_exit
+.endif
+
+store_in_eeprom_exit:
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Wait 1 second routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+wait1s:
+	ldi	Temp1, 5
+	mov	Temp5, Temp1
+wait1s_loop:
+	rcall wait200ms
+	dec	Temp5
+	brne	wait1s_loop
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Success beep routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+success_beep:
+	cli						; Disable all interrupts
+	rcall beep_f1
+	rcall beep_f2
+	rcall beep_f3
+	rcall beep_f4
+	rcall wait10ms
+	rcall beep_f1
+	rcall beep_f2
+	rcall beep_f3
+	rcall beep_f4
+	rcall wait10ms
+	rcall beep_f1
+	rcall beep_f2
+	rcall beep_f3
+	rcall beep_f4
+	sei						; Enable all interrupts
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Function and parameter value beep routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+function_paraval_beep:
+	lds	Temp5, Tx_Pgm_Func_No	; Function no
+	lds	Temp6, Tx_Pgm_Paraval_No	; Parameter value no
+	cli						; Disable all interrupts
+function_beep:
+	rcall beep_f1				
+	rcall beep_f1
+	rcall beep_f1
+	rcall wait10ms
+	dec	Temp5
+	brne	function_beep
+paraval_beep:
+	rcall beep_f4
+	rcall wait10ms
+	dec	Temp6
+	brne	paraval_beep
+	sei						; Enable all interrupts
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Program by TX routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+program_by_tx:	
+	; Start programming mode entry sequence by waiting for low RC pulse
+	cli						; Disable all interrupts
+	rcall beep_f4
+	sei						; Enable all interrupts
+	rcall wait100ms
+	lds	Temp1, New_Rcp			; Load new RC pulse value
+	cpi	Temp1, RCP_STOP		; Below stop?
+	brsh	program_by_tx			; No - start over
+
+	; Continue programming mode entry sequence by waiting for high RC pulse
+wait_for_rc_pulse_max:
+	cli						; Disable all interrupts
+	rcall beep_f1
+	rcall wait10ms
+	rcall beep_f1
+	sei						; Enable all interrupts
+	rcall wait100ms
+	lds	Temp1, New_Rcp			; Load new RC pulse value
+	cpi	Temp1, RCP_MAX			; Above max?
+	brlo	wait_for_rc_pulse_max	; No - start over
+
+	; Programming mode entry beeps
+	rcall success_beep
+	rcall wait1s
+	rcall wait1s
+
+	; Start at function 1, parameter value 1
+	ldi	Temp1, 1
+	sts	Tx_Pgm_Func_No, Temp1
+paraval_no_entry:
+	ldi	Temp1, 1
+	sts	Tx_Pgm_Paraval_No, Temp1
+beep_no_entry:
+	ldi	Temp1, 0
+	sts	Tx_Pgm_Beep_No, Temp1
+func_paraval:
+	rcall function_paraval_beep
+	ldi	Temp1, 5				; Wait is 5x 200ms
+	mov	Temp5, Temp1
+func_paraval_wait:
+	rcall wait200ms
+	lds	Temp1, New_Rcp			; Load new rc pulse value
+	cpi	Temp1, RCP_STOP		; Below stop?
+	brsh	func_paraval_cont_wait	; No - branch
+
+	rcall clear_eeprom_signature	; Clear signature
+	rcall store_in_eeprom		; Yes - store new value in EEPROM
+	rcall write_eeprom_signature	; Write signature
+	rcall success_beep			; Beep success
+	Enable_Watchdog Temp1		; Generate hardware reset from watchdog
+	rcall wait1s
+
+func_paraval_cont_wait:
+	dec	Temp5
+	brne	func_paraval_wait
+	lds	Temp1, Tx_Pgm_Beep_No	; Load and check number of beeps
+	inc	Temp1
+	sts	Tx_Pgm_Beep_No, Temp1
+	cpi	Temp1, 3				; Three beeps done?
+	brsh	paraval_next			; Yes - Next parameter value
+
+	rjmp	func_paraval			; No - go back
+
+paraval_next:					
+	rcall wait1s
+	lds	Temp1, Tx_Pgm_Paraval_No	; Parameter value no
+	inc	Temp1
+	sts	Tx_Pgm_Paraval_No, Temp1
+	ldi	Temp2, 5				; Default 5 parameter values
+.if TAIL == 0
+	lds	Temp1, Tx_Pgm_Func_No
+	cpi	Temp1, 3				; Function 3?
+	brne paraval_end_a			; No - branch
+	ldi	Temp2, 3				; Yes - set max parameter values
+paraval_end_a:
+	lds	Temp1, Tx_Pgm_Func_No
+	cpi	Temp1, 5				; Function below 5?
+	brlo paraval_end_b			; Yes - branch
+	ldi	Temp2, 2				; No - set max parameter values
+paraval_end_b:
+.else
+	lds	Temp1, Tx_Pgm_Func_No
+	cpi	Temp1, 4				; Function below 4?
+	brlo paraval_end_a			; Yes - branch
+	ldi	Temp2, 2				; No - set max parameter values
+paraval_end_a:
+.endif
+	inc	Temp2
+	lds	Temp1, Tx_Pgm_Paraval_No	
+	cp	Temp1, Temp2
+	brsh function_next			; Last parameter value?
+	rjmp	beep_no_entry			; No - go back
+
+function_next:					; Yes - Next function value
+	rcall wait1s
+	rcall wait1s
+	lds	Temp1, Tx_Pgm_Func_No	; Function value no
+	inc	Temp1
+	sts	Tx_Pgm_Func_No, Temp1
+.if TAIL == 0
+	cpi	Temp1, 7				; Main has 6 functions
+.else
+	cpi	Temp1, 6				; Tail has 5 functions
+.endif
+	brsh program_by_tx_exit		; Last function value?
+	rjmp	paraval_no_entry		; No - go back
+
+program_by_tx_exit:
+	Enable_Watchdog Temp1		; Generate hardware reset from watchdog
+	rcall wait1s
+

Atmel/Feigao6.inc

@@ -0,0 +1,315 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device Atmega8
+;*********************
+.include "m8def.inc"
+
+;**** **** **** **** ****
+; Fuses must be set to internal calibrated oscillator = 8Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+.equ ADC_LIMIT_L	= 211	; Power supply measurement ADC value for which main motor power is limited (low byte)
+.equ ADC_LIMIT_H	= 0		; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+;*********************
+; PORT D definitions *
+;*********************  
+;.equ			= 7	;i
+.equ	Comp_Com		= 6	;i Comparator common input (AIN0)
+.equ	ApFET		= 5	;o
+.equ	CpFET		= 4	;o
+.equ	BpFET		= 3	;o
+.equ	Rcp_In		= 2	;i RC pulse input
+;.equ       		= 1	;i
+;.equ       		= 0	;i
+
+.equ	INIT_PD		= 0
+.equ	DIR_PD		= (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+
+.MACRO Read_Rcp_Int
+	in	@0, PIND
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+.MACRO Read_Rcp_Icp_Int
+	in	@0, PINB
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+
+.MACRO Rcp_Int_Enable
+	ldi @0, (1<<INT0)	; Enable ext0int
+	out	GICR, @0
+.ENDMACRO
+.MACRO Rcp_Int_Disable
+	ldi @0, 0			; Disable ext0int
+	out	GICR, @0
+.ENDMACRO
+.MACRO Rcp_Int_First
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	out	MCUCR, @0		
+.ENDMACRO
+.MACRO Rcp_Int_Second
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	out	MCUCR, @0		
+.ENDMACRO
+.MACRO Clear_Int_Flag
+	clr 	@0
+	sbr @0, (1<<INTF0)	; Clear ext0int flag
+	out	GIFR, @0		
+.ENDMACRO
+
+.MACRO ApFET_on
+	sbi	PORTD,5
+.ENDMACRO
+.MACRO ApFET_off
+	cbi	PORTD,5
+.ENDMACRO
+.MACRO CpFET_on
+	sbi	PORTD,4
+.ENDMACRO
+.MACRO CpFET_off
+	cbi	PORTD,4
+.ENDMACRO
+.MACRO BpFET_on
+	sbi	PORTD,3
+.ENDMACRO
+.MACRO BpFET_off
+	cbi	PORTD,3
+.ENDMACRO
+.MACRO All_pFETs_Off
+	in	@0, PORTD
+	cbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+.MACRO All_pFETs_On
+	in	@0, PORTD
+	sbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+
+
+;*********************
+; PORT C definitions *
+;*********************
+;.equ    	  		= 7	; ADC7
+;.equ    	  		= 6	; ADC6
+.equ	Mux_A		= 5	; Phase A input
+.equ	Mux_C		= 4	; Phase C input
+;.equ    	  		= 3	; ADC3
+.equ Mux_B 		= 2	; Phase B input
+;.equ 	 		= 1 	; ADC1
+;.equ 			= 0 	; ADC0
+
+.equ	INIT_PC		= 0
+.equ	DIR_PC		= 0
+
+.MACRO Comp_Init
+   	in  @0, SFIOR		; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	out  SFIOR, @0
+   	cbi  ADCSRA, ADEN  	; Disable ADC
+.ENDMACRO
+.MACRO Set_Comp_Phase_A
+   	ldi  @0, Mux_A  	; Set comparator multiplexer to phase A
+   	out  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_B
+   	ldi  @0, Mux_B  	; Set comparator multiplexer to phase B
+   	out  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_C
+   	ldi  @0, Mux_C  	; Set comparator multiplexer to phase C
+   	out  ADMUX, @0
+.ENDMACRO
+.MACRO Read_Comp_Out
+	in	@0, ACSR		; Read comparator output
+.ENDMACRO
+
+
+;*********************
+; PORT B definitions *
+;*********************
+;.equ			= 7
+;.equ			= 6
+;.equ			= 5 	(sck stk200 interface) 
+.equ	DebugPin		= 4	;(miso stk200 interface)
+;.equ			= 3	(mosi stk200 interface) 
+.equ	AnFET		= 2
+.equ	CnFET		= 1
+.equ	BnFET		= 0
+
+.equ	INIT_PB		= 0
+.equ	DIR_PB		= (1<<DebugPin)+(1<<AnFET)+(1<<BnFET)+(1<<CnFET)
+
+.MACRO AnFET_on
+	sbi	PORTB,2
+.ENDMACRO
+.MACRO AnFET_off
+	cbi	PORTB,2
+.ENDMACRO
+.MACRO CnFET_on
+	sbi	PORTB,1
+.ENDMACRO
+.MACRO CnFET_off
+	cbi	PORTB,1
+.ENDMACRO
+.MACRO BnFET_on
+	sbi	PORTB,0
+.ENDMACRO
+.MACRO BnFET_off
+	cbi	PORTB,0
+.ENDMACRO
+.MACRO All_nFETs_Off
+	in	@0, PORTB
+	cbr	@0, (1<<AnFET)+(1<<BnFET)+(1<<CnFET)
+	out	PORTB, @0
+.ENDMACRO
+
+;**********************
+; MCU specific macros *
+;**********************
+.MACRO Disable_Watchdog
+	cli					; Disable interrupts
+	wdr					; Reset watchdog timer
+	in @0, WDTCR			; Write logical one to WDCE and WDE
+	ori @0, (1<<WDCE)|(1<<WDE)
+	out WDTCR, @0
+	ldi @0, (0<<WDE)		; Turn off WDT
+	out WDTCR, @0
+.ENDMACRO
+.MACRO Enable_Watchdog
+	ldi @0, (1<<WDE)		; Turn on WDT
+	sts WDTCR, @0
+.ENDMACRO
+
+.MACRO Initialize_MCU
+.ENDMACRO
+
+.MACRO Interrupt_Table_Definition
+	rjmp reset
+	rjmp ext_int0	; ext_int0 
+	nop			; ext_int1
+	nop 			; t2oc_int
+	rjmp t2ovfl_int; t2ovfl_int
+	nop			; icp1_int	
+	rjmp t1oca_int	; t1oca_int
+	nop			; t1ocb_int
+	rjmp t1ovfl_int; t1ovfl_int
+	rjmp t0ovfl_int; t0ovfl_int
+	nop			; spi_int
+	nop			; urxc
+	nop			; udre
+	nop			; utxc
+;	nop			; adc_int
+;	nop			; eep_int
+;	nop			; aci_int
+;	nop			; wire2_int
+;	nop			; spmc_int
+.ENDMACRO
+
+.MACRO Initialize_Interrupts
+	ldi	Temp1, (1<<TOIE0)+(1<<TOIE1)+(1<<OCIE1A)+(1<<TOIE2)
+	out	TIFR, Temp1	; Clear interrupts
+	out	TIMSK, Temp1	; Enable interrupts
+.ENDMACRO
+
+.MACRO Initialize_Adc
+  	in  	Temp1, ADCSRA	; Set ADCSRA register (1MHz clock)
+  	sbr  Temp1, (1<<ADPS1) 	
+  	sbr  Temp1, (1<<ADPS0) 	
+   	out  ADCSRA, Temp1
+.ENDMACRO
+.MACRO Start_Adc
+	ldi	Temp1, (1<<REFS1)+(1<<REFS0)
+	out	ADMUX, Temp1	; Set ADMUX register (2.56V reference, left adj result, input 0)
+  	in  	@0, ADCSRA	
+  	sbr  @0, (1<<ADEN) 	; Enable ADC	
+  	sbr  @0, (1<<ADSC) 	; Start ADC conversion	
+   	out  ADCSRA, @0
+.ENDMACRO
+.MACRO Get_Adc_Status
+  	in  	@0, ADCSRA	
+.ENDMACRO
+.MACRO Read_Adc_Result
+  	in  	@0, ADCL	
+  	in  	@1, ADCH	
+.ENDMACRO
+.MACRO Stop_Adc
+  	in  	@0, ADCSRA	
+  	cbr  @0, (1<<ADEN) 	; Disable ADC	
+   	out  ADCSRA, @0
+.ENDMACRO
+
+.MACRO Set_Timer0_CS0
+	out	TCCR0, @0
+.ENDMACRO
+.MACRO Set_Timer1_CS1
+	out	TCCR1B, @0
+.ENDMACRO
+.MACRO Set_Timer2_CS2
+	out	TCCR2, @0
+.ENDMACRO
+
+.MACRO Read_TCNT1L
+	in	@0, TCNT1L
+.ENDMACRO
+.MACRO Read_TCNT1H
+	in	@0, TCNT1H
+.ENDMACRO
+.MACRO Set_OCR1AL
+	out	OCR1AL, @0
+.ENDMACRO
+.MACRO Set_OCR1AH
+	out	OCR1AH, @0
+.ENDMACRO
+
+.MACRO Set_TCNT2
+	out	TCNT2, @0
+.ENDMACRO
+
+.MACRO Check_Eeprom_Ready
+	sbic	EECR, EEWE
+.ENDMACRO
+.MACRO Set_Eeprom_Address
+	out  EEARL, @0
+	out  EEARH, @1
+.ENDMACRO
+.MACRO Start_Eeprom_Write
+	sbi  EECR, EEMWE
+	sbi  EECR, EEWE
+.ENDMACRO

Atmel/HC5A1SA48V.inc

@@ -0,0 +1,350 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device Atmega48V
+;*********************
+.include "m48def.inc"
+
+;**** **** **** **** ****
+; Fuses must be set to internal calibrated oscillator = 8Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+.equ ADC_LIMIT_L	= 254	; Power supply measurement ADC value for which main motor power is limited (low byte)
+.equ ADC_LIMIT_H	= 0		; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+;*********************
+; PORT D definitions *
+;*********************  
+.equ	Mux_A		= 7	;i Phase A input
+.equ	Comp_Com		= 6	;i Comparator common input (AIN0)
+;.equ			= 5	
+;.equ			= 4	
+.equ	ApFET		= 3	;o
+.equ	Rcp_In		= 2	;i RC pulse input
+.equ BpFET      	= 1	;o
+.equ CpFET      	= 0	;o
+
+.equ	INIT_PD		= 0
+.equ	DIR_PD		= (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+
+.MACRO Read_Rcp_Int
+	in	@0, PIND
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+.MACRO Read_Rcp_Icp_Int
+	in	@0, PINB
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+
+.MACRO Rcp_Int_Enable
+	ldi @0, (1<<INT0)	; Enable ext0int
+	out	EIMSK, @0
+.ENDMACRO
+.MACRO Rcp_Int_Disable
+	ldi @0, 0			; Disable ext0int
+	out	EIMSK, @0
+.ENDMACRO
+.MACRO Rcp_Int_First
+	sbrs	Flags2, PGM_RCP_PWM_POL		; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	sbrc Flags2, PGM_RCP_PWM_POL		; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	sts	EICRA, @0		
+.ENDMACRO
+.MACRO Rcp_Int_Second
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	sts	EICRA, @0		
+.ENDMACRO
+.MACRO Clear_Int_Flag
+	clr 	@0
+	sbr @0, (1<<INTF0)	; Clear ext0int flag
+	out	EIFR, @0		
+.ENDMACRO
+
+.MACRO ApFET_on
+	sbi	PORTD,3
+.ENDMACRO
+.MACRO ApFET_off
+	cbi	PORTD,3
+.ENDMACRO
+.MACRO BpFET_on
+	sbi	PORTD,1
+.ENDMACRO
+.MACRO BpFET_off
+	cbi	PORTD,1
+.ENDMACRO
+.MACRO CpFET_on
+	sbi	PORTD,0
+.ENDMACRO
+.MACRO CpFET_off
+	cbi	PORTD,0
+.ENDMACRO
+.MACRO All_pFETs_Off
+	in	@0, PORTD
+	cbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+.MACRO All_pFETs_On
+	in	@0, PORTD
+	sbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+
+
+;*********************
+; PORT C definitions *
+;*********************
+;.equ    	  		= 7	; ADC7
+;.equ    	  		= 6	; ADC6
+;.equ    	  		= 5	; ADC5
+;.equ    	  		= 4	; ADC4
+.equ Mux_B 		= 3	; Phase B input
+.equ	Mux_C		= 2	; Phase C input
+;.equ 	 		= 1 	; ADC1
+;.equ 			= 0 	; ADC0
+
+.equ	INIT_PC		= 0
+.equ	DIR_PC		= 0
+
+.MACRO Comp_Init
+  	lds  @0, ADCSRA	; Disable ADC
+  	cbr  @0, (1<<ADEN) 	
+   	sts  ADCSRA, @0
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_A
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Disable
+   	cbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_B
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+  	ldi  @0, Mux_B  	; Set comparator multiplexer to phase B
+   	sts  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_C
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+  	ldi  @0, Mux_C  	; Set comparator multiplexer to phase C
+   	sts  ADMUX, @0
+.ENDMACRO
+.MACRO Read_Comp_Out
+	in	@0, ACSR		; Read comparator output
+.ENDMACRO
+
+
+;*********************
+; PORT B definitions *
+;*********************
+;.equ			= 7
+;.equ			= 6
+;.equ			= 5 	(sck stk200 interface) 
+.equ	DebugPin		= 4	;(miso stk200 interface)
+;.equ			= 3	(mosi stk200 interface) 
+.equ	CnFET		= 2	;o
+.equ	BnFET		= 1	;o
+.equ	AnFET		= 0	;o
+
+.equ	INIT_PB		= 0
+.equ	DIR_PB		= (1<<AnFET)+(1<<BnFET)+(1<<CnFET)+(1<<DebugPin)
+
+.MACRO AnFET_on
+	sbi	PORTB,0
+.ENDMACRO
+.MACRO AnFET_off
+	cbi	PORTB,0
+.ENDMACRO
+.MACRO BnFET_on
+	sbi	PORTB,1
+.ENDMACRO
+.MACRO BnFET_off
+	cbi	PORTB,1
+.ENDMACRO
+.MACRO CnFET_on
+	sbi	PORTB,2
+.ENDMACRO
+.MACRO CnFET_off
+	cbi	PORTB,2
+.ENDMACRO
+.MACRO All_nFETs_Off
+	in	@0, PORTB
+	cbr	@0, (1<<AnFET)+(1<<BnFET)+(1<<CnFET)
+	out	PORTB, @0
+.ENDMACRO
+
+
+;**********************
+; MCU specific macros *
+;**********************
+.MACRO Disable_Watchdog
+	cli					; Disable interrupts
+	wdr					; Reset watchdog timer
+	in @0, MCUSR			; Clear WDRF in MCUSR
+	andi @0, (0xff & (0<<WDRF))
+	out MCUSR, @0
+	lds @0, WDTCSR			; Write logical one to WDCE and WDE
+	ori @0, (1<<WDCE) | (1<<WDE)
+	sts WDTCSR, @0
+	ldi @0, (0<<WDE)		; Turn off WDT
+	sts WDTCSR, @0
+.ENDMACRO
+.MACRO Enable_Watchdog
+	ldi @0, (1<<WDE)		; Turn on WDT
+	sts WDTCSR, @0
+.ENDMACRO
+
+.MACRO Initialize_MCU
+	ldi	@0, (1<<CLKPCE)	; Set clock prescaler change enable
+	sts	CLKPR, @0
+	ldi	@0, 0			; Change clock prescaler (to divide by 1)
+	sts	CLKPR, @0
+.ENDMACRO
+
+.MACRO Interrupt_Table_Definition
+	rjmp reset
+	rjmp ext_int0	; ext_int0 
+	nop			; ext_int1
+	nop 			; pci0_int
+	nop 			; pci1_int
+	nop 			; pci2_int
+	nop 			; wdt_int
+	nop 			; t2oca_int
+	nop 			; t2ocb_int
+	rjmp t2ovfl_int; t2ovfl_int
+	rjmp icp1_int	; icp1_int	
+	rjmp t1oca_int	; t1oca_int
+	nop			; t1ocb_int
+	rjmp t1ovfl_int; t1ovfl_int
+	nop			; t0oca_int
+	nop			; t0ocb_int
+	rjmp t0ovfl_int; t0ovfl_int
+	nop			; spi_int
+	nop			; urxc
+	nop			; udre
+	nop			; utxc
+;	nop			; adc_int
+;	nop			; eep_int
+;	nop			; aci_int
+;	nop			; wire2_int
+;	nop			; spmc_int
+.ENDMACRO
+
+.MACRO Initialize_Interrupts
+	ldi	Temp1, (1<<TOIE0)
+	out	TIFR0, Temp1	; Clear interrupts
+	sts	TIMSK0, Temp1	; Enable interrupts
+	ldi	Temp1, (1<<TOIE1)+(1<<OCIE1A)
+	out	TIFR1, Temp1	; Clear interrupts
+	sts	TIMSK1, Temp1	; Enable interrupts
+	ldi	Temp1, (1<<TOIE2)
+	out	TIFR2, Temp1	; Clear interrupts
+	sts	TIMSK2, Temp1	; Enable interrupts
+.ENDMACRO
+
+.MACRO Initialize_Adc
+  	lds  Temp1, ADCSRA	; Set ADCSRA register (1MHz clock)
+  	sbr  Temp1, (1<<ADPS1) 	
+  	sbr  Temp1, (1<<ADPS0) 	
+   	sts  ADCSRA, Temp1
+.ENDMACRO
+.MACRO Start_Adc
+	ldi	Temp1, (1<<REFS1)+(1<<REFS0)+(1<<MUX2)+(1<<MUX1)+(1<<MUX0)
+	sts	ADMUX, Temp1	; Set ADMUX register (1.1V reference, left adj result, input 7)
+  	lds  @0, ADCSRA	
+  	sbr  @0, (1<<ADEN) 	; Enable ADC	
+  	sbr  @0, (1<<ADSC) 	; Start ADC conversion	
+   	sts  ADCSRA, @0
+.ENDMACRO
+.MACRO Get_Adc_Status
+  	lds  @0, ADCSRA	
+.ENDMACRO
+.MACRO Read_Adc_Result
+  	lds  @0, ADCL	
+  	lds  @1, ADCH	
+.ENDMACRO
+.MACRO Stop_Adc
+  	lds  @0, ADCSRA	
+  	cbr  @0, (1<<ADEN) 	; Disable ADC	
+   	sts  ADCSRA, @0
+.ENDMACRO
+
+.MACRO Set_Timer0_CS0
+	out	TCCR0B, @0
+.ENDMACRO
+.MACRO Set_Timer1_CS1
+	sts	TCCR1B, @0
+.ENDMACRO
+.MACRO Set_Timer2_CS2
+	sts	TCCR2B, @0
+.ENDMACRO
+
+.MACRO Read_TCNT1L
+	lds	@0, TCNT1L
+.ENDMACRO
+.MACRO Read_TCNT1H
+	lds	@0, TCNT1H
+.ENDMACRO
+.MACRO Read_ICR1L
+	lds	@0, ICR1L
+.ENDMACRO
+.MACRO Read_ICR1H
+	lds	@0, ICR1H
+.ENDMACRO
+.MACRO Set_OCR1AL
+	sts	OCR1AL, @0
+.ENDMACRO
+.MACRO Set_OCR1AH
+	sts	OCR1AH, @0
+.ENDMACRO
+
+.MACRO Set_TCNT2
+	sts	TCNT2, @0
+.ENDMACRO
+
+.MACRO Check_Eeprom_Ready
+	sbic	EECR, EEPE
+.ENDMACRO
+.MACRO Set_Eeprom_Address
+	out  EEARL, @0
+.ENDMACRO
+.MACRO Start_Eeprom_Write
+	sbi  EECR, EEMPE
+	sbi  EECR, EEPE
+.ENDMACRO

Atmel/HC5A1SA8.inc

@@ -0,0 +1,355 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device Atmega8
+;*********************
+.include "m8def.inc"
+
+;**** **** **** **** ****
+; Fuses must be set to internal calibrated oscillator = 8Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+.equ ADC_LIMIT_L	= 45		; Power supply measurement ADC value for which main motor power is limited (low byte)
+.equ ADC_LIMIT_H	= 0		; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+;*********************
+; PORT D definitions *
+;*********************  
+.equ BpFET		= 7	;o
+.equ	Comp_Com		= 6	;i Comparator common input (AIN0)
+.equ	CpFET		= 5	;o
+.equ	ApFET		= 4	;o
+.equ	AnFET		= 3	;o
+.equ	Rcp_In		= 2	;i RC pulse input
+.equ BnFET      	= 1	;o
+.equ CnFET      	= 0	;o
+
+.equ	INIT_PD		= 0
+.equ	DIR_PD		= (1<<AnFET)+(1<<BnFET)+(1<<CnFET)+(1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+
+.MACRO Read_Rcp_Int
+	in	@0, PIND
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+.MACRO Read_Rcp_Icp_Int
+	in	@0, PINB
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+
+.MACRO Rcp_Int_Enable
+	ldi @0, (1<<INT0)	; Enable ext0int
+	out	GICR, @0
+.ENDMACRO
+.MACRO Rcp_Int_Disable
+	ldi @0, 0			; Disable ext0int
+	out	GICR, @0
+.ENDMACRO
+.MACRO Rcp_Int_First
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	out	MCUCR, @0		
+.ENDMACRO
+.MACRO Rcp_Int_Second
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	out	MCUCR, @0		
+.ENDMACRO
+.MACRO Clear_Int_Flag
+	clr 	@0
+	sbr @0, (1<<INTF0)	; Clear ext0int flag
+	out	GIFR, @0		
+.ENDMACRO
+
+.MACRO Rcp_Icp_Int_Enable
+	in	@0, TIMSK
+	sbr @0, (1<<TICIE1)	; Enable icp1int
+	out	TIMSK, @0
+.ENDMACRO
+.MACRO Rcp_Icp_Int_Disable
+	in	@0, TIMSK
+	cbr @0, (1<<TICIE1)	; Disable icp1int
+	out	TIMSK, @0
+.ENDMACRO
+
+.MACRO Rcp_Icp_Int_First
+	in	@0, TCCR1B
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	sbr @0, (1<<ICES1)			; Yes - set icp1int to trig on rising edge
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	cbr @0, (1<<ICES1)			; Yes - set icp1int to trig on falling edge
+	out	TCCR1B, @0		
+.ENDMACRO
+.MACRO Rcp_Icp_Int_Second
+	in	@0, TCCR1B
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	cbr @0, (1<<ICES1)			; Yes - set icp1int to trig on falling edge
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	sbr @0, (1<<ICES1)			; Yes - set icp1int to trig on rising edge
+	out	TCCR1B, @0		
+.ENDMACRO
+.MACRO Clear_Icp_Int_Flag
+	clr 	@0
+	sbr @0, (1<<ICF1)	; Clear icp1int flag
+	out	TIFR, @0		
+.ENDMACRO
+
+.MACRO AnFET_on
+	sbi	PORTD,3
+.ENDMACRO
+.MACRO AnFET_off
+	cbi	PORTD,3
+.ENDMACRO
+.MACRO BnFET_on
+	sbi	PORTD,1
+.ENDMACRO
+.MACRO BnFET_off
+	cbi	PORTD,1
+.ENDMACRO
+.MACRO CnFET_on
+	sbi	PORTD,0
+.ENDMACRO
+.MACRO CnFET_off
+	cbi	PORTD,0
+.ENDMACRO
+.MACRO All_nFETs_Off
+	in	@0, PORTD
+	cbr	@0, (1<<AnFET)+(1<<BnFET)+(1<<CnFET)
+	out	PORTD, @0
+.ENDMACRO
+
+.MACRO ApFET_on
+	sbi	PORTD,4
+.ENDMACRO
+.MACRO ApFET_off
+	cbi	PORTD,4
+.ENDMACRO
+.MACRO BpFET_on
+	sbi	PORTD,7
+.ENDMACRO
+.MACRO BpFET_off
+	cbi	PORTD,7
+.ENDMACRO
+.MACRO CpFET_on
+	sbi	PORTD,5
+.ENDMACRO
+.MACRO CpFET_off
+	cbi	PORTD,5
+.ENDMACRO
+.MACRO All_pFETs_Off
+	in	@0, PORTD
+	cbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+.MACRO All_pFETs_On
+	in	@0, PORTD
+	sbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+
+
+;*********************
+; PORT C definitions *
+;*********************
+;.equ    	  		= 7	; ADC7
+;.equ    	  		= 6	; ADC6
+;.equ    	  		= 5	; ADC5
+.equ	Mux_A		= 4	; Phase A input
+.equ Mux_B 		= 3	; Phase B input
+.equ	Mux_C		= 2	; Phase C input
+;.equ 	 		= 1 	; ADC1
+;.equ 			= 0 	; ADC0
+
+.equ	INIT_PC		= 0
+.equ	DIR_PC		= 0
+
+.MACRO Comp_Init
+   	in  @0, SFIOR		; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	out  SFIOR, @0
+   	cbi  ADCSRA, ADEN  	; Disable ADC
+.ENDMACRO
+.MACRO Set_Comp_Phase_A
+   	ldi  @0, Mux_A  	; Set comparator multiplexer to phase A
+   	out  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_B
+   	ldi  @0, Mux_B  	; Set comparator multiplexer to phase B
+   	out  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_C
+   	ldi  @0, Mux_C  	; Set comparator multiplexer to phase C
+   	out  ADMUX, @0
+.ENDMACRO
+.MACRO Read_Comp_Out
+	in	@0, ACSR		; Read comparator output
+.ENDMACRO
+
+
+;*********************
+; PORT B definitions *
+;*********************
+;.equ			= 7
+;.equ			= 6
+;.equ			= 5 	(sck stk200 interface) 
+.equ	DebugPin		= 4	;(miso stk200 interface)
+;.equ			= 3	(mosi stk200 interface) 
+;.equ			= 2
+;.equ			= 1
+.equ	Rcp_Icp_In	= 0
+
+.equ	INIT_PB		= 0
+.equ	DIR_PB		= (1<<DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+.MACRO Disable_Watchdog
+	cli					; Disable interrupts
+	wdr					; Reset watchdog timer
+	in @0, WDTCR			; Write logical one to WDCE and WDE
+	ori @0, (1<<WDCE)|(1<<WDE)
+	out WDTCR, @0
+	ldi @0, (0<<WDE)		; Turn off WDT
+	out WDTCR, @0
+.ENDMACRO
+.MACRO Enable_Watchdog
+	ldi @0, (1<<WDE)		; Turn on WDT
+	sts WDTCR, @0
+.ENDMACRO
+
+.MACRO Initialize_MCU
+.ENDMACRO
+
+.MACRO Interrupt_Table_Definition
+	rjmp reset
+	rjmp ext_int0	; ext_int0 
+	nop			; ext_int1
+	nop 			; t2oc_int
+	rjmp t2ovfl_int; t2ovfl_int
+	rjmp icp1_int	; icp1_int	
+	rjmp t1oca_int	; t1oca_int
+	nop			; t1ocb_int
+	rjmp t1ovfl_int; t1ovfl_int
+	rjmp t0ovfl_int; t0ovfl_int
+	nop			; spi_int
+	nop			; urxc
+	nop			; udre
+	nop			; utxc
+;	nop			; adc_int
+;	nop			; eep_int
+;	nop			; aci_int
+;	nop			; wire2_int
+;	nop			; spmc_int
+.ENDMACRO
+
+.MACRO Initialize_Interrupts
+	ldi	Temp1, (1<<TOIE0)+(1<<TOIE1)+(1<<OCIE1A)+(1<<TOIE2)
+	out	TIFR, Temp1	; Clear interrupts
+	out	TIMSK, Temp1	; Enable interrupts
+.ENDMACRO
+
+.MACRO Initialize_Adc
+  	in  	Temp1, ADCSRA	; Set ADCSRA register (1MHz clock)
+  	sbr  Temp1, (1<<ADPS1) 	
+  	sbr  Temp1, (1<<ADPS0) 	
+   	out  ADCSRA, Temp1
+.ENDMACRO
+.MACRO Start_Adc
+	ldi	Temp1, (1<<REFS1)+(1<<REFS0)+(1<<MUX2)+(1<<MUX1)+(1<<MUX0)
+	out	ADMUX, Temp1	; Set ADMUX register (2.56V reference, left adj result, input 7)
+  	in  	@0, ADCSRA	
+  	sbr  @0, (1<<ADEN) 	; Enable ADC	
+  	sbr  @0, (1<<ADSC) 	; Start ADC conversion	
+   	out  ADCSRA, @0
+.ENDMACRO
+.MACRO Get_Adc_Status
+  	in  	@0, ADCSRA	
+.ENDMACRO
+.MACRO Read_Adc_Result
+  	in  	@0, ADCL	
+  	in  	@1, ADCH	
+.ENDMACRO
+.MACRO Stop_Adc
+  	in  	@0, ADCSRA	
+  	cbr  @0, (1<<ADEN) 	; Disable ADC	
+   	out  ADCSRA, @0
+.ENDMACRO
+
+.MACRO Set_Timer0_CS0
+	out	TCCR0, @0
+.ENDMACRO
+.MACRO Set_Timer1_CS1
+	out	TCCR1B, @0
+.ENDMACRO
+.MACRO Set_Timer2_CS2
+	out	TCCR2, @0
+.ENDMACRO
+
+.MACRO Read_TCNT1L
+	in	@0, TCNT1L
+.ENDMACRO
+.MACRO Read_TCNT1H
+	in	@0, TCNT1H
+.ENDMACRO
+.MACRO Read_ICR1L
+	in	@0, ICR1L
+.ENDMACRO
+.MACRO Read_ICR1H
+	in	@0, ICR1H
+.ENDMACRO
+.MACRO Set_OCR1AL
+	out	OCR1AL, @0
+.ENDMACRO
+.MACRO Set_OCR1AH
+	out	OCR1AH, @0
+.ENDMACRO
+
+.MACRO Set_TCNT2
+	out	TCNT2, @0
+.ENDMACRO
+
+.MACRO Check_Eeprom_Ready
+	sbic	EECR, EEWE
+.ENDMACRO
+.MACRO Set_Eeprom_Address
+	out  EEARL, @0
+	out  EEARH, @1
+.ENDMACRO
+.MACRO Start_Eeprom_Write
+	sbi  EECR, EEMWE
+	sbi  EECR, EEWE
+.ENDMACRO

Atmel/README

@@ -0,0 +1,26 @@
+This tree contains the BLHeli assembly code for sensorless brushless motor electronic speed control (ESC) boards.
+It is designed specifically for use with Eflite mCP X, but may also be used on other copters/planes.
+
+This tree contains AVR assembly code for Atmel MCU based ESCs. 
+
+Features and Changes
+--------------------
+- Can be configured for main motor or tail motor operation
+- Main motor operation has governor functionality
+- Many parmeters can be programmed from the TX
+- Supports 1kHz, 2kHz, 4kHz or 8kHz positive or negative pwm as input signal
+
+Supported Hardware
+------------------
+- HC 5A
+- Walkera WK-WST-10A-LT
+- Feigao 6A
+
+Installation and use
+--------------------
+The software is written, compiled and debugged in the AVR Studio 4 IDE.
+
+For more information, check out this thread:
+
+http://www.helifreak.com/showthread.php?t=357151
+

Atmel/WalkeraWST10LT.inc

@@ -0,0 +1,387 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device Atmega88P(A)
+;*********************
+.include "m88Pdef.inc"
+
+;**** **** **** **** ****
+; Fuses must be set to external oscillator 8.0- MHz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+.equ ADC_LIMIT_L	= 180	; Power supply measurement ADC value for which main motor power is limited (low byte)
+.equ ADC_LIMIT_H	= 1		; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+;*********************
+; PORT D definitions *
+;*********************  
+.equ	Mux_B		= 7	;i Phase B input
+.equ	Comp_Com		= 6	;i Comparator common input (AIN0)
+.equ	BnFET		= 5	;o
+.equ	BpFET		= 4	;o
+.equ	CpFET		= 3	;o
+.equ	Rcp_In		= 2	;i RC pulse input
+.equ	ApFET		= 1	;o
+;.equ       		= 0	;i
+
+.equ	INIT_PD		= 0
+.equ	DIR_PD		= (1<<ApFET)+(1<<BpFET)+(1<<CpFET)+(1<<BnFET)
+
+
+.MACRO Read_Rcp_Int
+	in	@0, PIND
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+.MACRO Read_Rcp_Icp_Int
+	in	@0, PINB
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	com	@0					; Yes - invert
+.ENDMACRO
+
+.MACRO Rcp_Int_Enable
+	ldi @0, (1<<INT0)	; Enable ext0int
+	out	EIMSK, @0
+.ENDMACRO
+.MACRO Rcp_Int_Disable
+	ldi @0, 0			; Disable ext0int
+	out	EIMSK, @0
+.ENDMACRO
+.MACRO Rcp_Int_First
+	sbrs	Flags2, PGM_RCP_PWM_POL		; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	sbrc Flags2, PGM_RCP_PWM_POL		; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	sts	EICRA, @0		
+.ENDMACRO
+.MACRO Rcp_Int_Second
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive?
+	ldi @0, (1<<ISC01)			; Yes - set next int0 to falling
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative?
+	ldi @0, (1<<ISC01)+(1<<ISC00)	; Yes - set next int0 to rising
+	sts	EICRA, @0		
+.ENDMACRO
+.MACRO Clear_Int_Flag
+	clr 	@0
+	sbr @0, (1<<INTF0)	; Clear ext0int flag
+	out	EIFR, @0		
+.ENDMACRO
+
+.MACRO Rcp_Icp_Int_Enable
+	lds	@0, TIMSK1
+	sbr @0, (1<<ICIE1)	; Enable icp1int
+	sts	TIMSK1, @0		
+.ENDMACRO
+.MACRO Rcp_Icp_Int_Disable
+	lds	@0, TIMSK1
+	cbr @0, (1<<ICIE1)	; Disable icp1int
+	sts	TIMSK1, @0		
+.ENDMACRO
+
+.MACRO Rcp_Icp_Int_First
+	lds	@0, TCCR1B
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive
+	sbr @0, (1<<ICES1)			; Yes - set icp1int to trig on rising edge
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative
+	cbr @0, (1<<ICES1)			; Yes - set icp1int to trig on falling edge
+	sts	TCCR1B, @0		
+.ENDMACRO
+.MACRO Rcp_Icp_Int_Second
+	lds	@0, TCCR1B
+	sbrs	Flags2, PGM_RCP_PWM_POL	; Is pwm polarity positive
+	cbr @0, (1<<ICES1)			; Yes - set icp1int to trig on falling edge
+	sbrc Flags2, PGM_RCP_PWM_POL	; Is pwm polarity negative
+	sbr @0, (1<<ICES1)			; Yes - set icp1int to trig on rising edge
+	sts	TCCR1B, @0		
+.ENDMACRO
+.MACRO Clear_Icp_Int_Flag
+	clr 	@0
+	sbr @0, (1<<ICF1)	; Clear icp1int flag
+	out	TIFR1, @0		
+.ENDMACRO
+
+.MACRO ApFET_on
+	sbi	PORTD,1
+.ENDMACRO
+.MACRO ApFET_off
+	cbi	PORTD,1
+.ENDMACRO
+.MACRO CpFET_on
+	sbi	PORTD,3
+.ENDMACRO
+.MACRO CpFET_off
+	cbi	PORTD,3
+.ENDMACRO
+.MACRO BpFET_on
+	sbi	PORTD,4
+.ENDMACRO
+.MACRO BpFET_off
+	cbi	PORTD,4
+.ENDMACRO
+.MACRO All_pFETs_Off
+	in	@0, PORTD
+	cbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+.MACRO All_pFETs_On
+	in	@0, PORTD
+	sbr	@0, (1<<ApFET)+(1<<BpFET)+(1<<CpFET)
+	out	PORTD, @0
+.ENDMACRO
+
+
+;*********************
+; PORT C definitions *
+;*********************
+;.equ    	  		= 7	; ADC7
+;.equ 			= 6	; ADC6
+;.equ 			= 5	; ADC5
+;.equ    	  		= 4	; ADC4
+.equ Mux_C 		= 3	; Phase C input
+.equ	Mux_A		= 2	; Phase A input
+;.equ 	 		= 1 	; ADC1
+;.equ 			= 0 	; ADC0
+
+.equ	INIT_PC		= 0
+.equ	DIR_PC		= 0
+
+.MACRO Comp_Init
+  	lds  @0, ADCSRA	; Disable ADC
+  	cbr  @0, (1<<ADEN) 	
+   	sts  ADCSRA, @0
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_A
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+  	ldi  @0, Mux_A  	; Set comparator multiplexer to phase A
+   	sts  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_C
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Enable
+   	sbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+   	ldi  @0, Mux_C  	; Set comparator multiplexer to phase C
+   	sts  ADMUX, @0
+.ENDMACRO
+.MACRO Set_Comp_Phase_B
+  	lds  @0, ADCSRB	; Set Analog Comparator Multiplexer Disable
+   	cbr  @0, (1<<ACME) 	
+   	sts  ADCSRB, @0
+.ENDMACRO
+.MACRO Read_Comp_Out
+	in	@0, ACSR		; Read comparator output
+.ENDMACRO
+
+
+;*********************
+; PORT B definitions *
+;*********************
+;.equ			= 7
+;.equ			= 6
+;.equ			= 5 	(sck stk200 interface) 
+.equ	DebugPin		= 4	;(miso stk200 interface)
+;.equ			= 3	(mosi stk200 interface) 
+.equ	AnFET		= 2
+.equ	CnFET		= 1
+.equ	Rcp_Icp_In	= 0
+
+.equ	INIT_PB		= 0
+.equ	DIR_PB		= (1<<DebugPin)+(1<<AnFET)+(1<<CnFET)
+
+.MACRO AnFET_on
+	sbi	PORTB,2
+.ENDMACRO
+.MACRO AnFET_off
+	cbi	PORTB,2
+.ENDMACRO
+.MACRO CnFET_on
+	sbi	PORTB,1
+.ENDMACRO
+.MACRO CnFET_off
+	cbi	PORTB,1
+.ENDMACRO
+.MACRO BnFET_on
+	sbi	PORTD,5
+.ENDMACRO
+.MACRO BnFET_off
+	cbi	PORTD,5
+.ENDMACRO
+.MACRO All_nFETs_Off
+	in	@0, PORTB
+	cbr	@0, (1<<AnFET)+(1<<CnFET)
+	out	PORTB, @0
+	in	@0, PORTD
+	cbr	@0, (1<<BnFET)
+	out	PORTD, @0
+.ENDMACRO
+
+;**********************
+; MCU specific macros *
+;**********************
+.MACRO Disable_Watchdog
+	cli					; Disable interrupts
+	wdr					; Reset watchdog timer
+	in @0, MCUSR			; Clear WDRF in MCUSR
+	andi @0, (0xff & (0<<WDRF))
+	out MCUSR, @0
+	lds @0, WDTCSR			; Write logical one to WDCE and WDE
+	ori @0, (1<<WDCE) | (1<<WDE)
+	sts WDTCSR, @0
+	ldi @0, (0<<WDE)		; Turn off WDT
+	sts WDTCSR, @0
+.ENDMACRO
+.MACRO Enable_Watchdog
+	ldi @0, (1<<WDE)		; Turn on WDT
+	sts WDTCSR, @0
+.ENDMACRO
+
+.MACRO Initialize_MCU
+	ldi	@0, (1<<CLKPCE)	; Set clock prescaler change enable
+	sts	CLKPR, @0
+	ldi	@0, (1<<CLKPS0)	; Change clock prescaler (to divide by 2)
+	sts	CLKPR, @0
+.ENDMACRO
+
+.MACRO Interrupt_Table_Definition
+	rjmp reset
+	rjmp ext_int0	; ext_int0 
+	nop			; ext_int1
+	nop 			; pci0_int
+	nop 			; pci1_int
+	nop 			; pci2_int
+	nop 			; wdt_int
+	nop 			; t2oca_int
+	nop 			; t2ocb_int
+	rjmp t2ovfl_int; t2ovfl_int
+	rjmp icp1_int	; icp1_int	
+	rjmp t1oca_int	; t1oca_int
+	nop			; t1ocb_int
+	rjmp t1ovfl_int; t1ovfl_int
+	nop			; t0oca_int
+	nop			; t0ocb_int
+	rjmp t0ovfl_int; t0ovfl_int
+	nop			; spi_int
+	nop			; urxc
+	nop			; udre
+	nop			; utxc
+;	nop			; adc_int
+;	nop			; eep_int
+;	nop			; aci_int
+;	nop			; wire2_int
+;	nop			; spmc_int
+.ENDMACRO
+
+.MACRO Initialize_Interrupts
+	ldi	Temp1, (1<<TOIE0)
+	out	TIFR0, Temp1	; Clear interrupts
+	sts	TIMSK0, Temp1	; Enable interrupts
+	ldi	Temp1, (1<<TOIE1)+(1<<OCIE1A)
+	out	TIFR1, Temp1	; Clear interrupts
+	sts	TIMSK1, Temp1	; Enable interrupts
+	ldi	Temp1, (1<<TOIE2)
+	out	TIFR2, Temp1	; Clear interrupts
+	sts	TIMSK2, Temp1	; Enable interrupts
+.ENDMACRO
+
+.MACRO Initialize_Adc
+  	lds  Temp1, ADCSRA	; Set ADCSRA register (1MHz clock)
+  	sbr  Temp1, (1<<ADPS1) 	
+  	sbr  Temp1, (1<<ADPS0) 	
+   	sts  ADCSRA, Temp1
+.ENDMACRO
+.MACRO Start_Adc
+	ldi	Temp1, (1<<REFS1)+(1<<REFS0)+(1<<MUX2)+(1<<MUX1)+(1<<MUX0)
+	sts	ADMUX, Temp1	; Set ADMUX register (1.1V reference, left adj result, input 7)
+  	lds  @0, ADCSRA	
+  	sbr  @0, (1<<ADEN) 	; Enable ADC	
+  	sbr  @0, (1<<ADSC) 	; Start ADC conversion	
+   	sts  ADCSRA, @0
+.ENDMACRO
+.MACRO Get_Adc_Status
+  	lds  @0, ADCSRA	
+.ENDMACRO
+.MACRO Read_Adc_Result
+  	lds  @0, ADCL	
+  	lds  @1, ADCH	
+.ENDMACRO
+.MACRO Stop_Adc
+  	lds  @0, ADCSRA	
+  	cbr  @0, (1<<ADEN) 	; Disable ADC	
+   	sts  ADCSRA, @0
+.ENDMACRO
+
+.MACRO Set_Timer0_CS0
+	out	TCCR0B, @0
+.ENDMACRO
+.MACRO Set_Timer1_CS1
+	sts	TCCR1B, @0
+.ENDMACRO
+.MACRO Set_Timer2_CS2
+	sts	TCCR2B, @0
+.ENDMACRO
+
+.MACRO Read_TCNT1L
+	lds	@0, TCNT1L
+.ENDMACRO
+.MACRO Read_TCNT1H
+	lds	@0, TCNT1H
+.ENDMACRO
+.MACRO Read_ICR1L
+	lds	@0, ICR1L
+.ENDMACRO
+.MACRO Read_ICR1H
+	lds	@0, ICR1H
+.ENDMACRO
+.MACRO Set_OCR1AL
+	sts	OCR1AL, @0
+.ENDMACRO
+.MACRO Set_OCR1AH
+	sts	OCR1AH, @0
+.ENDMACRO
+
+.MACRO Set_TCNT2
+	sts	TCNT2, @0
+.ENDMACRO
+
+.MACRO Check_Eeprom_Ready
+	sbic	EECR, EEPE
+.ENDMACRO
+.MACRO Set_Eeprom_Address
+	out  EEARL, @0
+	out  EEARH, @1
+.ENDMACRO
+.MACRO Start_Eeprom_Write
+	sbi  EECR, EEMPE
+	sbi  EECR, EEPE
+.ENDMACRO

Atmel/m48def.inc

@@ -0,0 +1,958 @@
+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
+;***** Created: 2009-11-03 14:40 ******* Source: ATmega48.xml ************
+;*************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number            : AVR000
+;* File Name         : "m48def.inc"
+;* Title             : Register/Bit Definitions for the ATmega48
+;* Date              : 2009-11-03
+;* Version           : 2.35
+;* Support E-mail    : avr@atmel.com
+;* Target MCU        : ATmega48
+;* 
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register 
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and 
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;* 
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in    r16,PORTB             ;read PORTB latch
+;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
+;* out   PORTB,r16             ;output to PORTB
+;* 
+;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
+;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
+;* rjmp  TOV0_is_set           ;jump if set
+;* ...                         ;otherwise do something else
+;*************************************************************************
+
+#ifndef _M48DEF_INC_
+#define _M48DEF_INC_
+
+
+#pragma partinc 0
+
+; ***** SPECIFY DEVICE ***************************************************
+.device ATmega48
+#pragma AVRPART ADMIN PART_NAME ATmega48
+.equ	SIGNATURE_000	= 0x1e
+.equ	SIGNATURE_001	= 0x92
+.equ	SIGNATURE_002	= 0x05
+
+#pragma AVRPART CORE CORE_VERSION V2E
+
+
+; ***** I/O REGISTER DEFINITIONS *****************************************
+; NOTE:
+; Definitions marked "MEMORY MAPPED"are extended I/O ports
+; and cannot be used with IN/OUT instructions
+.equ	UDR0	= 0xc6	; MEMORY MAPPED
+.equ	UBRR0L	= 0xc4	; MEMORY MAPPED
+.equ	UBRR0H	= 0xc5	; MEMORY MAPPED
+.equ	UCSR0C	= 0xc2	; MEMORY MAPPED
+.equ	UCSR0B	= 0xc1	; MEMORY MAPPED
+.equ	UCSR0A	= 0xc0	; MEMORY MAPPED
+.equ	TWAMR	= 0xbd	; MEMORY MAPPED
+.equ	TWCR	= 0xbc	; MEMORY MAPPED
+.equ	TWDR	= 0xbb	; MEMORY MAPPED
+.equ	TWAR	= 0xba	; MEMORY MAPPED
+.equ	TWSR	= 0xb9	; MEMORY MAPPED
+.equ	TWBR	= 0xb8	; MEMORY MAPPED
+.equ	ASSR	= 0xb6	; MEMORY MAPPED
+.equ	OCR2B	= 0xb4	; MEMORY MAPPED
+.equ	OCR2A	= 0xb3	; MEMORY MAPPED
+.equ	TCNT2	= 0xb2	; MEMORY MAPPED
+.equ	TCCR2B	= 0xb1	; MEMORY MAPPED
+.equ	TCCR2A	= 0xb0	; MEMORY MAPPED
+.equ	OCR1BL	= 0x8a	; MEMORY MAPPED
+.equ	OCR1BH	= 0x8b	; MEMORY MAPPED
+.equ	OCR1AL	= 0x88	; MEMORY MAPPED
+.equ	OCR1AH	= 0x89	; MEMORY MAPPED
+.equ	ICR1L	= 0x86	; MEMORY MAPPED
+.equ	ICR1H	= 0x87	; MEMORY MAPPED
+.equ	TCNT1L	= 0x84	; MEMORY MAPPED
+.equ	TCNT1H	= 0x85	; MEMORY MAPPED
+.equ	TCCR1C	= 0x82	; MEMORY MAPPED
+.equ	TCCR1B	= 0x81	; MEMORY MAPPED
+.equ	TCCR1A	= 0x80	; MEMORY MAPPED
+.equ	DIDR1	= 0x7f	; MEMORY MAPPED
+.equ	DIDR0	= 0x7e	; MEMORY MAPPED
+.equ	ADMUX	= 0x7c	; MEMORY MAPPED
+.equ	ADCSRB	= 0x7b	; MEMORY MAPPED
+.equ	ADCSRA	= 0x7a	; MEMORY MAPPED
+.equ	ADCH	= 0x79	; MEMORY MAPPED
+.equ	ADCL	= 0x78	; MEMORY MAPPED
+.equ	TIMSK2	= 0x70	; MEMORY MAPPED
+.equ	TIMSK1	= 0x6f	; MEMORY MAPPED
+.equ	TIMSK0	= 0x6e	; MEMORY MAPPED
+.equ	PCMSK1	= 0x6c	; MEMORY MAPPED
+.equ	PCMSK2	= 0x6d	; MEMORY MAPPED
+.equ	PCMSK0	= 0x6b	; MEMORY MAPPED
+.equ	EICRA	= 0x69	; MEMORY MAPPED
+.equ	PCICR	= 0x68	; MEMORY MAPPED
+.equ	OSCCAL	= 0x66	; MEMORY MAPPED
+.equ	PRR	= 0x64	; MEMORY MAPPED
+.equ	CLKPR	= 0x61	; MEMORY MAPPED
+.equ	WDTCSR	= 0x60	; MEMORY MAPPED
+.equ	SREG	= 0x3f
+.equ	SPL	= 0x3d
+.equ	SPH	= 0x3e
+.equ	SPMCSR	= 0x37
+.equ	MCUCR	= 0x35
+.equ	MCUSR	= 0x34
+.equ	SMCR	= 0x33
+.equ	ACSR	= 0x30
+.equ	SPDR	= 0x2e
+.equ	SPSR	= 0x2d
+.equ	SPCR	= 0x2c
+.equ	GPIOR2	= 0x2b
+.equ	GPIOR1	= 0x2a
+.equ	OCR0B	= 0x28
+.equ	OCR0A	= 0x27
+.equ	TCNT0	= 0x26
+.equ	TCCR0B	= 0x25
+.equ	TCCR0A	= 0x24
+.equ	GTCCR	= 0x23
+.equ	EEARL	= 0x21
+.equ	EEDR	= 0x20
+.equ	EECR	= 0x1f
+.equ	GPIOR0	= 0x1e
+.equ	EIMSK	= 0x1d
+.equ	EIFR	= 0x1c
+.equ	PCIFR	= 0x1b
+.equ	TIFR2	= 0x17
+.equ	TIFR1	= 0x16
+.equ	TIFR0	= 0x15
+.equ	PORTD	= 0x0b
+.equ	DDRD	= 0x0a
+.equ	PIND	= 0x09
+.equ	PORTC	= 0x08
+.equ	DDRC	= 0x07
+.equ	PINC	= 0x06
+.equ	PORTB	= 0x05
+.equ	DDRB	= 0x04
+.equ	PINB	= 0x03
+
+
+; ***** BIT DEFINITIONS **************************************************
+
+; ***** USART0 ***********************
+; UDR0 - USART I/O Data Register
+.equ	UDR0_0	= 0	; USART I/O Data Register bit 0
+.equ	UDR0_1	= 1	; USART I/O Data Register bit 1
+.equ	UDR0_2	= 2	; USART I/O Data Register bit 2
+.equ	UDR0_3	= 3	; USART I/O Data Register bit 3
+.equ	UDR0_4	= 4	; USART I/O Data Register bit 4
+.equ	UDR0_5	= 5	; USART I/O Data Register bit 5
+.equ	UDR0_6	= 6	; USART I/O Data Register bit 6
+.equ	UDR0_7	= 7	; USART I/O Data Register bit 7
+
+; UCSR0A - USART Control and Status Register A
+.equ	MPCM0	= 0	; Multi-processor Communication Mode
+.equ	U2X0	= 1	; Double the USART transmission speed
+.equ	UPE0	= 2	; Parity Error
+.equ	DOR0	= 3	; Data overRun
+.equ	FE0	= 4	; Framing Error
+.equ	UDRE0	= 5	; USART Data Register Empty
+.equ	TXC0	= 6	; USART Transmitt Complete
+.equ	RXC0	= 7	; USART Receive Complete
+
+; UCSR0B - USART Control and Status Register B
+.equ	TXB80	= 0	; Transmit Data Bit 8
+.equ	RXB80	= 1	; Receive Data Bit 8
+.equ	UCSZ02	= 2	; Character Size
+.equ	TXEN0	= 3	; Transmitter Enable
+.equ	RXEN0	= 4	; Receiver Enable
+.equ	UDRIE0	= 5	; USART Data register Empty Interrupt Enable
+.equ	TXCIE0	= 6	; TX Complete Interrupt Enable
+.equ	RXCIE0	= 7	; RX Complete Interrupt Enable
+
+; UCSR0C - USART Control and Status Register C
+.equ	UCPOL0	= 0	; Clock Polarity
+.equ	UCSZ00	= 1	; Character Size
+.equ	UCPHA0	= UCSZ00	; For compatibility
+.equ	UCSZ01	= 2	; Character Size
+.equ	UDORD0	= UCSZ01	; For compatibility
+.equ	USBS0	= 3	; Stop Bit Select
+.equ	UPM00	= 4	; Parity Mode Bit 0
+.equ	UPM01	= 5	; Parity Mode Bit 1
+.equ	UMSEL00	= 6	; USART Mode Select
+.equ	UMSEL0	= UMSEL00	; For compatibility
+.equ	UMSEL01	= 7	; USART Mode Select
+.equ	UMSEL1	= UMSEL01	; For compatibility
+
+; UBRR0H - USART Baud Rate Register High Byte
+.equ	UBRR8	= 0	; USART Baud Rate Register bit 8
+.equ	UBRR9	= 1	; USART Baud Rate Register bit 9
+.equ	UBRR10	= 2	; USART Baud Rate Register bit 10
+.equ	UBRR11	= 3	; USART Baud Rate Register bit 11
+
+; UBRR0L - USART Baud Rate Register Low Byte
+.equ	_UBRR0	= 0	; USART Baud Rate Register bit 0
+.equ	_UBRR1	= 1	; USART Baud Rate Register bit 1
+.equ	UBRR2	= 2	; USART Baud Rate Register bit 2
+.equ	UBRR3	= 3	; USART Baud Rate Register bit 3
+.equ	UBRR4	= 4	; USART Baud Rate Register bit 4
+.equ	UBRR5	= 5	; USART Baud Rate Register bit 5
+.equ	UBRR6	= 6	; USART Baud Rate Register bit 6
+.equ	UBRR7	= 7	; USART Baud Rate Register bit 7
+
+
+; ***** TWI **************************
+; TWAMR - TWI (Slave) Address Mask Register
+.equ	TWAM0	= 1	; 
+.equ	TWAMR0	= TWAM0	; For compatibility
+.equ	TWAM1	= 2	; 
+.equ	TWAMR1	= TWAM1	; For compatibility
+.equ	TWAM2	= 3	; 
+.equ	TWAMR2	= TWAM2	; For compatibility
+.equ	TWAM3	= 4	; 
+.equ	TWAMR3	= TWAM3	; For compatibility
+.equ	TWAM4	= 5	; 
+.equ	TWAMR4	= TWAM4	; For compatibility
+.equ	TWAM5	= 6	; 
+.equ	TWAMR5	= TWAM5	; For compatibility
+.equ	TWAM6	= 7	; 
+.equ	TWAMR6	= TWAM6	; For compatibility
+
+; TWBR - TWI Bit Rate register
+.equ	TWBR0	= 0	; 
+.equ	TWBR1	= 1	; 
+.equ	TWBR2	= 2	; 
+.equ	TWBR3	= 3	; 
+.equ	TWBR4	= 4	; 
+.equ	TWBR5	= 5	; 
+.equ	TWBR6	= 6	; 
+.equ	TWBR7	= 7	; 
+
+; TWCR - TWI Control Register
+.equ	TWIE	= 0	; TWI Interrupt Enable
+.equ	TWEN	= 2	; TWI Enable Bit
+.equ	TWWC	= 3	; TWI Write Collition Flag
+.equ	TWSTO	= 4	; TWI Stop Condition Bit
+.equ	TWSTA	= 5	; TWI Start Condition Bit
+.equ	TWEA	= 6	; TWI Enable Acknowledge Bit
+.equ	TWINT	= 7	; TWI Interrupt Flag
+
+; TWSR - TWI Status Register
+.equ	TWPS0	= 0	; TWI Prescaler
+.equ	TWPS1	= 1	; TWI Prescaler
+.equ	TWS3	= 3	; TWI Status
+.equ	TWS4	= 4	; TWI Status
+.equ	TWS5	= 5	; TWI Status
+.equ	TWS6	= 6	; TWI Status
+.equ	TWS7	= 7	; TWI Status
+
+; TWDR - TWI Data register
+.equ	TWD0	= 0	; TWI Data Register Bit 0
+.equ	TWD1	= 1	; TWI Data Register Bit 1
+.equ	TWD2	= 2	; TWI Data Register Bit 2
+.equ	TWD3	= 3	; TWI Data Register Bit 3
+.equ	TWD4	= 4	; TWI Data Register Bit 4
+.equ	TWD5	= 5	; TWI Data Register Bit 5
+.equ	TWD6	= 6	; TWI Data Register Bit 6
+.equ	TWD7	= 7	; TWI Data Register Bit 7
+
+; TWAR - TWI (Slave) Address register
+.equ	TWGCE	= 0	; TWI General Call Recognition Enable Bit
+.equ	TWA0	= 1	; TWI (Slave) Address register Bit 0
+.equ	TWA1	= 2	; TWI (Slave) Address register Bit 1
+.equ	TWA2	= 3	; TWI (Slave) Address register Bit 2
+.equ	TWA3	= 4	; TWI (Slave) Address register Bit 3
+.equ	TWA4	= 5	; TWI (Slave) Address register Bit 4
+.equ	TWA5	= 6	; TWI (Slave) Address register Bit 5
+.equ	TWA6	= 7	; TWI (Slave) Address register Bit 6
+
+
+; ***** TIMER_COUNTER_1 **************
+; TIMSK1 - Timer/Counter Interrupt Mask Register
+.equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
+.equ	OCIE1A	= 1	; Timer/Counter1 Output CompareA Match Interrupt Enable
+.equ	OCIE1B	= 2	; Timer/Counter1 Output CompareB Match Interrupt Enable
+.equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
+
+; TIFR1 - Timer/Counter Interrupt Flag register
+.equ	TOV1	= 0	; Timer/Counter1 Overflow Flag
+.equ	OCF1A	= 1	; Output Compare Flag 1A
+.equ	OCF1B	= 2	; Output Compare Flag 1B
+.equ	ICF1	= 5	; Input Capture Flag 1
+
+; TCCR1A - Timer/Counter1 Control Register A
+.equ	WGM10	= 0	; Waveform Generation Mode
+.equ	WGM11	= 1	; Waveform Generation Mode
+.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
+.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
+.equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
+.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
+
+; TCCR1B - Timer/Counter1 Control Register B
+.equ	CS10	= 0	; Prescaler source of Timer/Counter 1
+.equ	CS11	= 1	; Prescaler source of Timer/Counter 1
+.equ	CS12	= 2	; Prescaler source of Timer/Counter 1
+.equ	WGM12	= 3	; Waveform Generation Mode
+.equ	WGM13	= 4	; Waveform Generation Mode
+.equ	ICES1	= 6	; Input Capture 1 Edge Select
+.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
+
+; TCCR1C - Timer/Counter1 Control Register C
+.equ	FOC1B	= 6	; 
+.equ	FOC1A	= 7	; 
+
+; GTCCR - General Timer/Counter Control Register
+.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
+.equ	TSM	= 7	; Timer/Counter Synchronization Mode
+
+
+; ***** TIMER_COUNTER_2 **************
+; TIMSK2 - Timer/Counter Interrupt Mask register
+.equ	TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable
+.equ	TOIE2A	= TOIE2	; For compatibility
+.equ	OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable
+.equ	OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable
+
+; TIFR2 - Timer/Counter Interrupt Flag Register
+.equ	TOV2	= 0	; Timer/Counter2 Overflow Flag
+.equ	OCF2A	= 1	; Output Compare Flag 2A
+.equ	OCF2B	= 2	; Output Compare Flag 2B
+
+; TCCR2A - Timer/Counter2 Control Register A
+.equ	WGM20	= 0	; Waveform Genration Mode
+.equ	WGM21	= 1	; Waveform Genration Mode
+.equ	COM2B0	= 4	; Compare Output Mode bit 0
+.equ	COM2B1	= 5	; Compare Output Mode bit 1
+.equ	COM2A0	= 6	; Compare Output Mode bit 1
+.equ	COM2A1	= 7	; Compare Output Mode bit 1
+
+; TCCR2B - Timer/Counter2 Control Register B
+.equ	CS20	= 0	; Clock Select bit 0
+.equ	CS21	= 1	; Clock Select bit 1
+.equ	CS22	= 2	; Clock Select bit 2
+.equ	WGM22	= 3	; Waveform Generation Mode
+.equ	FOC2B	= 6	; Force Output Compare B
+.equ	FOC2A	= 7	; Force Output Compare A
+
+; TCNT2 - Timer/Counter2
+.equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0
+.equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1
+.equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2
+.equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3
+.equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4
+.equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5
+.equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6
+.equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7
+
+; OCR2A - Timer/Counter2 Output Compare Register A
+.equ	OCR2A_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
+.equ	OCR2A_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
+.equ	OCR2A_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
+.equ	OCR2A_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
+.equ	OCR2A_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
+.equ	OCR2A_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
+.equ	OCR2A_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
+.equ	OCR2A_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
+
+; OCR2B - Timer/Counter2 Output Compare Register B
+.equ	OCR2B_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
+.equ	OCR2B_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
+.equ	OCR2B_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
+.equ	OCR2B_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
+.equ	OCR2B_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
+.equ	OCR2B_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
+.equ	OCR2B_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
+.equ	OCR2B_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
+
+; ASSR - Asynchronous Status Register
+.equ	TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy
+.equ	TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy
+.equ	OCR2BUB	= 2	; Output Compare Register 2 Update Busy
+.equ	OCR2AUB	= 3	; Output Compare Register2 Update Busy
+.equ	TCN2UB	= 4	; Timer/Counter2 Update Busy
+.equ	AS2	= 5	; Asynchronous Timer/Counter2
+.equ	EXCLK	= 6	; Enable External Clock Input
+
+; GTCCR - General Timer Counter Control register
+.equ	PSRASY	= 1	; Prescaler Reset Timer/Counter2
+.equ	PSR2	= PSRASY	; For compatibility
+;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
+
+
+; ***** AD_CONVERTER *****************
+; ADMUX - The ADC multiplexer Selection Register
+.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
+.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
+.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
+.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
+.equ	ADLAR	= 5	; Left Adjust Result
+.equ	REFS0	= 6	; Reference Selection Bit 0
+.equ	REFS1	= 7	; Reference Selection Bit 1
+
+; ADCSRA - The ADC Control and Status register A
+.equ	ADPS0	= 0	; ADC  Prescaler Select Bits
+.equ	ADPS1	= 1	; ADC  Prescaler Select Bits
+.equ	ADPS2	= 2	; ADC  Prescaler Select Bits
+.equ	ADIE	= 3	; ADC Interrupt Enable
+.equ	ADIF	= 4	; ADC Interrupt Flag
+.equ	ADATE	= 5	; ADC  Auto Trigger Enable
+.equ	ADSC	= 6	; ADC Start Conversion
+.equ	ADEN	= 7	; ADC Enable
+
+; ADCSRB - The ADC Control and Status register B
+.equ	ADTS0	= 0	; ADC Auto Trigger Source bit 0
+.equ	ADTS1	= 1	; ADC Auto Trigger Source bit 1
+.equ	ADTS2	= 2	; ADC Auto Trigger Source bit 2
+.equ	ACME	= 6	; 
+
+; ADCH - ADC Data Register High Byte
+.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
+.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
+.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
+.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
+.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
+.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
+.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
+.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
+
+; ADCL - ADC Data Register Low Byte
+.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
+.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
+.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
+.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
+.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
+.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
+.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
+.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
+
+; DIDR0 - Digital Input Disable Register
+.equ	ADC0D	= 0	; 
+.equ	ADC1D	= 1	; 
+.equ	ADC2D	= 2	; 
+.equ	ADC3D	= 3	; 
+.equ	ADC4D	= 4	; 
+.equ	ADC5D	= 5	; 
+
+
+; ***** ANALOG_COMPARATOR ************
+; ACSR - Analog Comparator Control And Status Register
+.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
+.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
+.equ	ACIC	= 2	; Analog Comparator Input Capture Enable
+.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
+.equ	ACI	= 4	; Analog Comparator Interrupt Flag
+.equ	ACO	= 5	; Analog Compare Output
+.equ	ACBG	= 6	; Analog Comparator Bandgap Select
+.equ	ACD	= 7	; Analog Comparator Disable
+
+; DIDR1 - Digital Input Disable Register 1
+.equ	AIN0D	= 0	; AIN0 Digital Input Disable
+.equ	AIN1D	= 1	; AIN1 Digital Input Disable
+
+
+; ***** PORTB ************************
+; PORTB - Port B Data Register
+.equ	PORTB0	= 0	; Port B Data Register bit 0
+.equ	PB0	= 0	; For compatibility
+.equ	PORTB1	= 1	; Port B Data Register bit 1
+.equ	PB1	= 1	; For compatibility
+.equ	PORTB2	= 2	; Port B Data Register bit 2
+.equ	PB2	= 2	; For compatibility
+.equ	PORTB3	= 3	; Port B Data Register bit 3
+.equ	PB3	= 3	; For compatibility
+.equ	PORTB4	= 4	; Port B Data Register bit 4
+.equ	PB4	= 4	; For compatibility
+.equ	PORTB5	= 5	; Port B Data Register bit 5
+.equ	PB5	= 5	; For compatibility
+.equ	PORTB6	= 6	; Port B Data Register bit 6
+.equ	PB6	= 6	; For compatibility
+.equ	PORTB7	= 7	; Port B Data Register bit 7
+.equ	PB7	= 7	; For compatibility
+
+; DDRB - Port B Data Direction Register
+.equ	DDB0	= 0	; Port B Data Direction Register bit 0
+.equ	DDB1	= 1	; Port B Data Direction Register bit 1
+.equ	DDB2	= 2	; Port B Data Direction Register bit 2
+.equ	DDB3	= 3	; Port B Data Direction Register bit 3
+.equ	DDB4	= 4	; Port B Data Direction Register bit 4
+.equ	DDB5	= 5	; Port B Data Direction Register bit 5
+.equ	DDB6	= 6	; Port B Data Direction Register bit 6
+.equ	DDB7	= 7	; Port B Data Direction Register bit 7
+
+; PINB - Port B Input Pins
+.equ	PINB0	= 0	; Port B Input Pins bit 0
+.equ	PINB1	= 1	; Port B Input Pins bit 1
+.equ	PINB2	= 2	; Port B Input Pins bit 2
+.equ	PINB3	= 3	; Port B Input Pins bit 3
+.equ	PINB4	= 4	; Port B Input Pins bit 4
+.equ	PINB5	= 5	; Port B Input Pins bit 5
+.equ	PINB6	= 6	; Port B Input Pins bit 6
+.equ	PINB7	= 7	; Port B Input Pins bit 7
+
+
+; ***** PORTC ************************
+; PORTC - Port C Data Register
+.equ	PORTC0	= 0	; Port C Data Register bit 0
+.equ	PC0	= 0	; For compatibility
+.equ	PORTC1	= 1	; Port C Data Register bit 1
+.equ	PC1	= 1	; For compatibility
+.equ	PORTC2	= 2	; Port C Data Register bit 2
+.equ	PC2	= 2	; For compatibility
+.equ	PORTC3	= 3	; Port C Data Register bit 3
+.equ	PC3	= 3	; For compatibility
+.equ	PORTC4	= 4	; Port C Data Register bit 4
+.equ	PC4	= 4	; For compatibility
+.equ	PORTC5	= 5	; Port C Data Register bit 5
+.equ	PC5	= 5	; For compatibility
+.equ	PORTC6	= 6	; Port C Data Register bit 6
+.equ	PC6	= 6	; For compatibility
+
+; DDRC - Port C Data Direction Register
+.equ	DDC0	= 0	; Port C Data Direction Register bit 0
+.equ	DDC1	= 1	; Port C Data Direction Register bit 1
+.equ	DDC2	= 2	; Port C Data Direction Register bit 2
+.equ	DDC3	= 3	; Port C Data Direction Register bit 3
+.equ	DDC4	= 4	; Port C Data Direction Register bit 4
+.equ	DDC5	= 5	; Port C Data Direction Register bit 5
+.equ	DDC6	= 6	; Port C Data Direction Register bit 6
+
+; PINC - Port C Input Pins
+.equ	PINC0	= 0	; Port C Input Pins bit 0
+.equ	PINC1	= 1	; Port C Input Pins bit 1
+.equ	PINC2	= 2	; Port C Input Pins bit 2
+.equ	PINC3	= 3	; Port C Input Pins bit 3
+.equ	PINC4	= 4	; Port C Input Pins bit 4
+.equ	PINC5	= 5	; Port C Input Pins bit 5
+.equ	PINC6	= 6	; Port C Input Pins bit 6
+
+
+; ***** PORTD ************************
+; PORTD - Port D Data Register
+.equ	PORTD0	= 0	; Port D Data Register bit 0
+.equ	PD0	= 0	; For compatibility
+.equ	PORTD1	= 1	; Port D Data Register bit 1
+.equ	PD1	= 1	; For compatibility
+.equ	PORTD2	= 2	; Port D Data Register bit 2
+.equ	PD2	= 2	; For compatibility
+.equ	PORTD3	= 3	; Port D Data Register bit 3
+.equ	PD3	= 3	; For compatibility
+.equ	PORTD4	= 4	; Port D Data Register bit 4
+.equ	PD4	= 4	; For compatibility
+.equ	PORTD5	= 5	; Port D Data Register bit 5
+.equ	PD5	= 5	; For compatibility
+.equ	PORTD6	= 6	; Port D Data Register bit 6
+.equ	PD6	= 6	; For compatibility
+.equ	PORTD7	= 7	; Port D Data Register bit 7
+.equ	PD7	= 7	; For compatibility
+
+; DDRD - Port D Data Direction Register
+.equ	DDD0	= 0	; Port D Data Direction Register bit 0
+.equ	DDD1	= 1	; Port D Data Direction Register bit 1
+.equ	DDD2	= 2	; Port D Data Direction Register bit 2
+.equ	DDD3	= 3	; Port D Data Direction Register bit 3
+.equ	DDD4	= 4	; Port D Data Direction Register bit 4
+.equ	DDD5	= 5	; Port D Data Direction Register bit 5
+.equ	DDD6	= 6	; Port D Data Direction Register bit 6
+.equ	DDD7	= 7	; Port D Data Direction Register bit 7
+
+; PIND - Port D Input Pins
+.equ	PIND0	= 0	; Port D Input Pins bit 0
+.equ	PIND1	= 1	; Port D Input Pins bit 1
+.equ	PIND2	= 2	; Port D Input Pins bit 2
+.equ	PIND3	= 3	; Port D Input Pins bit 3
+.equ	PIND4	= 4	; Port D Input Pins bit 4
+.equ	PIND5	= 5	; Port D Input Pins bit 5
+.equ	PIND6	= 6	; Port D Input Pins bit 6
+.equ	PIND7	= 7	; Port D Input Pins bit 7
+
+
+; ***** TIMER_COUNTER_0 **************
+; TIMSK0 - Timer/Counter0 Interrupt Mask Register
+.equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
+.equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
+.equ	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable
+
+; TIFR0 - Timer/Counter0 Interrupt Flag register
+.equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
+.equ	OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
+.equ	OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B
+
+; TCCR0A - Timer/Counter  Control Register A
+.equ	WGM00	= 0	; Waveform Generation Mode
+.equ	WGM01	= 1	; Waveform Generation Mode
+.equ	COM0B0	= 4	; Compare Output Mode, Fast PWm
+.equ	COM0B1	= 5	; Compare Output Mode, Fast PWm
+.equ	COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
+.equ	COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode
+
+; TCCR0B - Timer/Counter Control Register B
+.equ	CS00	= 0	; Clock Select
+.equ	CS01	= 1	; Clock Select
+.equ	CS02	= 2	; Clock Select
+.equ	WGM02	= 3	; 
+.equ	FOC0B	= 6	; Force Output Compare B
+.equ	FOC0A	= 7	; Force Output Compare A
+
+; TCNT0 - Timer/Counter0
+.equ	TCNT0_0	= 0	; 
+.equ	TCNT0_1	= 1	; 
+.equ	TCNT0_2	= 2	; 
+.equ	TCNT0_3	= 3	; 
+.equ	TCNT0_4	= 4	; 
+.equ	TCNT0_5	= 5	; 
+.equ	TCNT0_6	= 6	; 
+.equ	TCNT0_7	= 7	; 
+
+; OCR0A - Timer/Counter0 Output Compare Register
+.equ	OCR0A_0	= 0	; 
+.equ	OCR0A_1	= 1	; 
+.equ	OCR0A_2	= 2	; 
+.equ	OCR0A_3	= 3	; 
+.equ	OCR0A_4	= 4	; 
+.equ	OCR0A_5	= 5	; 
+.equ	OCR0A_6	= 6	; 
+.equ	OCR0A_7	= 7	; 
+
+; OCR0B - Timer/Counter0 Output Compare Register
+.equ	OCR0B_0	= 0	; 
+.equ	OCR0B_1	= 1	; 
+.equ	OCR0B_2	= 2	; 
+.equ	OCR0B_3	= 3	; 
+.equ	OCR0B_4	= 4	; 
+.equ	OCR0B_5	= 5	; 
+.equ	OCR0B_6	= 6	; 
+.equ	OCR0B_7	= 7	; 
+
+; GTCCR - General Timer/Counter Control Register
+;.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
+.equ	PSR10	= PSRSYNC	; For compatibility
+;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
+
+
+; ***** EXTERNAL_INTERRUPT ***********
+; EICRA - External Interrupt Control Register
+.equ	ISC00	= 0	; External Interrupt Sense Control 0 Bit 0
+.equ	ISC01	= 1	; External Interrupt Sense Control 0 Bit 1
+.equ	ISC10	= 2	; External Interrupt Sense Control 1 Bit 0
+.equ	ISC11	= 3	; External Interrupt Sense Control 1 Bit 1
+
+; EIMSK - External Interrupt Mask Register
+.equ	INT0	= 0	; External Interrupt Request 0 Enable
+.equ	INT1	= 1	; External Interrupt Request 1 Enable
+
+; EIFR - External Interrupt Flag Register
+.equ	INTF0	= 0	; External Interrupt Flag 0
+.equ	INTF1	= 1	; External Interrupt Flag 1
+
+; PCICR - Pin Change Interrupt Control Register
+.equ	PCIE0	= 0	; Pin Change Interrupt Enable 0
+.equ	PCIE1	= 1	; Pin Change Interrupt Enable 1
+.equ	PCIE2	= 2	; Pin Change Interrupt Enable 2
+
+; PCMSK2 - Pin Change Mask Register 2
+.equ	PCINT16	= 0	; Pin Change Enable Mask 16
+.equ	PCINT17	= 1	; Pin Change Enable Mask 17
+.equ	PCINT18	= 2	; Pin Change Enable Mask 18
+.equ	PCINT19	= 3	; Pin Change Enable Mask 19
+.equ	PCINT20	= 4	; Pin Change Enable Mask 20
+.equ	PCINT21	= 5	; Pin Change Enable Mask 21
+.equ	PCINT22	= 6	; Pin Change Enable Mask 22
+.equ	PCINT23	= 7	; Pin Change Enable Mask 23
+
+; PCMSK1 - Pin Change Mask Register 1
+.equ	PCINT8	= 0	; Pin Change Enable Mask 8
+.equ	PCINT9	= 1	; Pin Change Enable Mask 9
+.equ	PCINT10	= 2	; Pin Change Enable Mask 10
+.equ	PCINT11	= 3	; Pin Change Enable Mask 11
+.equ	PCINT12	= 4	; Pin Change Enable Mask 12
+.equ	PCINT13	= 5	; Pin Change Enable Mask 13
+.equ	PCINT14	= 6	; Pin Change Enable Mask 14
+
+; PCMSK0 - Pin Change Mask Register 0
+.equ	PCINT0	= 0	; Pin Change Enable Mask 0
+.equ	PCINT1	= 1	; Pin Change Enable Mask 1
+.equ	PCINT2	= 2	; Pin Change Enable Mask 2
+.equ	PCINT3	= 3	; Pin Change Enable Mask 3
+.equ	PCINT4	= 4	; Pin Change Enable Mask 4
+.equ	PCINT5	= 5	; Pin Change Enable Mask 5
+.equ	PCINT6	= 6	; Pin Change Enable Mask 6
+.equ	PCINT7	= 7	; Pin Change Enable Mask 7
+
+; PCIFR - Pin Change Interrupt Flag Register
+.equ	PCIF0	= 0	; Pin Change Interrupt Flag 0
+.equ	PCIF1	= 1	; Pin Change Interrupt Flag 1
+.equ	PCIF2	= 2	; Pin Change Interrupt Flag 2
+
+
+; ***** SPI **************************
+; SPDR - SPI Data Register
+.equ	SPDR0	= 0	; SPI Data Register bit 0
+.equ	SPDR1	= 1	; SPI Data Register bit 1
+.equ	SPDR2	= 2	; SPI Data Register bit 2
+.equ	SPDR3	= 3	; SPI Data Register bit 3
+.equ	SPDR4	= 4	; SPI Data Register bit 4
+.equ	SPDR5	= 5	; SPI Data Register bit 5
+.equ	SPDR6	= 6	; SPI Data Register bit 6
+.equ	SPDR7	= 7	; SPI Data Register bit 7
+
+; SPSR - SPI Status Register
+.equ	SPI2X	= 0	; Double SPI Speed Bit
+.equ	WCOL	= 6	; Write Collision Flag
+.equ	SPIF	= 7	; SPI Interrupt Flag
+
+; SPCR - SPI Control Register
+.equ	SPR0	= 0	; SPI Clock Rate Select 0
+.equ	SPR1	= 1	; SPI Clock Rate Select 1
+.equ	CPHA	= 2	; Clock Phase
+.equ	CPOL	= 3	; Clock polarity
+.equ	MSTR	= 4	; Master/Slave Select
+.equ	DORD	= 5	; Data Order
+.equ	SPE	= 6	; SPI Enable
+.equ	SPIE	= 7	; SPI Interrupt Enable
+
+
+; ***** CPU **************************
+; SREG - Status Register
+.equ	SREG_C	= 0	; Carry Flag
+.equ	SREG_Z	= 1	; Zero Flag
+.equ	SREG_N	= 2	; Negative Flag
+.equ	SREG_V	= 3	; Two's Complement Overflow Flag
+.equ	SREG_S	= 4	; Sign Bit
+.equ	SREG_H	= 5	; Half Carry Flag
+.equ	SREG_T	= 6	; Bit Copy Storage
+.equ	SREG_I	= 7	; Global Interrupt Enable
+
+; OSCCAL - Oscillator Calibration Value
+.equ	CAL0	= 0	; Oscillator Calibration Value Bit0
+.equ	CAL1	= 1	; Oscillator Calibration Value Bit1
+.equ	CAL2	= 2	; Oscillator Calibration Value Bit2
+.equ	CAL3	= 3	; Oscillator Calibration Value Bit3
+.equ	CAL4	= 4	; Oscillator Calibration Value Bit4
+.equ	CAL5	= 5	; Oscillator Calibration Value Bit5
+.equ	CAL6	= 6	; Oscillator Calibration Value Bit6
+.equ	CAL7	= 7	; Oscillator Calibration Value Bit7
+
+; CLKPR - Clock Prescale Register
+.equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
+.equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
+.equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
+.equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
+.equ	CLKPCE	= 7	; Clock Prescaler Change Enable
+
+; SPMCSR - Store Program Memory Control Register
+.equ	SELFPRGEN	= 0	; Self Programming Enable
+.equ	PGERS	= 1	; Page Erase
+.equ	PGWRT	= 2	; Page Write
+.equ	BLBSET	= 3	; Boot Lock Bit Set
+.equ	RWWSRE	= 4	; Read-While-Write section read enable
+.equ	RWWSB	= 6	; Read-While-Write Section Busy
+.equ	SPMIE	= 7	; SPM Interrupt Enable
+
+; MCUCR - MCU Control Register
+.equ	PUD	= 4	; 
+
+; MCUSR - MCU Status Register
+.equ	PORF	= 0	; Power-on reset flag
+.equ	EXTRF	= 1	; External Reset Flag
+.equ	EXTREF	= EXTRF	; For compatibility
+.equ	BORF	= 2	; Brown-out Reset Flag
+.equ	WDRF	= 3	; Watchdog Reset Flag
+
+; SMCR - 
+.equ	SE	= 0	; 
+.equ	SM0	= 1	; 
+.equ	SM1	= 2	; 
+.equ	SM2	= 3	; 
+
+; GPIOR2 - General Purpose I/O Register 2
+.equ	GPIOR20	= 0	; 
+.equ	GPIOR21	= 1	; 
+.equ	GPIOR22	= 2	; 
+.equ	GPIOR23	= 3	; 
+.equ	GPIOR24	= 4	; 
+.equ	GPIOR25	= 5	; 
+.equ	GPIOR26	= 6	; 
+.equ	GPIOR27	= 7	; 
+
+; GPIOR1 - General Purpose I/O Register 1
+.equ	GPIOR10	= 0	; 
+.equ	GPIOR11	= 1	; 
+.equ	GPIOR12	= 2	; 
+.equ	GPIOR13	= 3	; 
+.equ	GPIOR14	= 4	; 
+.equ	GPIOR15	= 5	; 
+.equ	GPIOR16	= 6	; 
+.equ	GPIOR17	= 7	; 
+
+; GPIOR0 - General Purpose I/O Register 0
+.equ	GPIOR00	= 0	; 
+.equ	GPIOR01	= 1	; 
+.equ	GPIOR02	= 2	; 
+.equ	GPIOR03	= 3	; 
+.equ	GPIOR04	= 4	; 
+.equ	GPIOR05	= 5	; 
+.equ	GPIOR06	= 6	; 
+.equ	GPIOR07	= 7	; 
+
+; PRR - Power Reduction Register
+.equ	PRADC	= 0	; Power Reduction ADC
+.equ	PRUSART0	= 1	; Power Reduction USART
+.equ	PRSPI	= 2	; Power Reduction Serial Peripheral Interface
+.equ	PRTIM1	= 3	; Power Reduction Timer/Counter1
+.equ	PRTIM0	= 5	; Power Reduction Timer/Counter0
+.equ	PRTIM2	= 6	; Power Reduction Timer/Counter2
+.equ	PRTWI	= 7	; Power Reduction TWI
+
+
+; ***** WATCHDOG *********************
+; WDTCSR - Watchdog Timer Control Register
+.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
+.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
+.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
+.equ	WDE	= 3	; Watch Dog Enable
+.equ	WDCE	= 4	; Watchdog Change Enable
+.equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
+.equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
+.equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag
+
+
+; ***** EEPROM ***********************
+; EEARL - EEPROM Address Register Low Byte
+.equ	EEAR0	= 0	; EEPROM Read/Write Access Bit 0
+.equ	EEAR1	= 1	; EEPROM Read/Write Access Bit 1
+.equ	EEAR2	= 2	; EEPROM Read/Write Access Bit 2
+.equ	EEAR3	= 3	; EEPROM Read/Write Access Bit 3
+.equ	EEAR4	= 4	; EEPROM Read/Write Access Bit 4
+.equ	EEAR5	= 5	; EEPROM Read/Write Access Bit 5
+.equ	EEAR6	= 6	; EEPROM Read/Write Access Bit 6
+.equ	EEAR7	= 7	; EEPROM Read/Write Access Bit 7
+
+; EEDR - EEPROM Data Register
+.equ	EEDR0	= 0	; EEPROM Data Register bit 0
+.equ	EEDR1	= 1	; EEPROM Data Register bit 1
+.equ	EEDR2	= 2	; EEPROM Data Register bit 2
+.equ	EEDR3	= 3	; EEPROM Data Register bit 3
+.equ	EEDR4	= 4	; EEPROM Data Register bit 4
+.equ	EEDR5	= 5	; EEPROM Data Register bit 5
+.equ	EEDR6	= 6	; EEPROM Data Register bit 6
+.equ	EEDR7	= 7	; EEPROM Data Register bit 7
+
+; EECR - EEPROM Control Register
+.equ	EERE	= 0	; EEPROM Read Enable
+.equ	EEPE	= 1	; EEPROM Write Enable
+.equ	EEWE	= EEPE	; For compatibility
+.equ	EEMPE	= 2	; EEPROM Master Write Enable
+.equ	EEMWE	= EEMPE	; For compatibility
+.equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
+.equ	EEPM0	= 4	; EEPROM Programming Mode Bit 0
+.equ	EEPM1	= 5	; EEPROM Programming Mode Bit 1
+
+
+
+; ***** LOCKSBITS ********************************************************
+.equ	LB1	= 0	; Lockbit
+.equ	LB2	= 1	; Lockbit
+
+
+; ***** FUSES ************************************************************
+; LOW fuse bits
+.equ	CKSEL0	= 0	; Select Clock Source
+.equ	CKSEL1	= 1	; Select Clock Source
+.equ	CKSEL2	= 2	; Select Clock Source
+.equ	CKSEL3	= 3	; Select Clock Source
+.equ	SUT0	= 4	; Select start-up time
+.equ	SUT1	= 5	; Select start-up time
+.equ	CKOUT	= 6	; Clock output
+.equ	CKDIV8	= 7	; Divide clock by 8
+
+; HIGH fuse bits
+.equ	BODLEVEL0	= 0	; Brown-out Detector trigger level
+.equ	BODLEVEL1	= 1	; Brown-out Detector trigger level
+.equ	BODLEVEL2	= 2	; Brown-out Detector trigger level
+.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
+.equ	WDTON	= 4	; Watchdog Timer Always On
+.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
+.equ	DWEN	= 6	; debugWIRE Enable
+.equ	RSTDISBL	= 7	; External reset disable
+
+; EXTENDED fuse bits
+;.equ	SELFPRGEN	= 0	; Self Programming Enable
+
+
+
+; ***** CPU REGISTER DEFINITIONS *****************************************
+.def	XH	= r27
+.def	XL	= r26
+.def	YH	= r29
+.def	YL	= r28
+.def	ZH	= r31
+.def	ZL	= r30
+
+
+
+; ***** DATA MEMORY DECLARATIONS *****************************************
+.equ	FLASHEND	= 0x07ff	; Note: Word address
+.equ	IOEND	= 0x00ff
+.equ	SRAM_START	= 0x0100
+.equ	SRAM_SIZE	= 512
+.equ	RAMEND	= 0x02ff
+.equ	XRAMEND	= 0x0000
+.equ	E2END	= 0x00ff
+.equ	EEPROMEND	= 0x00ff
+.equ	EEADRBITS	= 8
+#pragma AVRPART MEMORY PROG_FLASH 4096
+#pragma AVRPART MEMORY EEPROM 256
+#pragma AVRPART MEMORY INT_SRAM SIZE 512
+#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
+
+
+
+; ***** BOOTLOADER DECLARATIONS ******************************************
+.equ	NRWW_START_ADDR	= 0x0
+.equ	NRWW_STOP_ADDR	= 0x7ff
+.equ	RWW_START_ADDR	= 0x0
+.equ	RWW_STOP_ADDR	= 0x0
+.equ	PAGESIZE	= 32
+
+
+
+; ***** INTERRUPT VECTORS ************************************************
+.equ	INT0addr	= 0x0001	; External Interrupt Request 0
+.equ	INT1addr	= 0x0002	; External Interrupt Request 1
+.equ	PCI0addr	= 0x0003	; Pin Change Interrupt Request 0
+.equ	PCI1addr	= 0x0004	; Pin Change Interrupt Request 0
+.equ	PCI2addr	= 0x0005	; Pin Change Interrupt Request 1
+.equ	WDTaddr	= 0x0006	; Watchdog Time-out Interrupt
+.equ	OC2Aaddr	= 0x0007	; Timer/Counter2 Compare Match A
+.equ	OC2Baddr	= 0x0008	; Timer/Counter2 Compare Match A
+.equ	OVF2addr	= 0x0009	; Timer/Counter2 Overflow
+.equ	ICP1addr	= 0x000a	; Timer/Counter1 Capture Event
+.equ	OC1Aaddr	= 0x000b	; Timer/Counter1 Compare Match A
+.equ	OC1Baddr	= 0x000c	; Timer/Counter1 Compare Match B
+.equ	OVF1addr	= 0x000d	; Timer/Counter1 Overflow
+.equ	OC0Aaddr	= 0x000e	; TimerCounter0 Compare Match A
+.equ	OC0Baddr	= 0x000f	; TimerCounter0 Compare Match B
+.equ	OVF0addr	= 0x0010	; Timer/Couner0 Overflow
+.equ	SPIaddr	= 0x0011	; SPI Serial Transfer Complete
+.equ	URXCaddr	= 0x0012	; USART Rx Complete
+.equ	UDREaddr	= 0x0013	; USART, Data Register Empty
+.equ	UTXCaddr	= 0x0014	; USART Tx Complete
+.equ	ADCCaddr	= 0x0015	; ADC Conversion Complete
+.equ	ERDYaddr	= 0x0016	; EEPROM Ready
+.equ	ACIaddr	= 0x0017	; Analog Comparator
+.equ	TWIaddr	= 0x0018	; Two-wire Serial Interface
+.equ	SPMRaddr	= 0x0019	; Store Program Memory Read
+
+.equ	INT_VECTORS_SIZE	= 26	; size in words
+
+#endif  /* _M48DEF_INC_ */
+
+; ***** END OF FILE ******************************************************

Atmel/m88Pdef.inc

@@ -0,0 +1,976 @@
+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
+;***** Created: 2009-11-03 14:40 ******* Source: ATmega88P.xml ***********
+;*************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number            : AVR000
+;* File Name         : "m88Pdef.inc"
+;* Title             : Register/Bit Definitions for the ATmega88P
+;* Date              : 2009-11-03
+;* Version           : 2.35
+;* Support E-mail    : avr@atmel.com
+;* Target MCU        : ATmega88P
+;* 
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register 
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and 
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;* 
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in    r16,PORTB             ;read PORTB latch
+;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
+;* out   PORTB,r16             ;output to PORTB
+;* 
+;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
+;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
+;* rjmp  TOV0_is_set           ;jump if set
+;* ...                         ;otherwise do something else
+;*************************************************************************
+
+#ifndef _M88PDEF_INC_
+#define _M88PDEF_INC_
+
+
+#pragma partinc 0
+
+; ***** SPECIFY DEVICE ***************************************************
+.device ATmega88P
+#pragma AVRPART ADMIN PART_NAME ATmega88P
+.equ	SIGNATURE_000	= 0x1e
+.equ	SIGNATURE_001	= 0x93
+.equ	SIGNATURE_002	= 0x0f
+
+#pragma AVRPART CORE CORE_VERSION V2E
+
+
+; ***** I/O REGISTER DEFINITIONS *****************************************
+; NOTE:
+; Definitions marked "MEMORY MAPPED"are extended I/O ports
+; and cannot be used with IN/OUT instructions
+.equ	UDR0	= 0xc6	; MEMORY MAPPED
+.equ	UBRR0L	= 0xc4	; MEMORY MAPPED
+.equ	UBRR0H	= 0xc5	; MEMORY MAPPED
+.equ	UCSR0C	= 0xc2	; MEMORY MAPPED
+.equ	UCSR0B	= 0xc1	; MEMORY MAPPED
+.equ	UCSR0A	= 0xc0	; MEMORY MAPPED
+.equ	TWAMR	= 0xbd	; MEMORY MAPPED
+.equ	TWCR	= 0xbc	; MEMORY MAPPED
+.equ	TWDR	= 0xbb	; MEMORY MAPPED
+.equ	TWAR	= 0xba	; MEMORY MAPPED
+.equ	TWSR	= 0xb9	; MEMORY MAPPED
+.equ	TWBR	= 0xb8	; MEMORY MAPPED
+.equ	ASSR	= 0xb6	; MEMORY MAPPED
+.equ	OCR2B	= 0xb4	; MEMORY MAPPED
+.equ	OCR2A	= 0xb3	; MEMORY MAPPED
+.equ	TCNT2	= 0xb2	; MEMORY MAPPED
+.equ	TCCR2B	= 0xb1	; MEMORY MAPPED
+.equ	TCCR2A	= 0xb0	; MEMORY MAPPED
+.equ	OCR1BL	= 0x8a	; MEMORY MAPPED
+.equ	OCR1BH	= 0x8b	; MEMORY MAPPED
+.equ	OCR1AL	= 0x88	; MEMORY MAPPED
+.equ	OCR1AH	= 0x89	; MEMORY MAPPED
+.equ	ICR1L	= 0x86	; MEMORY MAPPED
+.equ	ICR1H	= 0x87	; MEMORY MAPPED
+.equ	TCNT1L	= 0x84	; MEMORY MAPPED
+.equ	TCNT1H	= 0x85	; MEMORY MAPPED
+.equ	TCCR1C	= 0x82	; MEMORY MAPPED
+.equ	TCCR1B	= 0x81	; MEMORY MAPPED
+.equ	TCCR1A	= 0x80	; MEMORY MAPPED
+.equ	DIDR1	= 0x7f	; MEMORY MAPPED
+.equ	DIDR0	= 0x7e	; MEMORY MAPPED
+.equ	ADMUX	= 0x7c	; MEMORY MAPPED
+.equ	ADCSRB	= 0x7b	; MEMORY MAPPED
+.equ	ADCSRA	= 0x7a	; MEMORY MAPPED
+.equ	ADCH	= 0x79	; MEMORY MAPPED
+.equ	ADCL	= 0x78	; MEMORY MAPPED
+.equ	TIMSK2	= 0x70	; MEMORY MAPPED
+.equ	TIMSK1	= 0x6f	; MEMORY MAPPED
+.equ	TIMSK0	= 0x6e	; MEMORY MAPPED
+.equ	PCMSK1	= 0x6c	; MEMORY MAPPED
+.equ	PCMSK2	= 0x6d	; MEMORY MAPPED
+.equ	PCMSK0	= 0x6b	; MEMORY MAPPED
+.equ	EICRA	= 0x69	; MEMORY MAPPED
+.equ	PCICR	= 0x68	; MEMORY MAPPED
+.equ	OSCCAL	= 0x66	; MEMORY MAPPED
+.equ	PRR	= 0x64	; MEMORY MAPPED
+.equ	CLKPR	= 0x61	; MEMORY MAPPED
+.equ	WDTCSR	= 0x60	; MEMORY MAPPED
+.equ	SREG	= 0x3f
+.equ	SPL	= 0x3d
+.equ	SPH	= 0x3e
+.equ	SPMCSR	= 0x37
+.equ	MCUCR	= 0x35
+.equ	MCUSR	= 0x34
+.equ	SMCR	= 0x33
+.equ	ACSR	= 0x30
+.equ	SPDR	= 0x2e
+.equ	SPSR	= 0x2d
+.equ	SPCR	= 0x2c
+.equ	GPIOR2	= 0x2b
+.equ	GPIOR1	= 0x2a
+.equ	OCR0B	= 0x28
+.equ	OCR0A	= 0x27
+.equ	TCNT0	= 0x26
+.equ	TCCR0B	= 0x25
+.equ	TCCR0A	= 0x24
+.equ	GTCCR	= 0x23
+.equ	EEARH	= 0x22
+.equ	EEARL	= 0x21
+.equ	EEDR	= 0x20
+.equ	EECR	= 0x1f
+.equ	GPIOR0	= 0x1e
+.equ	EIMSK	= 0x1d
+.equ	EIFR	= 0x1c
+.equ	PCIFR	= 0x1b
+.equ	TIFR2	= 0x17
+.equ	TIFR1	= 0x16
+.equ	TIFR0	= 0x15
+.equ	PORTD	= 0x0b
+.equ	DDRD	= 0x0a
+.equ	PIND	= 0x09
+.equ	PORTC	= 0x08
+.equ	DDRC	= 0x07
+.equ	PINC	= 0x06
+.equ	PORTB	= 0x05
+.equ	DDRB	= 0x04
+.equ	PINB	= 0x03
+
+
+; ***** BIT DEFINITIONS **************************************************
+
+; ***** USART0 ***********************
+; UDR0 - USART I/O Data Register
+.equ	UDR0_0	= 0	; USART I/O Data Register bit 0
+.equ	UDR0_1	= 1	; USART I/O Data Register bit 1
+.equ	UDR0_2	= 2	; USART I/O Data Register bit 2
+.equ	UDR0_3	= 3	; USART I/O Data Register bit 3
+.equ	UDR0_4	= 4	; USART I/O Data Register bit 4
+.equ	UDR0_5	= 5	; USART I/O Data Register bit 5
+.equ	UDR0_6	= 6	; USART I/O Data Register bit 6
+.equ	UDR0_7	= 7	; USART I/O Data Register bit 7
+
+; UCSR0A - USART Control and Status Register A
+.equ	MPCM0	= 0	; Multi-processor Communication Mode
+.equ	U2X0	= 1	; Double the USART transmission speed
+.equ	UPE0	= 2	; Parity Error
+.equ	DOR0	= 3	; Data overRun
+.equ	FE0	= 4	; Framing Error
+.equ	UDRE0	= 5	; USART Data Register Empty
+.equ	TXC0	= 6	; USART Transmitt Complete
+.equ	RXC0	= 7	; USART Receive Complete
+
+; UCSR0B - USART Control and Status Register B
+.equ	TXB80	= 0	; Transmit Data Bit 8
+.equ	RXB80	= 1	; Receive Data Bit 8
+.equ	UCSZ02	= 2	; Character Size
+.equ	TXEN0	= 3	; Transmitter Enable
+.equ	RXEN0	= 4	; Receiver Enable
+.equ	UDRIE0	= 5	; USART Data register Empty Interrupt Enable
+.equ	TXCIE0	= 6	; TX Complete Interrupt Enable
+.equ	RXCIE0	= 7	; RX Complete Interrupt Enable
+
+; UCSR0C - USART Control and Status Register C
+.equ	UCPOL0	= 0	; Clock Polarity
+.equ	UCSZ00	= 1	; Character Size
+.equ	UCPHA0	= UCSZ00	; For compatibility
+.equ	UCSZ01	= 2	; Character Size
+.equ	UDORD0	= UCSZ01	; For compatibility
+.equ	USBS0	= 3	; Stop Bit Select
+.equ	UPM00	= 4	; Parity Mode Bit 0
+.equ	UPM01	= 5	; Parity Mode Bit 1
+.equ	UMSEL00	= 6	; USART Mode Select
+.equ	UMSEL0	= UMSEL00	; For compatibility
+.equ	UMSEL01	= 7	; USART Mode Select
+.equ	UMSEL1	= UMSEL01	; For compatibility
+
+; UBRR0H - USART Baud Rate Register High Byte
+.equ	UBRR8	= 0	; USART Baud Rate Register bit 8
+.equ	UBRR9	= 1	; USART Baud Rate Register bit 9
+.equ	UBRR10	= 2	; USART Baud Rate Register bit 10
+.equ	UBRR11	= 3	; USART Baud Rate Register bit 11
+
+; UBRR0L - USART Baud Rate Register Low Byte
+.equ	_UBRR0	= 0	; USART Baud Rate Register bit 0
+.equ	_UBRR1	= 1	; USART Baud Rate Register bit 1
+.equ	UBRR2	= 2	; USART Baud Rate Register bit 2
+.equ	UBRR3	= 3	; USART Baud Rate Register bit 3
+.equ	UBRR4	= 4	; USART Baud Rate Register bit 4
+.equ	UBRR5	= 5	; USART Baud Rate Register bit 5
+.equ	UBRR6	= 6	; USART Baud Rate Register bit 6
+.equ	UBRR7	= 7	; USART Baud Rate Register bit 7
+
+
+; ***** TWI **************************
+; TWAMR - TWI (Slave) Address Mask Register
+.equ	TWAM0	= 1	; 
+.equ	TWAMR0	= TWAM0	; For compatibility
+.equ	TWAM1	= 2	; 
+.equ	TWAMR1	= TWAM1	; For compatibility
+.equ	TWAM2	= 3	; 
+.equ	TWAMR2	= TWAM2	; For compatibility
+.equ	TWAM3	= 4	; 
+.equ	TWAMR3	= TWAM3	; For compatibility
+.equ	TWAM4	= 5	; 
+.equ	TWAMR4	= TWAM4	; For compatibility
+.equ	TWAM5	= 6	; 
+.equ	TWAMR5	= TWAM5	; For compatibility
+.equ	TWAM6	= 7	; 
+.equ	TWAMR6	= TWAM6	; For compatibility
+
+; TWBR - TWI Bit Rate register
+.equ	TWBR0	= 0	; 
+.equ	TWBR1	= 1	; 
+.equ	TWBR2	= 2	; 
+.equ	TWBR3	= 3	; 
+.equ	TWBR4	= 4	; 
+.equ	TWBR5	= 5	; 
+.equ	TWBR6	= 6	; 
+.equ	TWBR7	= 7	; 
+
+; TWCR - TWI Control Register
+.equ	TWIE	= 0	; TWI Interrupt Enable
+.equ	TWEN	= 2	; TWI Enable Bit
+.equ	TWWC	= 3	; TWI Write Collition Flag
+.equ	TWSTO	= 4	; TWI Stop Condition Bit
+.equ	TWSTA	= 5	; TWI Start Condition Bit
+.equ	TWEA	= 6	; TWI Enable Acknowledge Bit
+.equ	TWINT	= 7	; TWI Interrupt Flag
+
+; TWSR - TWI Status Register
+.equ	TWPS0	= 0	; TWI Prescaler
+.equ	TWPS1	= 1	; TWI Prescaler
+.equ	TWS3	= 3	; TWI Status
+.equ	TWS4	= 4	; TWI Status
+.equ	TWS5	= 5	; TWI Status
+.equ	TWS6	= 6	; TWI Status
+.equ	TWS7	= 7	; TWI Status
+
+; TWDR - TWI Data register
+.equ	TWD0	= 0	; TWI Data Register Bit 0
+.equ	TWD1	= 1	; TWI Data Register Bit 1
+.equ	TWD2	= 2	; TWI Data Register Bit 2
+.equ	TWD3	= 3	; TWI Data Register Bit 3
+.equ	TWD4	= 4	; TWI Data Register Bit 4
+.equ	TWD5	= 5	; TWI Data Register Bit 5
+.equ	TWD6	= 6	; TWI Data Register Bit 6
+.equ	TWD7	= 7	; TWI Data Register Bit 7
+
+; TWAR - TWI (Slave) Address register
+.equ	TWGCE	= 0	; TWI General Call Recognition Enable Bit
+.equ	TWA0	= 1	; TWI (Slave) Address register Bit 0
+.equ	TWA1	= 2	; TWI (Slave) Address register Bit 1
+.equ	TWA2	= 3	; TWI (Slave) Address register Bit 2
+.equ	TWA3	= 4	; TWI (Slave) Address register Bit 3
+.equ	TWA4	= 5	; TWI (Slave) Address register Bit 4
+.equ	TWA5	= 6	; TWI (Slave) Address register Bit 5
+.equ	TWA6	= 7	; TWI (Slave) Address register Bit 6
+
+
+; ***** TIMER_COUNTER_1 **************
+; TIMSK1 - Timer/Counter Interrupt Mask Register
+.equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
+.equ	OCIE1A	= 1	; Timer/Counter1 Output CompareA Match Interrupt Enable
+.equ	OCIE1B	= 2	; Timer/Counter1 Output CompareB Match Interrupt Enable
+.equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
+
+; TIFR1 - Timer/Counter Interrupt Flag register
+.equ	TOV1	= 0	; Timer/Counter1 Overflow Flag
+.equ	OCF1A	= 1	; Output Compare Flag 1A
+.equ	OCF1B	= 2	; Output Compare Flag 1B
+.equ	ICF1	= 5	; Input Capture Flag 1
+
+; TCCR1A - Timer/Counter1 Control Register A
+.equ	WGM10	= 0	; Waveform Generation Mode
+.equ	WGM11	= 1	; Waveform Generation Mode
+.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
+.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
+.equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
+.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
+
+; TCCR1B - Timer/Counter1 Control Register B
+.equ	CS10	= 0	; Prescaler source of Timer/Counter 1
+.equ	CS11	= 1	; Prescaler source of Timer/Counter 1
+.equ	CS12	= 2	; Prescaler source of Timer/Counter 1
+.equ	WGM12	= 3	; Waveform Generation Mode
+.equ	WGM13	= 4	; Waveform Generation Mode
+.equ	ICES1	= 6	; Input Capture 1 Edge Select
+.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
+
+; TCCR1C - Timer/Counter1 Control Register C
+.equ	FOC1B	= 6	; 
+.equ	FOC1A	= 7	; 
+
+; GTCCR - General Timer/Counter Control Register
+.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
+.equ	TSM	= 7	; Timer/Counter Synchronization Mode
+
+
+; ***** TIMER_COUNTER_2 **************
+; TIMSK2 - Timer/Counter Interrupt Mask register
+.equ	TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable
+.equ	TOIE2A	= TOIE2	; For compatibility
+.equ	OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable
+.equ	OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable
+
+; TIFR2 - Timer/Counter Interrupt Flag Register
+.equ	TOV2	= 0	; Timer/Counter2 Overflow Flag
+.equ	OCF2A	= 1	; Output Compare Flag 2A
+.equ	OCF2B	= 2	; Output Compare Flag 2B
+
+; TCCR2A - Timer/Counter2 Control Register A
+.equ	WGM20	= 0	; Waveform Genration Mode
+.equ	WGM21	= 1	; Waveform Genration Mode
+.equ	COM2B0	= 4	; Compare Output Mode bit 0
+.equ	COM2B1	= 5	; Compare Output Mode bit 1
+.equ	COM2A0	= 6	; Compare Output Mode bit 1
+.equ	COM2A1	= 7	; Compare Output Mode bit 1
+
+; TCCR2B - Timer/Counter2 Control Register B
+.equ	CS20	= 0	; Clock Select bit 0
+.equ	CS21	= 1	; Clock Select bit 1
+.equ	CS22	= 2	; Clock Select bit 2
+.equ	WGM22	= 3	; Waveform Generation Mode
+.equ	FOC2B	= 6	; Force Output Compare B
+.equ	FOC2A	= 7	; Force Output Compare A
+
+; TCNT2 - Timer/Counter2
+.equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0
+.equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1
+.equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2
+.equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3
+.equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4
+.equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5
+.equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6
+.equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7
+
+; OCR2A - Timer/Counter2 Output Compare Register A
+.equ	OCR2A_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
+.equ	OCR2A_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
+.equ	OCR2A_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
+.equ	OCR2A_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
+.equ	OCR2A_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
+.equ	OCR2A_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
+.equ	OCR2A_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
+.equ	OCR2A_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
+
+; OCR2B - Timer/Counter2 Output Compare Register B
+.equ	OCR2B_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
+.equ	OCR2B_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
+.equ	OCR2B_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
+.equ	OCR2B_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
+.equ	OCR2B_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
+.equ	OCR2B_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
+.equ	OCR2B_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
+.equ	OCR2B_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
+
+; ASSR - Asynchronous Status Register
+.equ	TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy
+.equ	TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy
+.equ	OCR2BUB	= 2	; Output Compare Register 2 Update Busy
+.equ	OCR2AUB	= 3	; Output Compare Register2 Update Busy
+.equ	TCN2UB	= 4	; Timer/Counter2 Update Busy
+.equ	AS2	= 5	; Asynchronous Timer/Counter2
+.equ	EXCLK	= 6	; Enable External Clock Input
+
+; GTCCR - General Timer Counter Control register
+.equ	PSRASY	= 1	; Prescaler Reset Timer/Counter2
+.equ	PSR2	= PSRASY	; For compatibility
+;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
+
+
+; ***** AD_CONVERTER *****************
+; ADMUX - The ADC multiplexer Selection Register
+.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
+.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
+.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
+.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
+.equ	ADLAR	= 5	; Left Adjust Result
+.equ	REFS0	= 6	; Reference Selection Bit 0
+.equ	REFS1	= 7	; Reference Selection Bit 1
+
+; ADCSRA - The ADC Control and Status register A
+.equ	ADPS0	= 0	; ADC  Prescaler Select Bits
+.equ	ADPS1	= 1	; ADC  Prescaler Select Bits
+.equ	ADPS2	= 2	; ADC  Prescaler Select Bits
+.equ	ADIE	= 3	; ADC Interrupt Enable
+.equ	ADIF	= 4	; ADC Interrupt Flag
+.equ	ADATE	= 5	; ADC  Auto Trigger Enable
+.equ	ADSC	= 6	; ADC Start Conversion
+.equ	ADEN	= 7	; ADC Enable
+
+; ADCSRB - The ADC Control and Status register B
+.equ	ADTS0	= 0	; ADC Auto Trigger Source bit 0
+.equ	ADTS1	= 1	; ADC Auto Trigger Source bit 1
+.equ	ADTS2	= 2	; ADC Auto Trigger Source bit 2
+.equ	ACME	= 6	; 
+
+; ADCH - ADC Data Register High Byte
+.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
+.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
+.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
+.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
+.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
+.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
+.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
+.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
+
+; ADCL - ADC Data Register Low Byte
+.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
+.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
+.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
+.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
+.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
+.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
+.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
+.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
+
+; DIDR0 - Digital Input Disable Register
+.equ	ADC0D	= 0	; 
+.equ	ADC1D	= 1	; 
+.equ	ADC2D	= 2	; 
+.equ	ADC3D	= 3	; 
+.equ	ADC4D	= 4	; 
+.equ	ADC5D	= 5	; 
+
+
+; ***** ANALOG_COMPARATOR ************
+; ACSR - Analog Comparator Control And Status Register
+.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
+.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
+.equ	ACIC	= 2	; Analog Comparator Input Capture Enable
+.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
+.equ	ACI	= 4	; Analog Comparator Interrupt Flag
+.equ	ACO	= 5	; Analog Compare Output
+.equ	ACBG	= 6	; Analog Comparator Bandgap Select
+.equ	ACD	= 7	; Analog Comparator Disable
+
+; DIDR1 - Digital Input Disable Register 1
+.equ	AIN0D	= 0	; AIN0 Digital Input Disable
+.equ	AIN1D	= 1	; AIN1 Digital Input Disable
+
+
+; ***** PORTB ************************
+; PORTB - Port B Data Register
+.equ	PORTB0	= 0	; Port B Data Register bit 0
+.equ	PB0	= 0	; For compatibility
+.equ	PORTB1	= 1	; Port B Data Register bit 1
+.equ	PB1	= 1	; For compatibility
+.equ	PORTB2	= 2	; Port B Data Register bit 2
+.equ	PB2	= 2	; For compatibility
+.equ	PORTB3	= 3	; Port B Data Register bit 3
+.equ	PB3	= 3	; For compatibility
+.equ	PORTB4	= 4	; Port B Data Register bit 4
+.equ	PB4	= 4	; For compatibility
+.equ	PORTB5	= 5	; Port B Data Register bit 5
+.equ	PB5	= 5	; For compatibility
+.equ	PORTB6	= 6	; Port B Data Register bit 6
+.equ	PB6	= 6	; For compatibility
+.equ	PORTB7	= 7	; Port B Data Register bit 7
+.equ	PB7	= 7	; For compatibility
+
+; DDRB - Port B Data Direction Register
+.equ	DDB0	= 0	; Port B Data Direction Register bit 0
+.equ	DDB1	= 1	; Port B Data Direction Register bit 1
+.equ	DDB2	= 2	; Port B Data Direction Register bit 2
+.equ	DDB3	= 3	; Port B Data Direction Register bit 3
+.equ	DDB4	= 4	; Port B Data Direction Register bit 4
+.equ	DDB5	= 5	; Port B Data Direction Register bit 5
+.equ	DDB6	= 6	; Port B Data Direction Register bit 6
+.equ	DDB7	= 7	; Port B Data Direction Register bit 7
+
+; PINB - Port B Input Pins
+.equ	PINB0	= 0	; Port B Input Pins bit 0
+.equ	PINB1	= 1	; Port B Input Pins bit 1
+.equ	PINB2	= 2	; Port B Input Pins bit 2
+.equ	PINB3	= 3	; Port B Input Pins bit 3
+.equ	PINB4	= 4	; Port B Input Pins bit 4
+.equ	PINB5	= 5	; Port B Input Pins bit 5
+.equ	PINB6	= 6	; Port B Input Pins bit 6
+.equ	PINB7	= 7	; Port B Input Pins bit 7
+
+
+; ***** PORTC ************************
+; PORTC - Port C Data Register
+.equ	PORTC0	= 0	; Port C Data Register bit 0
+.equ	PC0	= 0	; For compatibility
+.equ	PORTC1	= 1	; Port C Data Register bit 1
+.equ	PC1	= 1	; For compatibility
+.equ	PORTC2	= 2	; Port C Data Register bit 2
+.equ	PC2	= 2	; For compatibility
+.equ	PORTC3	= 3	; Port C Data Register bit 3
+.equ	PC3	= 3	; For compatibility
+.equ	PORTC4	= 4	; Port C Data Register bit 4
+.equ	PC4	= 4	; For compatibility
+.equ	PORTC5	= 5	; Port C Data Register bit 5
+.equ	PC5	= 5	; For compatibility
+.equ	PORTC6	= 6	; Port C Data Register bit 6
+.equ	PC6	= 6	; For compatibility
+
+; DDRC - Port C Data Direction Register
+.equ	DDC0	= 0	; Port C Data Direction Register bit 0
+.equ	DDC1	= 1	; Port C Data Direction Register bit 1
+.equ	DDC2	= 2	; Port C Data Direction Register bit 2
+.equ	DDC3	= 3	; Port C Data Direction Register bit 3
+.equ	DDC4	= 4	; Port C Data Direction Register bit 4
+.equ	DDC5	= 5	; Port C Data Direction Register bit 5
+.equ	DDC6	= 6	; Port C Data Direction Register bit 6
+
+; PINC - Port C Input Pins
+.equ	PINC0	= 0	; Port C Input Pins bit 0
+.equ	PINC1	= 1	; Port C Input Pins bit 1
+.equ	PINC2	= 2	; Port C Input Pins bit 2
+.equ	PINC3	= 3	; Port C Input Pins bit 3
+.equ	PINC4	= 4	; Port C Input Pins bit 4
+.equ	PINC5	= 5	; Port C Input Pins bit 5
+.equ	PINC6	= 6	; Port C Input Pins bit 6
+
+
+; ***** PORTD ************************
+; PORTD - Port D Data Register
+.equ	PORTD0	= 0	; Port D Data Register bit 0
+.equ	PD0	= 0	; For compatibility
+.equ	PORTD1	= 1	; Port D Data Register bit 1
+.equ	PD1	= 1	; For compatibility
+.equ	PORTD2	= 2	; Port D Data Register bit 2
+.equ	PD2	= 2	; For compatibility
+.equ	PORTD3	= 3	; Port D Data Register bit 3
+.equ	PD3	= 3	; For compatibility
+.equ	PORTD4	= 4	; Port D Data Register bit 4
+.equ	PD4	= 4	; For compatibility
+.equ	PORTD5	= 5	; Port D Data Register bit 5
+.equ	PD5	= 5	; For compatibility
+.equ	PORTD6	= 6	; Port D Data Register bit 6
+.equ	PD6	= 6	; For compatibility
+.equ	PORTD7	= 7	; Port D Data Register bit 7
+.equ	PD7	= 7	; For compatibility
+
+; DDRD - Port D Data Direction Register
+.equ	DDD0	= 0	; Port D Data Direction Register bit 0
+.equ	DDD1	= 1	; Port D Data Direction Register bit 1
+.equ	DDD2	= 2	; Port D Data Direction Register bit 2
+.equ	DDD3	= 3	; Port D Data Direction Register bit 3
+.equ	DDD4	= 4	; Port D Data Direction Register bit 4
+.equ	DDD5	= 5	; Port D Data Direction Register bit 5
+.equ	DDD6	= 6	; Port D Data Direction Register bit 6
+.equ	DDD7	= 7	; Port D Data Direction Register bit 7
+
+; PIND - Port D Input Pins
+.equ	PIND0	= 0	; Port D Input Pins bit 0
+.equ	PIND1	= 1	; Port D Input Pins bit 1
+.equ	PIND2	= 2	; Port D Input Pins bit 2
+.equ	PIND3	= 3	; Port D Input Pins bit 3
+.equ	PIND4	= 4	; Port D Input Pins bit 4
+.equ	PIND5	= 5	; Port D Input Pins bit 5
+.equ	PIND6	= 6	; Port D Input Pins bit 6
+.equ	PIND7	= 7	; Port D Input Pins bit 7
+
+
+; ***** TIMER_COUNTER_0 **************
+; TIMSK0 - Timer/Counter0 Interrupt Mask Register
+.equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
+.equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
+.equ	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable
+
+; TIFR0 - Timer/Counter0 Interrupt Flag register
+.equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
+.equ	OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
+.equ	OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B
+
+; TCCR0A - Timer/Counter  Control Register A
+.equ	WGM00	= 0	; Waveform Generation Mode
+.equ	WGM01	= 1	; Waveform Generation Mode
+.equ	COM0B0	= 4	; Compare Output Mode, Fast PWm
+.equ	COM0B1	= 5	; Compare Output Mode, Fast PWm
+.equ	COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
+.equ	COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode
+
+; TCCR0B - Timer/Counter Control Register B
+.equ	CS00	= 0	; Clock Select
+.equ	CS01	= 1	; Clock Select
+.equ	CS02	= 2	; Clock Select
+.equ	WGM02	= 3	; 
+.equ	FOC0B	= 6	; Force Output Compare B
+.equ	FOC0A	= 7	; Force Output Compare A
+
+; TCNT0 - Timer/Counter0
+.equ	TCNT0_0	= 0	; 
+.equ	TCNT0_1	= 1	; 
+.equ	TCNT0_2	= 2	; 
+.equ	TCNT0_3	= 3	; 
+.equ	TCNT0_4	= 4	; 
+.equ	TCNT0_5	= 5	; 
+.equ	TCNT0_6	= 6	; 
+.equ	TCNT0_7	= 7	; 
+
+; OCR0A - Timer/Counter0 Output Compare Register
+.equ	OCR0A_0	= 0	; 
+.equ	OCR0A_1	= 1	; 
+.equ	OCR0A_2	= 2	; 
+.equ	OCR0A_3	= 3	; 
+.equ	OCR0A_4	= 4	; 
+.equ	OCR0A_5	= 5	; 
+.equ	OCR0A_6	= 6	; 
+.equ	OCR0A_7	= 7	; 
+
+; OCR0B - Timer/Counter0 Output Compare Register
+.equ	OCR0B_0	= 0	; 
+.equ	OCR0B_1	= 1	; 
+.equ	OCR0B_2	= 2	; 
+.equ	OCR0B_3	= 3	; 
+.equ	OCR0B_4	= 4	; 
+.equ	OCR0B_5	= 5	; 
+.equ	OCR0B_6	= 6	; 
+.equ	OCR0B_7	= 7	; 
+
+; GTCCR - General Timer/Counter Control Register
+;.equ	PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
+.equ	PSR10	= PSRSYNC	; For compatibility
+;.equ	TSM	= 7	; Timer/Counter Synchronization Mode
+
+
+; ***** EXTERNAL_INTERRUPT ***********
+; EICRA - External Interrupt Control Register
+.equ	ISC00	= 0	; External Interrupt Sense Control 0 Bit 0
+.equ	ISC01	= 1	; External Interrupt Sense Control 0 Bit 1
+.equ	ISC10	= 2	; External Interrupt Sense Control 1 Bit 0
+.equ	ISC11	= 3	; External Interrupt Sense Control 1 Bit 1
+
+; EIMSK - External Interrupt Mask Register
+.equ	INT0	= 0	; External Interrupt Request 0 Enable
+.equ	INT1	= 1	; External Interrupt Request 1 Enable
+
+; EIFR - External Interrupt Flag Register
+.equ	INTF0	= 0	; External Interrupt Flag 0
+.equ	INTF1	= 1	; External Interrupt Flag 1
+
+; PCICR - Pin Change Interrupt Control Register
+.equ	PCIE0	= 0	; Pin Change Interrupt Enable 0
+.equ	PCIE1	= 1	; Pin Change Interrupt Enable 1
+.equ	PCIE2	= 2	; Pin Change Interrupt Enable 2
+
+; PCMSK2 - Pin Change Mask Register 2
+.equ	PCINT16	= 0	; Pin Change Enable Mask 16
+.equ	PCINT17	= 1	; Pin Change Enable Mask 17
+.equ	PCINT18	= 2	; Pin Change Enable Mask 18
+.equ	PCINT19	= 3	; Pin Change Enable Mask 19
+.equ	PCINT20	= 4	; Pin Change Enable Mask 20
+.equ	PCINT21	= 5	; Pin Change Enable Mask 21
+.equ	PCINT22	= 6	; Pin Change Enable Mask 22
+.equ	PCINT23	= 7	; Pin Change Enable Mask 23
+
+; PCMSK1 - Pin Change Mask Register 1
+.equ	PCINT8	= 0	; Pin Change Enable Mask 8
+.equ	PCINT9	= 1	; Pin Change Enable Mask 9
+.equ	PCINT10	= 2	; Pin Change Enable Mask 10
+.equ	PCINT11	= 3	; Pin Change Enable Mask 11
+.equ	PCINT12	= 4	; Pin Change Enable Mask 12
+.equ	PCINT13	= 5	; Pin Change Enable Mask 13
+.equ	PCINT14	= 6	; Pin Change Enable Mask 14
+
+; PCMSK0 - Pin Change Mask Register 0
+.equ	PCINT0	= 0	; Pin Change Enable Mask 0
+.equ	PCINT1	= 1	; Pin Change Enable Mask 1
+.equ	PCINT2	= 2	; Pin Change Enable Mask 2
+.equ	PCINT3	= 3	; Pin Change Enable Mask 3
+.equ	PCINT4	= 4	; Pin Change Enable Mask 4
+.equ	PCINT5	= 5	; Pin Change Enable Mask 5
+.equ	PCINT6	= 6	; Pin Change Enable Mask 6
+.equ	PCINT7	= 7	; Pin Change Enable Mask 7
+
+; PCIFR - Pin Change Interrupt Flag Register
+.equ	PCIF0	= 0	; Pin Change Interrupt Flag 0
+.equ	PCIF1	= 1	; Pin Change Interrupt Flag 1
+.equ	PCIF2	= 2	; Pin Change Interrupt Flag 2
+
+
+; ***** SPI **************************
+; SPDR - SPI Data Register
+.equ	SPDR0	= 0	; SPI Data Register bit 0
+.equ	SPDR1	= 1	; SPI Data Register bit 1
+.equ	SPDR2	= 2	; SPI Data Register bit 2
+.equ	SPDR3	= 3	; SPI Data Register bit 3
+.equ	SPDR4	= 4	; SPI Data Register bit 4
+.equ	SPDR5	= 5	; SPI Data Register bit 5
+.equ	SPDR6	= 6	; SPI Data Register bit 6
+.equ	SPDR7	= 7	; SPI Data Register bit 7
+
+; SPSR - SPI Status Register
+.equ	SPI2X	= 0	; Double SPI Speed Bit
+.equ	WCOL	= 6	; Write Collision Flag
+.equ	SPIF	= 7	; SPI Interrupt Flag
+
+; SPCR - SPI Control Register
+.equ	SPR0	= 0	; SPI Clock Rate Select 0
+.equ	SPR1	= 1	; SPI Clock Rate Select 1
+.equ	CPHA	= 2	; Clock Phase
+.equ	CPOL	= 3	; Clock polarity
+.equ	MSTR	= 4	; Master/Slave Select
+.equ	DORD	= 5	; Data Order
+.equ	SPE	= 6	; SPI Enable
+.equ	SPIE	= 7	; SPI Interrupt Enable
+
+
+; ***** WATCHDOG *********************
+; WDTCSR - Watchdog Timer Control Register
+.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
+.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
+.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
+.equ	WDE	= 3	; Watch Dog Enable
+.equ	WDCE	= 4	; Watchdog Change Enable
+.equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
+.equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
+.equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag
+
+
+; ***** EEPROM ***********************
+; EEARL - EEPROM Address Register Low Byte
+.equ	EEAR0	= 0	; EEPROM Read/Write Access Bit 0
+.equ	EEAR1	= 1	; EEPROM Read/Write Access Bit 1
+.equ	EEAR2	= 2	; EEPROM Read/Write Access Bit 2
+.equ	EEAR3	= 3	; EEPROM Read/Write Access Bit 3
+.equ	EEAR4	= 4	; EEPROM Read/Write Access Bit 4
+.equ	EEAR5	= 5	; EEPROM Read/Write Access Bit 5
+.equ	EEAR6	= 6	; EEPROM Read/Write Access Bit 6
+.equ	EEAR7	= 7	; EEPROM Read/Write Access Bit 7
+
+; EEARH - EEPROM Address Register High Byte
+.equ	EEAR8	= 0	; EEPROM Read/Write Access Bit 0
+
+; EEDR - EEPROM Data Register
+.equ	EEDR0	= 0	; EEPROM Data Register bit 0
+.equ	EEDR1	= 1	; EEPROM Data Register bit 1
+.equ	EEDR2	= 2	; EEPROM Data Register bit 2
+.equ	EEDR3	= 3	; EEPROM Data Register bit 3
+.equ	EEDR4	= 4	; EEPROM Data Register bit 4
+.equ	EEDR5	= 5	; EEPROM Data Register bit 5
+.equ	EEDR6	= 6	; EEPROM Data Register bit 6
+.equ	EEDR7	= 7	; EEPROM Data Register bit 7
+
+; EECR - EEPROM Control Register
+.equ	EERE	= 0	; EEPROM Read Enable
+.equ	EEPE	= 1	; EEPROM Write Enable
+.equ	EEMPE	= 2	; EEPROM Master Write Enable
+.equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
+.equ	EEPM0	= 4	; EEPROM Programming Mode Bit 0
+.equ	EEPM1	= 5	; EEPROM Programming Mode Bit 1
+
+
+; ***** CPU **************************
+; SREG - Status Register
+.equ	SREG_C	= 0	; Carry Flag
+.equ	SREG_Z	= 1	; Zero Flag
+.equ	SREG_N	= 2	; Negative Flag
+.equ	SREG_V	= 3	; Two's Complement Overflow Flag
+.equ	SREG_S	= 4	; Sign Bit
+.equ	SREG_H	= 5	; Half Carry Flag
+.equ	SREG_T	= 6	; Bit Copy Storage
+.equ	SREG_I	= 7	; Global Interrupt Enable
+
+; OSCCAL - Oscillator Calibration Value
+.equ	CAL0	= 0	; Oscillator Calibration Value Bit0
+.equ	CAL1	= 1	; Oscillator Calibration Value Bit1
+.equ	CAL2	= 2	; Oscillator Calibration Value Bit2
+.equ	CAL3	= 3	; Oscillator Calibration Value Bit3
+.equ	CAL4	= 4	; Oscillator Calibration Value Bit4
+.equ	CAL5	= 5	; Oscillator Calibration Value Bit5
+.equ	CAL6	= 6	; Oscillator Calibration Value Bit6
+.equ	CAL7	= 7	; Oscillator Calibration Value Bit7
+
+; CLKPR - Clock Prescale Register
+.equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
+.equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
+.equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
+.equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
+.equ	CLKPCE	= 7	; Clock Prescaler Change Enable
+
+; SPMCSR - Store Program Memory Control and Status Register
+.equ	SELFPRGEN	= 0	; Self Programming Enable
+.equ	PGERS	= 1	; Page Erase
+.equ	PGWRT	= 2	; Page Write
+.equ	BLBSET	= 3	; Boot Lock Bit Set
+.equ	RWWSRE	= 4	; Read-While-Write section read enable
+.equ	RWWSB	= 6	; Read-While-Write Section Busy
+.equ	SPMIE	= 7	; SPM Interrupt Enable
+
+; MCUCR - MCU Control Register
+.equ	IVCE	= 0	; 
+.equ	IVSEL	= 1	; 
+.equ	PUD	= 4	; 
+.equ	BODSE	= 5	; BOD Sleep Enable
+.equ	BODS	= 6	; BOD Sleep
+
+; MCUSR - MCU Status Register
+.equ	PORF	= 0	; Power-on reset flag
+.equ	EXTRF	= 1	; External Reset Flag
+.equ	EXTREF	= EXTRF	; For compatibility
+.equ	BORF	= 2	; Brown-out Reset Flag
+.equ	WDRF	= 3	; Watchdog Reset Flag
+
+; SMCR - Sleep Mode Control Register
+.equ	SE	= 0	; Sleep Enable
+.equ	SM0	= 1	; Sleep Mode Select Bit 0
+.equ	SM1	= 2	; Sleep Mode Select Bit 1
+.equ	SM2	= 3	; Sleep Mode Select Bit 2
+
+; GPIOR2 - General Purpose I/O Register 2
+.equ	GPIOR20	= 0	; 
+.equ	GPIOR21	= 1	; 
+.equ	GPIOR22	= 2	; 
+.equ	GPIOR23	= 3	; 
+.equ	GPIOR24	= 4	; 
+.equ	GPIOR25	= 5	; 
+.equ	GPIOR26	= 6	; 
+.equ	GPIOR27	= 7	; 
+
+; GPIOR1 - General Purpose I/O Register 1
+.equ	GPIOR10	= 0	; 
+.equ	GPIOR11	= 1	; 
+.equ	GPIOR12	= 2	; 
+.equ	GPIOR13	= 3	; 
+.equ	GPIOR14	= 4	; 
+.equ	GPIOR15	= 5	; 
+.equ	GPIOR16	= 6	; 
+.equ	GPIOR17	= 7	; 
+
+; GPIOR0 - General Purpose I/O Register 0
+.equ	GPIOR00	= 0	; 
+.equ	GPIOR01	= 1	; 
+.equ	GPIOR02	= 2	; 
+.equ	GPIOR03	= 3	; 
+.equ	GPIOR04	= 4	; 
+.equ	GPIOR05	= 5	; 
+.equ	GPIOR06	= 6	; 
+.equ	GPIOR07	= 7	; 
+
+; PRR - Power Reduction Register
+.equ	PRADC	= 0	; Power Reduction ADC
+.equ	PRUSART0	= 1	; Power Reduction USART
+.equ	PRSPI	= 2	; Power Reduction Serial Peripheral Interface
+.equ	PRTIM1	= 3	; Power Reduction Timer/Counter1
+.equ	PRTIM0	= 5	; Power Reduction Timer/Counter0
+.equ	PRTIM2	= 6	; Power Reduction Timer/Counter2
+.equ	PRTWI	= 7	; Power Reduction TWI
+
+
+
+; ***** LOCKSBITS ********************************************************
+.equ	LB1	= 0	; Lock bit
+.equ	LB2	= 1	; Lock bit
+.equ	BLB01	= 2	; Boot Lock bit
+.equ	BLB02	= 3	; Boot Lock bit
+.equ	BLB11	= 4	; Boot lock bit
+.equ	BLB12	= 5	; Boot lock bit
+
+
+; ***** FUSES ************************************************************
+; LOW fuse bits
+.equ	CKSEL0	= 0	; Select Clock Source
+.equ	CKSEL1	= 1	; Select Clock Source
+.equ	CKSEL2	= 2	; Select Clock Source
+.equ	CKSEL3	= 3	; Select Clock Source
+.equ	SUT0	= 4	; Select start-up time
+.equ	SUT1	= 5	; Select start-up time
+.equ	CKOUT	= 6	; Clock output
+.equ	CKDIV8	= 7	; Divide clock by 8
+
+; HIGH fuse bits
+.equ	BODLEVEL0	= 0	; Brown-out Detector trigger level
+.equ	BODLEVEL1	= 1	; Brown-out Detector trigger level
+.equ	BODLEVEL2	= 2	; Brown-out Detector trigger level
+.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
+.equ	WDTON	= 4	; Watchdog Timer Always On
+.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
+.equ	DWEN	= 6	; debugWIRE Enable
+.equ	RSTDISBL	= 7	; External reset disable
+
+; EXTENDED fuse bits
+.equ	BOOTRST	= 0	; Select reset vector
+.equ	BOOTSZ0	= 1	; Select boot size
+.equ	BOOTSZ1	= 2	; Select boot size
+
+
+
+; ***** CPU REGISTER DEFINITIONS *****************************************
+.def	XH	= r27
+.def	XL	= r26
+.def	YH	= r29
+.def	YL	= r28
+.def	ZH	= r31
+.def	ZL	= r30
+
+
+
+; ***** DATA MEMORY DECLARATIONS *****************************************
+.equ	FLASHEND	= 0x0fff	; Note: Word address
+.equ	IOEND	= 0x00ff
+.equ	SRAM_START	= 0x0100
+.equ	SRAM_SIZE	= 1024
+.equ	RAMEND	= 0x04ff
+.equ	XRAMEND	= 0x0000
+.equ	E2END	= 0x01ff
+.equ	EEPROMEND	= 0x01ff
+.equ	EEADRBITS	= 9
+#pragma AVRPART MEMORY PROG_FLASH 8192
+#pragma AVRPART MEMORY EEPROM 512
+#pragma AVRPART MEMORY INT_SRAM SIZE 1024
+#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
+
+
+
+; ***** BOOTLOADER DECLARATIONS ******************************************
+.equ	NRWW_START_ADDR	= 0xc00
+.equ	NRWW_STOP_ADDR	= 0xfff
+.equ	RWW_START_ADDR	= 0x0
+.equ	RWW_STOP_ADDR	= 0xbff
+.equ	PAGESIZE	= 32
+.equ	FIRSTBOOTSTART	= 0xf80
+.equ	SECONDBOOTSTART	= 0xf00
+.equ	THIRDBOOTSTART	= 0xe00
+.equ	FOURTHBOOTSTART	= 0xc00
+.equ	SMALLBOOTSTART	= FIRSTBOOTSTART
+.equ	LARGEBOOTSTART	= FOURTHBOOTSTART
+
+
+
+; ***** INTERRUPT VECTORS ************************************************
+.equ	INT0addr	= 0x0001	; External Interrupt Request 0
+.equ	INT1addr	= 0x0002	; External Interrupt Request 1
+.equ	PCI0addr	= 0x0003	; Pin Change Interrupt Request 0
+.equ	PCI1addr	= 0x0004	; Pin Change Interrupt Request 0
+.equ	PCI2addr	= 0x0005	; Pin Change Interrupt Request 1
+.equ	WDTaddr	= 0x0006	; Watchdog Time-out Interrupt
+.equ	OC2Aaddr	= 0x0007	; Timer/Counter2 Compare Match A
+.equ	OC2Baddr	= 0x0008	; Timer/Counter2 Compare Match A
+.equ	OVF2addr	= 0x0009	; Timer/Counter2 Overflow
+.equ	ICP1addr	= 0x000a	; Timer/Counter1 Capture Event
+.equ	OC1Aaddr	= 0x000b	; Timer/Counter1 Compare Match A
+.equ	OC1Baddr	= 0x000c	; Timer/Counter1 Compare Match B
+.equ	OVF1addr	= 0x000d	; Timer/Counter1 Overflow
+.equ	OC0Aaddr	= 0x000e	; TimerCounter0 Compare Match A
+.equ	OC0Baddr	= 0x000f	; TimerCounter0 Compare Match B
+.equ	OVF0addr	= 0x0010	; Timer/Couner0 Overflow
+.equ	SPIaddr	= 0x0011	; SPI Serial Transfer Complete
+.equ	URXCaddr	= 0x0012	; USART Rx Complete
+.equ	UDREaddr	= 0x0013	; USART, Data Register Empty
+.equ	UTXCaddr	= 0x0014	; USART Tx Complete
+.equ	ADCCaddr	= 0x0015	; ADC Conversion Complete
+.equ	ERDYaddr	= 0x0016	; EEPROM Ready
+.equ	ACIaddr	= 0x0017	; Analog Comparator
+.equ	TWIaddr	= 0x0018	; Two-wire Serial Interface
+.equ	SPMRaddr	= 0x0019	; Store Program Memory Read
+
+.equ	INT_VECTORS_SIZE	= 26	; size in words
+
+#endif  /* _M88PDEF_INC_ */
+
+; ***** END OF FILE ******************************************************

Atmel/m8def.inc

@@ -0,0 +1,738 @@
+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
+;***** Created: 2005-01-11 10:31 ******* Source: ATmega8.xml *************
+;*************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number            : AVR000
+;* File Name         : "m8def.inc"
+;* Title             : Register/Bit Definitions for the ATmega8
+;* Date              : 2005-01-11
+;* Version           : 2.14
+;* Support E-mail    : avr@atmel.com
+;* Target MCU        : ATmega8
+;* 
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register 
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and 
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;* 
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in    r16,PORTB             ;read PORTB latch
+;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
+;* out   PORTB,r16             ;output to PORTB
+;* 
+;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
+;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
+;* rjmp  TOV0_is_set           ;jump if set
+;* ...                         ;otherwise do something else
+;*************************************************************************
+
+;.ifndef _M8DEF_INC_
+;.define _M8DEF_INC_
+
+
+;.pragma partinc 0
+
+; ***** SPECIFY DEVICE ***************************************************
+.device ATmega8
+;.pragma AVRPART ADMIN PART_NAME ATmega8
+.equ	SIGNATURE_000	= 0x1e
+.equ	SIGNATURE_001	= 0x93
+.equ	SIGNATURE_002	= 0x07
+
+;.pragma AVRPART CORE CORE_VERSION V2E
+
+
+; ***** I/O REGISTER DEFINITIONS *****************************************
+; NOTE:
+; Definitions marked "MEMORY MAPPED"are extended I/O ports
+; and cannot be used with IN/OUT instructions
+.equ	SREG	= 0x3f
+.equ	SPH	= 0x3e
+.equ	SPL	= 0x3d
+.equ	GICR	= 0x3b
+.equ	GIFR	= 0x3a
+.equ	TIMSK	= 0x39
+.equ	TIFR	= 0x38
+.equ	SPMCR	= 0x37
+.equ	TWCR	= 0x36
+.equ	MCUCR	= 0x35
+.equ	MCUCSR	= 0x34
+.equ	TCCR0	= 0x33
+.equ	TCNT0	= 0x32
+.equ	OSCCAL	= 0x31
+.equ	SFIOR	= 0x30
+.equ	TCCR1A	= 0x2f
+.equ	TCCR1B	= 0x2e
+.equ	TCNT1H	= 0x2d
+.equ	TCNT1L	= 0x2c
+.equ	OCR1AH	= 0x2b
+.equ	OCR1AL	= 0x2a
+.equ	OCR1BH	= 0x29
+.equ	OCR1BL	= 0x28
+.equ	ICR1H	= 0x27
+.equ	ICR1L	= 0x26
+.equ	TCCR2	= 0x25
+.equ	TCNT2	= 0x24
+.equ	OCR2	= 0x23
+.equ	ASSR	= 0x22
+.equ	WDTCR	= 0x21
+.equ	UBRRH	= 0x20
+.equ	UCSRC	= 0x20
+.equ	EEARH	= 0x1f
+.equ	EEARL	= 0x1e
+.equ	EEDR	= 0x1d
+.equ	EECR	= 0x1c
+.equ	PORTB	= 0x18
+.equ	DDRB	= 0x17
+.equ	PINB	= 0x16
+.equ	PORTC	= 0x15
+.equ	DDRC	= 0x14
+.equ	PINC	= 0x13
+.equ	PORTD	= 0x12
+.equ	DDRD	= 0x11
+.equ	PIND	= 0x10
+.equ	SPDR	= 0x0f
+.equ	SPSR	= 0x0e
+.equ	SPCR	= 0x0d
+.equ	UDR	= 0x0c
+.equ	UCSRA	= 0x0b
+.equ	UCSRB	= 0x0a
+.equ	UBRRL	= 0x09
+.equ	ACSR	= 0x08
+.equ	ADMUX	= 0x07
+.equ	ADCSRA	= 0x06
+.equ	ADCH	= 0x05
+.equ	ADCL	= 0x04
+.equ	TWDR	= 0x03
+.equ	TWAR	= 0x02
+.equ	TWSR	= 0x01
+.equ	TWBR	= 0x00
+
+
+; ***** BIT DEFINITIONS **************************************************
+
+; ***** ANALOG_COMPARATOR ************
+; SFIOR - Special Function IO Register
+.equ	ACME	= 3	; Analog Comparator Multiplexer Enable
+
+; ACSR - Analog Comparator Control And Status Register
+.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
+.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
+.equ	ACIC	= 2	; Analog Comparator Input Capture Enable
+.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
+.equ	ACI	= 4	; Analog Comparator Interrupt Flag
+.equ	ACO	= 5	; Analog Compare Output
+.equ	ACBG	= 6	; Analog Comparator Bandgap Select
+.equ	ACD	= 7	; Analog Comparator Disable
+
+
+; ***** SPI **************************
+; SPDR - SPI Data Register
+.equ	SPDR0	= 0	; SPI Data Register bit 0
+.equ	SPDR1	= 1	; SPI Data Register bit 1
+.equ	SPDR2	= 2	; SPI Data Register bit 2
+.equ	SPDR3	= 3	; SPI Data Register bit 3
+.equ	SPDR4	= 4	; SPI Data Register bit 4
+.equ	SPDR5	= 5	; SPI Data Register bit 5
+.equ	SPDR6	= 6	; SPI Data Register bit 6
+.equ	SPDR7	= 7	; SPI Data Register bit 7
+
+; SPSR - SPI Status Register
+.equ	SPI2X	= 0	; Double SPI Speed Bit
+.equ	WCOL	= 6	; Write Collision Flag
+.equ	SPIF	= 7	; SPI Interrupt Flag
+
+; SPCR - SPI Control Register
+.equ	SPR0	= 0	; SPI Clock Rate Select 0
+.equ	SPR1	= 1	; SPI Clock Rate Select 1
+.equ	CPHA	= 2	; Clock Phase
+.equ	CPOL	= 3	; Clock polarity
+.equ	MSTR	= 4	; Master/Slave Select
+.equ	DORD	= 5	; Data Order
+.equ	SPE	= 6	; SPI Enable
+.equ	SPIE	= 7	; SPI Interrupt Enable
+
+
+; ***** EXTERNAL_INTERRUPT ***********
+; GICR - General Interrupt Control Register
+.equ	GIMSK	= GICR	; For compatibility
+.equ	IVCE	= 0	; Interrupt Vector Change Enable
+.equ	IVSEL	= 1	; Interrupt Vector Select
+.equ	INT0	= 6	; External Interrupt Request 0 Enable
+.equ	INT1	= 7	; External Interrupt Request 1 Enable
+
+; GIFR - General Interrupt Flag Register
+.equ	INTF0	= 6	; External Interrupt Flag 0
+.equ	INTF1	= 7	; External Interrupt Flag 1
+
+; MCUCR - MCU Control Register
+.equ	ISC00	= 0	; Interrupt Sense Control 0 Bit 0
+.equ	ISC01	= 1	; Interrupt Sense Control 0 Bit 1
+.equ	ISC10	= 2	; Interrupt Sense Control 1 Bit 0
+.equ	ISC11	= 3	; Interrupt Sense Control 1 Bit 1
+
+
+; ***** TIMER_COUNTER_0 **************
+; TIMSK - Timer/Counter Interrupt Mask Register
+.equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
+
+; TIFR - Timer/Counter Interrupt Flag register
+.equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
+
+; TCCR0 - Timer/Counter0 Control Register
+.equ	CS00	= 0	; Clock Select0 bit 0
+.equ	CS01	= 1	; Clock Select0 bit 1
+.equ	CS02	= 2	; Clock Select0 bit 2
+
+; TCNT0 - Timer Counter 0
+.equ	TCNT00	= 0	; Timer Counter 0 bit 0
+.equ	TCNT01	= 1	; Timer Counter 0 bit 1
+.equ	TCNT02	= 2	; Timer Counter 0 bit 2
+.equ	TCNT03	= 3	; Timer Counter 0 bit 3
+.equ	TCNT04	= 4	; Timer Counter 0 bit 4
+.equ	TCNT05	= 5	; Timer Counter 0 bit 5
+.equ	TCNT06	= 6	; Timer Counter 0 bit 6
+.equ	TCNT07	= 7	; Timer Counter 0 bit 7
+
+
+; ***** TIMER_COUNTER_1 **************
+; TIMSK - Timer/Counter Interrupt Mask Register
+.equ	TOIE1	= 2	; Timer/Counter1 Overflow Interrupt Enable
+.equ	OCIE1B	= 3	; Timer/Counter1 Output CompareB Match Interrupt Enable
+.equ	OCIE1A	= 4	; Timer/Counter1 Output CompareA Match Interrupt Enable
+.equ	TICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
+
+; TIFR - Timer/Counter Interrupt Flag register
+.equ	TOV1	= 2	; Timer/Counter1 Overflow Flag
+.equ	OCF1B	= 3	; Output Compare Flag 1B
+.equ	OCF1A	= 4	; Output Compare Flag 1A
+.equ	ICF1	= 5	; Input Capture Flag 1
+
+; TCCR1A - Timer/Counter1 Control Register A
+.equ	WGM10	= 0	; Waveform Generation Mode
+.equ	PWM10	= WGM10	; For compatibility
+.equ	WGM11	= 1	; Waveform Generation Mode
+.equ	PWM11	= WGM11	; For compatibility
+.equ	FOC1B	= 2	; Force Output Compare 1B
+.equ	FOC1A	= 3	; Force Output Compare 1A
+.equ	COM1B0	= 4	; Compare Output Mode 1B, bit 0
+.equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
+.equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
+.equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
+
+; TCCR1B - Timer/Counter1 Control Register B
+.equ	CS10	= 0	; Prescaler source of Timer/Counter 1
+.equ	CS11	= 1	; Prescaler source of Timer/Counter 1
+.equ	CS12	= 2	; Prescaler source of Timer/Counter 1
+.equ	WGM12	= 3	; Waveform Generation Mode
+.equ	CTC10	= WGM12	; For compatibility
+.equ	CTC1	= WGM12	; For compatibility
+.equ	WGM13	= 4	; Waveform Generation Mode
+.equ	CTC11	= WGM13	; For compatibility
+.equ	ICES1	= 6	; Input Capture 1 Edge Select
+.equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
+
+
+; ***** TIMER_COUNTER_2 **************
+; TIMSK - Timer/Counter Interrupt Mask register
+.equ	TOIE2	= 6	; Timer/Counter2 Overflow Interrupt Enable
+.equ	OCIE2	= 7	; Timer/Counter2 Output Compare Match Interrupt Enable
+
+; TIFR - Timer/Counter Interrupt Flag Register
+.equ	TOV2	= 6	; Timer/Counter2 Overflow Flag
+.equ	OCF2	= 7	; Output Compare Flag 2
+
+; TCCR2 - Timer/Counter2 Control Register
+.equ	CS20	= 0	; Clock Select bit 0
+.equ	CS21	= 1	; Clock Select bit 1
+.equ	CS22	= 2	; Clock Select bit 2
+.equ	WGM21	= 3	; Waveform Generation Mode
+.equ	CTC2	= WGM21	; For compatibility
+.equ	COM20	= 4	; Compare Output Mode bit 0
+.equ	COM21	= 5	; Compare Output Mode bit 1
+.equ	WGM20	= 6	; Waveform Genration Mode
+.equ	PWM2	= WGM20	; For compatibility
+.equ	FOC2	= 7	; Force Output Compare
+
+; TCNT2 - Timer/Counter2
+.equ	TCNT2_0	= 0	; Timer/Counter 2 bit 0
+.equ	TCNT2_1	= 1	; Timer/Counter 2 bit 1
+.equ	TCNT2_2	= 2	; Timer/Counter 2 bit 2
+.equ	TCNT2_3	= 3	; Timer/Counter 2 bit 3
+.equ	TCNT2_4	= 4	; Timer/Counter 2 bit 4
+.equ	TCNT2_5	= 5	; Timer/Counter 2 bit 5
+.equ	TCNT2_6	= 6	; Timer/Counter 2 bit 6
+.equ	TCNT2_7	= 7	; Timer/Counter 2 bit 7
+
+; OCR2 - Timer/Counter2 Output Compare Register
+.equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
+.equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
+.equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
+.equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
+.equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
+.equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
+.equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
+.equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7
+
+; ASSR - Asynchronous Status Register
+.equ	TCR2UB	= 0	; Timer/counter Control Register2 Update Busy
+.equ	OCR2UB	= 1	; Output Compare Register2 Update Busy
+.equ	TCN2UB	= 2	; Timer/Counter2 Update Busy
+.equ	AS2	= 3	; Asynchronous Timer/counter2
+
+; SFIOR - Special Function IO Register
+.equ	PSR2	= 1	; Prescaler Reset Timer/Counter2
+
+
+; ***** USART ************************
+; UDR - USART I/O Data Register
+.equ	UDR0	= 0	; USART I/O Data Register bit 0
+.equ	UDR1	= 1	; USART I/O Data Register bit 1
+.equ	UDR2	= 2	; USART I/O Data Register bit 2
+.equ	UDR3	= 3	; USART I/O Data Register bit 3
+.equ	UDR4	= 4	; USART I/O Data Register bit 4
+.equ	UDR5	= 5	; USART I/O Data Register bit 5
+.equ	UDR6	= 6	; USART I/O Data Register bit 6
+.equ	UDR7	= 7	; USART I/O Data Register bit 7
+
+; UCSRA - USART Control and Status Register A
+.equ	USR	= UCSRA	; For compatibility
+.equ	MPCM	= 0	; Multi-processor Communication Mode
+.equ	U2X	= 1	; Double the USART transmission speed
+.equ	UPE	= 2	; Parity Error
+.equ	PE	= UPE	; For compatibility
+.equ	DOR	= 3	; Data overRun
+.equ	FE	= 4	; Framing Error
+.equ	UDRE	= 5	; USART Data Register Empty
+.equ	TXC	= 6	; USART Transmitt Complete
+.equ	RXC	= 7	; USART Receive Complete
+
+; UCSRB - USART Control and Status Register B
+.equ	UCR	= UCSRB	; For compatibility
+.equ	TXB8	= 0	; Transmit Data Bit 8
+.equ	RXB8	= 1	; Receive Data Bit 8
+.equ	UCSZ2	= 2	; Character Size
+.equ	CHR9	= UCSZ2	; For compatibility
+.equ	TXEN	= 3	; Transmitter Enable
+.equ	RXEN	= 4	; Receiver Enable
+.equ	UDRIE	= 5	; USART Data register Empty Interrupt Enable
+.equ	TXCIE	= 6	; TX Complete Interrupt Enable
+.equ	RXCIE	= 7	; RX Complete Interrupt Enable
+
+; UCSRC - USART Control and Status Register C
+.equ	UCPOL	= 0	; Clock Polarity
+.equ	UCSZ0	= 1	; Character Size
+.equ	UCSZ1	= 2	; Character Size
+.equ	USBS	= 3	; Stop Bit Select
+.equ	UPM0	= 4	; Parity Mode Bit 0
+.equ	UPM1	= 5	; Parity Mode Bit 1
+.equ	UMSEL	= 6	; USART Mode Select
+.equ	URSEL	= 7	; Register Select
+
+.equ	UBRRHI	= UBRRH	; For compatibility
+
+; ***** TWI **************************
+; TWBR - TWI Bit Rate register
+.equ	I2BR	= TWBR	; For compatibility
+.equ	TWBR0	= 0	; 
+.equ	TWBR1	= 1	; 
+.equ	TWBR2	= 2	; 
+.equ	TWBR3	= 3	; 
+.equ	TWBR4	= 4	; 
+.equ	TWBR5	= 5	; 
+.equ	TWBR6	= 6	; 
+.equ	TWBR7	= 7	; 
+
+; TWCR - TWI Control Register
+.equ	I2CR	= TWCR	; For compatibility
+.equ	TWIE	= 0	; TWI Interrupt Enable
+.equ	I2IE	= TWIE	; For compatibility
+.equ	TWEN	= 2	; TWI Enable Bit
+.equ	I2EN	= TWEN	; For compatibility
+.equ	ENI2C	= TWEN	; For compatibility
+.equ	TWWC	= 3	; TWI Write Collition Flag
+.equ	I2WC	= TWWC	; For compatibility
+.equ	TWSTO	= 4	; TWI Stop Condition Bit
+.equ	I2STO	= TWSTO	; For compatibility
+.equ	TWSTA	= 5	; TWI Start Condition Bit
+.equ	I2STA	= TWSTA	; For compatibility
+.equ	TWEA	= 6	; TWI Enable Acknowledge Bit
+.equ	I2EA	= TWEA	; For compatibility
+.equ	TWINT	= 7	; TWI Interrupt Flag
+.equ	I2INT	= TWINT	; For compatibility
+
+; TWSR - TWI Status Register
+.equ	I2SR	= TWSR	; For compatibility
+.equ	TWPS0	= 0	; TWI Prescaler
+.equ	TWS0	= TWPS0	; For compatibility
+.equ	I2GCE	= TWPS0	; For compatibility
+.equ	TWPS1	= 1	; TWI Prescaler
+.equ	TWS1	= TWPS1	; For compatibility
+.equ	TWS3	= 3	; TWI Status
+.equ	I2S3	= TWS3	; For compatibility
+.equ	TWS4	= 4	; TWI Status
+.equ	I2S4	= TWS4	; For compatibility
+.equ	TWS5	= 5	; TWI Status
+.equ	I2S5	= TWS5	; For compatibility
+.equ	TWS6	= 6	; TWI Status
+.equ	I2S6	= TWS6	; For compatibility
+.equ	TWS7	= 7	; TWI Status
+.equ	I2S7	= TWS7	; For compatibility
+
+; TWDR - TWI Data register
+.equ	I2DR	= TWDR	; For compatibility
+.equ	TWD0	= 0	; TWI Data Register Bit 0
+.equ	TWD1	= 1	; TWI Data Register Bit 1
+.equ	TWD2	= 2	; TWI Data Register Bit 2
+.equ	TWD3	= 3	; TWI Data Register Bit 3
+.equ	TWD4	= 4	; TWI Data Register Bit 4
+.equ	TWD5	= 5	; TWI Data Register Bit 5
+.equ	TWD6	= 6	; TWI Data Register Bit 6
+.equ	TWD7	= 7	; TWI Data Register Bit 7
+
+; TWAR - TWI (Slave) Address register
+.equ	I2AR	= TWAR	; For compatibility
+.equ	TWGCE	= 0	; TWI General Call Recognition Enable Bit
+.equ	TWA0	= 1	; TWI (Slave) Address register Bit 0
+.equ	TWA1	= 2	; TWI (Slave) Address register Bit 1
+.equ	TWA2	= 3	; TWI (Slave) Address register Bit 2
+.equ	TWA3	= 4	; TWI (Slave) Address register Bit 3
+.equ	TWA4	= 5	; TWI (Slave) Address register Bit 4
+.equ	TWA5	= 6	; TWI (Slave) Address register Bit 5
+.equ	TWA6	= 7	; TWI (Slave) Address register Bit 6
+
+
+; ***** WATCHDOG *********************
+; WDTCR - Watchdog Timer Control Register
+.equ	WDTCSR	= WDTCR	; For compatibility
+.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
+.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
+.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
+.equ	WDE	= 3	; Watch Dog Enable
+.equ	WDCE	= 4	; Watchdog Change Enable
+.equ	WDTOE	= WDCE	; For compatibility
+
+
+; ***** PORTB ************************
+; PORTB - Port B Data Register
+.equ	PORTB0	= 0	; Port B Data Register bit 0
+.equ	PB0	= 0	; For compatibility
+.equ	PORTB1	= 1	; Port B Data Register bit 1
+.equ	PB1	= 1	; For compatibility
+.equ	PORTB2	= 2	; Port B Data Register bit 2
+.equ	PB2	= 2	; For compatibility
+.equ	PORTB3	= 3	; Port B Data Register bit 3
+.equ	PB3	= 3	; For compatibility
+.equ	PORTB4	= 4	; Port B Data Register bit 4
+.equ	PB4	= 4	; For compatibility
+.equ	PORTB5	= 5	; Port B Data Register bit 5
+.equ	PB5	= 5	; For compatibility
+.equ	PORTB6	= 6	; Port B Data Register bit 6
+.equ	PB6	= 6	; For compatibility
+.equ	PORTB7	= 7	; Port B Data Register bit 7
+.equ	PB7	= 7	; For compatibility
+
+; DDRB - Port B Data Direction Register
+.equ	DDB0	= 0	; Port B Data Direction Register bit 0
+.equ	DDB1	= 1	; Port B Data Direction Register bit 1
+.equ	DDB2	= 2	; Port B Data Direction Register bit 2
+.equ	DDB3	= 3	; Port B Data Direction Register bit 3
+.equ	DDB4	= 4	; Port B Data Direction Register bit 4
+.equ	DDB5	= 5	; Port B Data Direction Register bit 5
+.equ	DDB6	= 6	; Port B Data Direction Register bit 6
+.equ	DDB7	= 7	; Port B Data Direction Register bit 7
+
+; PINB - Port B Input Pins
+.equ	PINB0	= 0	; Port B Input Pins bit 0
+.equ	PINB1	= 1	; Port B Input Pins bit 1
+.equ	PINB2	= 2	; Port B Input Pins bit 2
+.equ	PINB3	= 3	; Port B Input Pins bit 3
+.equ	PINB4	= 4	; Port B Input Pins bit 4
+.equ	PINB5	= 5	; Port B Input Pins bit 5
+.equ	PINB6	= 6	; Port B Input Pins bit 6
+.equ	PINB7	= 7	; Port B Input Pins bit 7
+
+
+; ***** PORTC ************************
+; PORTC - Port C Data Register
+.equ	PORTC0	= 0	; Port C Data Register bit 0
+.equ	PC0	= 0	; For compatibility
+.equ	PORTC1	= 1	; Port C Data Register bit 1
+.equ	PC1	= 1	; For compatibility
+.equ	PORTC2	= 2	; Port C Data Register bit 2
+.equ	PC2	= 2	; For compatibility
+.equ	PORTC3	= 3	; Port C Data Register bit 3
+.equ	PC3	= 3	; For compatibility
+.equ	PORTC4	= 4	; Port C Data Register bit 4
+.equ	PC4	= 4	; For compatibility
+.equ	PORTC5	= 5	; Port C Data Register bit 5
+.equ	PC5	= 5	; For compatibility
+.equ	PORTC6	= 6	; Port C Data Register bit 6
+.equ	PC6	= 6	; For compatibility
+
+; DDRC - Port C Data Direction Register
+.equ	DDC0	= 0	; Port C Data Direction Register bit 0
+.equ	DDC1	= 1	; Port C Data Direction Register bit 1
+.equ	DDC2	= 2	; Port C Data Direction Register bit 2
+.equ	DDC3	= 3	; Port C Data Direction Register bit 3
+.equ	DDC4	= 4	; Port C Data Direction Register bit 4
+.equ	DDC5	= 5	; Port C Data Direction Register bit 5
+.equ	DDC6	= 6	; Port C Data Direction Register bit 6
+
+; PINC - Port C Input Pins
+.equ	PINC0	= 0	; Port C Input Pins bit 0
+.equ	PINC1	= 1	; Port C Input Pins bit 1
+.equ	PINC2	= 2	; Port C Input Pins bit 2
+.equ	PINC3	= 3	; Port C Input Pins bit 3
+.equ	PINC4	= 4	; Port C Input Pins bit 4
+.equ	PINC5	= 5	; Port C Input Pins bit 5
+.equ	PINC6	= 6	; Port C Input Pins bit 6
+
+
+; ***** PORTD ************************
+; PORTD - Port D Data Register
+.equ	PORTD0	= 0	; Port D Data Register bit 0
+.equ	PD0	= 0	; For compatibility
+.equ	PORTD1	= 1	; Port D Data Register bit 1
+.equ	PD1	= 1	; For compatibility
+.equ	PORTD2	= 2	; Port D Data Register bit 2
+.equ	PD2	= 2	; For compatibility
+.equ	PORTD3	= 3	; Port D Data Register bit 3
+.equ	PD3	= 3	; For compatibility
+.equ	PORTD4	= 4	; Port D Data Register bit 4
+.equ	PD4	= 4	; For compatibility
+.equ	PORTD5	= 5	; Port D Data Register bit 5
+.equ	PD5	= 5	; For compatibility
+.equ	PORTD6	= 6	; Port D Data Register bit 6
+.equ	PD6	= 6	; For compatibility
+.equ	PORTD7	= 7	; Port D Data Register bit 7
+.equ	PD7	= 7	; For compatibility
+
+; DDRD - Port D Data Direction Register
+.equ	DDD0	= 0	; Port D Data Direction Register bit 0
+.equ	DDD1	= 1	; Port D Data Direction Register bit 1
+.equ	DDD2	= 2	; Port D Data Direction Register bit 2
+.equ	DDD3	= 3	; Port D Data Direction Register bit 3
+.equ	DDD4	= 4	; Port D Data Direction Register bit 4
+.equ	DDD5	= 5	; Port D Data Direction Register bit 5
+.equ	DDD6	= 6	; Port D Data Direction Register bit 6
+.equ	DDD7	= 7	; Port D Data Direction Register bit 7
+
+; PIND - Port D Input Pins
+.equ	PIND0	= 0	; Port D Input Pins bit 0
+.equ	PIND1	= 1	; Port D Input Pins bit 1
+.equ	PIND2	= 2	; Port D Input Pins bit 2
+.equ	PIND3	= 3	; Port D Input Pins bit 3
+.equ	PIND4	= 4	; Port D Input Pins bit 4
+.equ	PIND5	= 5	; Port D Input Pins bit 5
+.equ	PIND6	= 6	; Port D Input Pins bit 6
+.equ	PIND7	= 7	; Port D Input Pins bit 7
+
+
+; ***** EEPROM ***********************
+; EEDR - EEPROM Data Register
+.equ	EEDR0	= 0	; EEPROM Data Register bit 0
+.equ	EEDR1	= 1	; EEPROM Data Register bit 1
+.equ	EEDR2	= 2	; EEPROM Data Register bit 2
+.equ	EEDR3	= 3	; EEPROM Data Register bit 3
+.equ	EEDR4	= 4	; EEPROM Data Register bit 4
+.equ	EEDR5	= 5	; EEPROM Data Register bit 5
+.equ	EEDR6	= 6	; EEPROM Data Register bit 6
+.equ	EEDR7	= 7	; EEPROM Data Register bit 7
+
+; EECR - EEPROM Control Register
+.equ	EERE	= 0	; EEPROM Read Enable
+.equ	EEWE	= 1	; EEPROM Write Enable
+.equ	EEMWE	= 2	; EEPROM Master Write Enable
+.equ	EEWEE	= EEMWE	; For compatibility
+.equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
+
+
+; ***** CPU **************************
+; SREG - Status Register
+.equ	SREG_C	= 0	; Carry Flag
+.equ	SREG_Z	= 1	; Zero Flag
+.equ	SREG_N	= 2	; Negative Flag
+.equ	SREG_V	= 3	; Two's Complement Overflow Flag
+.equ	SREG_S	= 4	; Sign Bit
+.equ	SREG_H	= 5	; Half Carry Flag
+.equ	SREG_T	= 6	; Bit Copy Storage
+.equ	SREG_I	= 7	; Global Interrupt Enable
+
+; MCUCR - MCU Control Register
+;.equ	ISC00	= 0	; Interrupt Sense Control 0 Bit 0
+;.equ	ISC01	= 1	; Interrupt Sense Control 0 Bit 1
+;.equ	ISC10	= 2	; Interrupt Sense Control 1 Bit 0
+;.equ	ISC11	= 3	; Interrupt Sense Control 1 Bit 1
+.equ	SM0	= 4	; Sleep Mode Select
+.equ	SM1	= 5	; Sleep Mode Select
+.equ	SM2	= 6	; Sleep Mode Select
+.equ	SE	= 7	; Sleep Enable
+
+; MCUCSR - MCU Control And Status Register
+.equ	MCUSR	= MCUCSR	; For compatibility
+.equ	PORF	= 0	; Power-on reset flag
+.equ	EXTRF	= 1	; External Reset Flag
+.equ	BORF	= 2	; Brown-out Reset Flag
+.equ	WDRF	= 3	; Watchdog Reset Flag
+
+; OSCCAL - Oscillator Calibration Value
+.equ	CAL0	= 0	; Oscillator Calibration Value Bit0
+.equ	CAL1	= 1	; Oscillator Calibration Value Bit1
+.equ	CAL2	= 2	; Oscillator Calibration Value Bit2
+.equ	CAL3	= 3	; Oscillator Calibration Value Bit3
+.equ	CAL4	= 4	; Oscillator Calibration Value Bit4
+.equ	CAL5	= 5	; Oscillator Calibration Value Bit5
+.equ	CAL6	= 6	; Oscillator Calibration Value Bit6
+.equ	CAL7	= 7	; Oscillator Calibration Value Bit7
+
+; SPMCR - Store Program Memory Control Register
+.equ	SPMEN	= 0	; Store Program Memory Enable
+.equ	PGERS	= 1	; Page Erase
+.equ	PGWRT	= 2	; Page Write
+.equ	BLBSET	= 3	; Boot Lock Bit Set
+.equ	RWWSRE	= 4	; Read-While-Write Section Read Enable
+.equ	RWWSB	= 6	; Read-While-Write Section Busy
+.equ	SPMIE	= 7	; SPM Interrupt Enable
+
+; SFIOR - Special Function IO Register
+.equ	PSR10	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
+.equ	PUD	= 2	; Pull-up Disable
+.equ	ADHSM	= 4	; ADC High Speed Mode
+
+
+; ***** AD_CONVERTER *****************
+; ADMUX - The ADC multiplexer Selection Register
+.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
+.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
+.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
+.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
+.equ	ADLAR	= 5	; Left Adjust Result
+.equ	REFS0	= 6	; Reference Selection Bit 0
+.equ	REFS1	= 7	; Reference Selection Bit 1
+
+; ADCSRA - The ADC Control and Status register
+.equ	ADCSR	= ADCSRA	; For compatibility
+.equ	ADPS0	= 0	; ADC  Prescaler Select Bits
+.equ	ADPS1	= 1	; ADC  Prescaler Select Bits
+.equ	ADPS2	= 2	; ADC  Prescaler Select Bits
+.equ	ADIE	= 3	; ADC Interrupt Enable
+.equ	ADIF	= 4	; ADC Interrupt Flag
+.equ	ADFR	= 5	; ADC  Free Running Select
+.equ	ADSC	= 6	; ADC Start Conversion
+.equ	ADEN	= 7	; ADC Enable
+
+
+
+; ***** LOCKSBITS ********************************************************
+.equ	LB1	= 0	; Lock bit
+.equ	LB2	= 1	; Lock bit
+.equ	BLB01	= 2	; Boot Lock bit
+.equ	BLB02	= 3	; Boot Lock bit
+.equ	BLB11	= 4	; Boot lock bit
+.equ	BLB12	= 5	; Boot lock bit
+
+
+; ***** FUSES ************************************************************
+; LOW fuse bits
+.equ	CKSEL0	= 0	; Select Clock Source
+.equ	CKSEL1	= 1	; Select Clock Source
+.equ	CKSEL2	= 2	; Select Clock Source
+.equ	CKSEL3	= 3	; Select Clock Source
+.equ	SUT0	= 4	; Select start-up time
+.equ	SUT1	= 5	; Select start-up time
+.equ	BODEN	= 6	; Brown out detector enable
+.equ	BODLEVEL	= 7	; Brown out detector trigger level
+
+; HIGH fuse bits
+.equ	BOOTRST	= 0	; Select Reset Vector
+.equ	BOOTSZ0	= 1	; Select Boot Size
+.equ	BOOTSZ1	= 2	; Select Boot Size
+.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
+.equ	CKOPT	= 4	; Oscillator Options
+.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
+.equ	WTDON	= 6	; Enable watchdog
+.equ	RSTDISBL	= 7	; Disable reset
+
+
+
+; ***** CPU REGISTER DEFINITIONS *****************************************
+.def	XH	= r27
+.def	XL	= r26
+.def	YH	= r29
+.def	YL	= r28
+.def	ZH	= r31
+.def	ZL	= r30
+
+
+
+; ***** DATA MEMORY DECLARATIONS *****************************************
+.equ	FLASHEND	= 0x0fff	; Note: Word address
+.equ	IOEND	= 0x003f
+.equ	SRAM_START	= 0x0060
+.equ	SRAM_SIZE	= 1024
+.equ	RAMEND	= 0x045f
+.equ	XRAMEND	= 0x0000
+.equ	E2END	= 0x01ff
+.equ	EEPROMEND	= 0x01ff
+.equ	EEADRBITS	= 9
+;.pragma AVRPART MEMORY PROG_FLASH 8192
+;.pragma AVRPART MEMORY EEPROM 512
+;.pragma AVRPART MEMORY INT_SRAM SIZE 1024
+;.pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
+
+
+
+; ***** BOOTLOADER DECLARATIONS ******************************************
+.equ	NRWW_START_ADDR	= 0xc00
+.equ	NRWW_STOP_ADDR	= 0xfff
+.equ	RWW_START_ADDR	= 0x0
+.equ	RWW_STOP_ADDR	= 0xbff
+.equ	PAGESIZE	= 32
+.equ	FIRSTBOOTSTART	= 0xf80
+.equ	SECONDBOOTSTART	= 0xf00
+.equ	THIRDBOOTSTART	= 0xe00
+.equ	FOURTHBOOTSTART	= 0xc00
+.equ	SMALLBOOTSTART	= FIRSTBOOTSTART
+.equ	LARGEBOOTSTART	= FOURTHBOOTSTART
+
+
+
+; ***** INTERRUPT VECTORS ************************************************
+.equ	INT0addr	= 0x0001	; External Interrupt Request 0
+.equ	INT1addr	= 0x0002	; External Interrupt Request 1
+.equ	OC2addr	= 0x0003	; Timer/Counter2 Compare Match
+.equ	OVF2addr	= 0x0004	; Timer/Counter2 Overflow
+.equ	ICP1addr	= 0x0005	; Timer/Counter1 Capture Event
+.equ	OC1Aaddr	= 0x0006	; Timer/Counter1 Compare Match A
+.equ	OC1Baddr	= 0x0007	; Timer/Counter1 Compare Match B
+.equ	OVF1addr	= 0x0008	; Timer/Counter1 Overflow
+.equ	OVF0addr	= 0x0009	; Timer/Counter0 Overflow
+.equ	SPIaddr	= 0x000a	; Serial Transfer Complete
+.equ	URXCaddr	= 0x000b	; USART, Rx Complete
+.equ	UDREaddr	= 0x000c	; USART Data Register Empty
+.equ	UTXCaddr	= 0x000d	; USART, Tx Complete
+.equ	ADCCaddr	= 0x000e	; ADC Conversion Complete
+.equ	ERDYaddr	= 0x000f	; EEPROM Ready
+.equ	ACIaddr	= 0x0010	; Analog Comparator
+.equ	TWIaddr	= 0x0011	; 2-wire Serial Interface
+.equ	SPMRaddr	= 0x0012	; Store Program Memory Ready
+
+.equ	INT_VECTORS_SIZE	= 19	; size in words
+
+;.pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
+
+;.endif  /* _M8DEF_INC_ */
+
+; ***** END OF FILE ******************************************************

COPYING

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
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+or that patent license was granted, prior to 28 March 2007.
+
+  Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+  12. No Surrender of Others' Freedom.
+
+  If conditions are imposed on you (whether by court order, agreement or
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+
+  13. Use with the GNU Affero General Public License.
+
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+
+  14. Revised Versions of this License.
+
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+address new problems or concerns.
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+
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+
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+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
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+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.

README

@@ -0,0 +1,12 @@
+This tree contains the BLHeli assembly code for sensorless brushless motor electronic speed control (ESC) boards.
+It is designed specifically for use with Eflite mCP X, but may also be used on other copters/planes.
+
+There is one version of the software for Silabs MCU based ESCs, and another for Atmel MCU based ESCs.
+
+For more information, check out these threads on Helifreak:
+
+http://www.helifreak.com/showthread.php?t=390517 (for SiLabs MCU based ESCs)
+http://www.helifreak.com/showthread.php?t=357151 (for Atmel MCU based ESCs)
+
+April 2012,
+Steffen Skaug

SiLabs/BLHeliTxPgm.inc

@@ -0,0 +1,743 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; BLHeliTxPgm SiLabs                                      
+;                                                         
+; EEPROM is not available in SiLabs MCUs                  
+; Therefore a segment of the flash is used as "EEPROM"    
+;                                                         
+;**** **** **** **** ****
+
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read eeprom byte routine
+;
+; Assumes data in Temp1 and address in DPTR 
+; Also assumes address high byte to be zero
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_eeprom_byte:
+	clr	A
+	movc	A, @A+DPTR			; Read from flash
+	mov	Temp1, A				; Load read value
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write eeprom byte routine
+;
+; Assumes data in Temp1 and address in DPTR 
+; Also assumes address high byte to be zero
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_eeprom_byte:
+	orl	PSCTL, #01h			; Set the PSWE bit
+	anl	PSCTL, #0FDh			; Clear the PSEE bit
+	mov	FLKEY, #0A5h			; First key code
+	mov	FLKEY, #0F1h			; Second key code
+	mov	A, Temp1				; Load value to be written
+	movx	@DPTR, A				; Write to flash
+	anl	PSCTL, #0FEh			; Clear the PSWE bit
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Clear eeprom signature routine (erases the flash segment used for "eeprom" variables)
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+clear_eeprom_signature:	
+	; Erase flash
+	orl	PSCTL, #02h			; Set the PSEE bit
+	orl	PSCTL, #01h			; Set the PSWE bit
+	mov	FLKEY, #0A5h			; First key code
+	mov	FLKEY, #0F1h			; Second key code
+	mov	DPTR, #Eep_Initialized_L	
+	movx	@DPTR, A
+	anl	PSCTL, #0FCh			; Clear the PSEE and PSWE bits
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write eeprom signature routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_eeprom_signature:	
+IF TAIL == 0
+	mov	DPTR, #Eep_Initialized_L
+	mov	Temp1, #0A5h
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Initialized_H
+	mov	Temp1, #05Ah
+	call write_eeprom_byte
+ELSE
+	mov	DPTR, #Eep_Initialized_L
+	mov	Temp1, #05Ah
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Initialized_H
+	mov	Temp1, #0A5h
+	call write_eeprom_byte
+ENDIF
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read eeprom perameters routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_eeprom_parameters:	
+IF TAIL == 0
+	; Check initialized signature
+	mov	DPTR, #Eep_Initialized_L
+	call read_eeprom_byte
+	clr	C
+	mov	A, Temp1
+	subb	A, #0A5h
+	jnz	read_eeprom_store_defaults
+
+	mov	DPTR, #Eep_Initialized_H
+	call read_eeprom_byte
+	clr	C
+	mov	A, Temp1
+	subb	A, #05Ah
+	jnz	read_eeprom_store_defaults
+
+	; Read eeprom
+	mov	DPTR, #Eep_Pgm_Gov_P_Gain
+	call read_eeprom_byte
+	mov	Pgm_Gov_P_Gain, Temp1
+
+	mov	DPTR, #Eep_Pgm_Gov_I_Gain
+	call read_eeprom_byte
+	mov	Pgm_Gov_I_Gain, Temp1
+
+	mov	DPTR, #Eep_Pgm_Gov_Mode
+	call read_eeprom_byte
+	mov	Pgm_Gov_Mode, Temp1
+
+	mov	DPTR, #Eep_Pgm_Low_Voltage_Lim
+	call read_eeprom_byte
+	mov	Pgm_Low_Voltage_Lim, Temp1
+
+	mov	DPTR, #Eep_Pgm_Startup_Pwr
+	call read_eeprom_byte
+	mov	Pgm_Startup_Pwr, Temp1
+
+	mov	DPTR, #Eep_Pgm_Pwm_Freq
+	call read_eeprom_byte
+	setb	Flags2.PGM_PWM_HIGH_FREQ
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	clr	Flags2.PGM_PWM_HIGH_FREQ
+
+	mov	DPTR, #Eep_Pgm_Direction_Rev
+	call read_eeprom_byte
+	clr	Flags2.PGM_DIRECTION_REV
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_DIRECTION_REV
+
+	mov	DPTR, #Eep_Pgm_Input_Pol
+	call read_eeprom_byte
+	clr	Flags2.PGM_RCP_PWM_POL
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_RCP_PWM_POL
+ELSE
+	; Check initialized signature
+	mov	DPTR, #Eep_Initialized_L
+	call read_eeprom_byte
+	clr	C
+	mov	A, Temp1
+	subb	A, #05Ah
+	jnz	read_eeprom_store_defaults
+
+	mov	DPTR, #Eep_Initialized_H
+	call read_eeprom_byte
+	clr	C
+	mov	A, Temp1
+	subb	A, #0A5h
+	jnz	read_eeprom_store_defaults
+
+	; Read eeprom
+	mov	DPTR, #Eep_Pgm_Tail_Gain
+	call read_eeprom_byte
+	mov	Pgm_Tail_Gain, Temp1
+
+	mov	DPTR, #Eep_Pgm_Tail_Idle
+	call read_eeprom_byte
+	mov	Pgm_Tail_Idle, Temp1
+
+	mov	DPTR, #Eep_Pgm_Startup_Pwr
+	call read_eeprom_byte
+	mov	Pgm_Startup_Pwr, Temp1
+
+	mov	DPTR, #Eep_Pgm_Pwm_Freq
+	call read_eeprom_byte
+	clr	Flags2.PGM_PWM_HIGH_FREQ
+	mov	A, Temp1
+	jnb	ACC.0, ($+5)
+	setb	Flags2.PGM_PWM_HIGH_FREQ
+	clr	Flags2.PGM_PWM_OFF_DAMPED
+	clr	C
+	mov	A, Temp1
+	subb	A, #3
+	jc	($+4)
+	setb	Flags2.PGM_PWM_OFF_DAMPED
+
+	mov	DPTR, #Eep_Pgm_Direction_Rev
+	call read_eeprom_byte
+	clr	Flags2.PGM_DIRECTION_REV
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_DIRECTION_REV
+
+	mov	DPTR, #Eep_Pgm_Input_Pol
+	call read_eeprom_byte
+	clr	Flags2.PGM_RCP_PWM_POL
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_RCP_PWM_POL
+
+	mov	Pgm_Gov_Mode, #3
+ENDIF
+	jmp	read_eeprom_exit
+
+read_eeprom_store_defaults:
+	call set_default_parameters	
+	call store_all_in_eeprom	
+read_eeprom_exit:
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read all tags from flash and store in temporary storage
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_tags:
+	mov	Temp3, #48				; Number of tags
+	mov	Temp2, #Tag_Temporary_Storage	; Set RAM address
+	mov	DPTR, #Eep_ESC_Layout		; Set flash address
+read_tag:	
+	call read_eeprom_byte
+	mov	A, Temp1
+	mov	@Temp2, A			; Write to RAM
+	inc	Temp2
+	inc	DPTR
+	djnz Temp3, read_tag	
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write all tags from temporary storage and store in flash
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_tags:
+	mov	Temp3, #48				; Number of tags
+	mov	Temp2, #Tag_Temporary_Storage	; Set RAM address
+	mov	DPTR, #Eep_ESC_Layout		; Set flash address
+write_tag:	
+	mov	A, @Temp2			; Read from RAM
+	mov	Temp1, A
+	call write_eeprom_byte
+	inc	Temp2
+	inc	DPTR
+	djnz Temp3, write_tag	
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Store all parameter value in EEPROM routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+store_all_in_eeprom:
+	clr	EA						; Disable interrupts
+	call	read_tags
+	call	clear_eeprom_signature		; Erase flash
+
+	mov	DPTR, #Eep_FW_Main_Revision	; Store firmware main revision
+	mov	Temp1, #EEPROM_FW_MAIN_REVISION
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_FW_Sub_Revision	; Store firmware sub revision
+	mov	Temp1, #EEPROM_FW_SUB_REVISION
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Layout_Revision	; Store EEPROM layout revision
+	mov	Temp1, #EEPROM_LAYOUT_REVISION
+	call write_eeprom_byte
+
+IF TAIL == 0
+	mov	DPTR, #Eep_Pgm_Gov_P_Gain
+	mov	Temp1, Pgm_Gov_P_Gain
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Gov_I_Gain
+	mov	Temp1, Pgm_Gov_I_Gain
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Gov_Mode
+	mov	Temp1, Pgm_Gov_Mode
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Low_Voltage_Lim
+	mov	Temp1, Pgm_Low_Voltage_Lim
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Startup_Pwr
+	mov	Temp1, Pgm_Startup_Pwr
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Pwm_Freq
+	mov	Temp1, #1
+	jb	Flags2.PGM_PWM_HIGH_FREQ, ($+5)
+	mov	Temp1, #2
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Direction_Rev
+	mov	Temp1, #1
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	mov	Temp1, #2
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Input_Pol
+	mov	Temp1, #1
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+5)
+	mov	Temp1, #2
+	call write_eeprom_byte
+ELSE
+	mov	DPTR, #Eep_Pgm_Tail_Gain
+	mov	Temp1, Pgm_Tail_Gain
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Tail_Idle
+	mov	Temp1, Pgm_Tail_Idle
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Startup_Pwr
+	mov	Temp1, Pgm_Startup_Pwr
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Pwm_Freq
+	mov	Temp1, #1
+	jb	Flags2.PGM_PWM_HIGH_FREQ, ($+5)
+	mov	Temp1, #2
+	jnb	Flags2.PGM_PWM_OFF_DAMPED, ($+5)
+	mov	Temp1, #3
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Direction_Rev
+	mov	Temp1, #1
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	mov	Temp1, #2
+	call write_eeprom_byte
+
+	mov	DPTR, #Eep_Pgm_Input_Pol
+	mov	Temp1, #1
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+5)
+	mov	Temp1, #2
+	call write_eeprom_byte
+ENDIF
+	call	write_tags
+	call write_eeprom_signature
+	ret	
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Store new parameter value in ram routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+store_in_ram:	
+	mov	Temp4, Tx_Pgm_Func_No	; Function no
+	mov	Temp1, Tx_Pgm_Paraval_No	; Parameter value no
+IF TAIL == 0
+	mov	A, Temp4
+	clr	C
+	subb	A, #1
+	jz	store_main_func_1
+	mov	A, Temp4
+	clr	C
+	subb	A, #2
+	jz	store_main_func_2
+	mov	A, Temp4
+	clr	C
+	subb	A, #3
+	jz	store_main_func_3
+	mov	A, Temp4
+	clr	C
+	subb	A, #4
+	jz	store_main_func_4
+	mov	A, Temp4
+	clr	C
+	subb	A, #5
+	jz	store_main_func_5
+	mov	A, Temp4
+	clr	C
+	subb	A, #6
+	jz	store_main_func_6
+	mov	A, Temp4
+	clr	C
+	subb	A, #7
+	jz	store_main_func_7
+	mov	A, Temp4
+	clr	C
+	subb	A, #8
+	jz	store_main_func_8
+
+store_main_func_1:
+	mov	Pgm_Gov_P_Gain, Temp1
+	jmp	store_in_ram_exit
+
+store_main_func_2:
+	mov	Pgm_Gov_I_Gain, Temp1
+	jmp	store_in_ram_exit
+
+store_main_func_3:
+	mov	Pgm_Gov_Mode, Temp1
+	jmp	store_in_ram_exit
+
+store_main_func_4:
+	mov	Pgm_Low_Voltage_Lim, Temp1
+	jmp	store_in_ram_exit
+
+store_main_func_5:
+	mov	Pgm_Startup_Pwr, Temp1
+	jmp	store_in_ram_exit
+
+store_main_func_6:
+	setb	Flags2.PGM_PWM_HIGH_FREQ
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	clr	Flags2.PGM_PWM_HIGH_FREQ
+	jmp	store_in_ram_exit
+
+store_main_func_7:
+	clr	Flags2.PGM_DIRECTION_REV
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_DIRECTION_REV
+	jmp	store_in_ram_exit
+
+store_main_func_8:
+	clr	Flags2.PGM_RCP_PWM_POL
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_RCP_PWM_POL
+	jmp	store_in_ram_exit
+ELSE
+	mov	A, Temp4
+	clr	C
+	subb	A, #1
+	jz	store_tail_func_1
+	mov	A, Temp4
+	clr	C
+	subb	A, #2
+	jz	store_tail_func_2
+	mov	A, Temp4
+	clr	C
+	subb	A, #3
+	jz	store_tail_func_3
+	mov	A, Temp4
+	clr	C
+	subb	A, #4
+	jz	store_tail_func_4
+	mov	A, Temp4
+	clr	C
+	subb	A, #5
+	jz	store_tail_func_5
+	mov	A, Temp4
+	clr	C
+	subb	A, #6
+	jz	store_tail_func_6
+
+store_tail_func_1:
+	mov	Pgm_Tail_Gain, Temp1
+	jmp	store_in_ram_exit
+
+store_tail_func_2:
+	mov	Pgm_Tail_Idle, Temp1
+	jmp	store_in_ram_exit
+
+store_tail_func_3:
+	mov	Pgm_Startup_Pwr, Temp1
+	jmp	store_in_ram_exit
+
+store_tail_func_4:
+	clr	Flags2.PGM_PWM_HIGH_FREQ
+	mov	A, Temp1
+	jnb	ACC.0, ($+5)
+	setb	Flags2.PGM_PWM_HIGH_FREQ
+	clr	Flags2.PGM_PWM_OFF_DAMPED
+	clr	C
+	mov	A, Temp1
+	subb	A, #3
+	jc	($+4)
+	setb	Flags2.PGM_PWM_OFF_DAMPED
+	jmp	store_in_ram_exit
+
+store_tail_func_5:
+	clr	Flags2.PGM_DIRECTION_REV
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_DIRECTION_REV
+	jmp	store_in_ram_exit
+
+store_tail_func_6:
+	clr	Flags2.PGM_RCP_PWM_POL
+	mov	A, Temp1
+	jnb	ACC.1, ($+5)
+	setb	Flags2.PGM_RCP_PWM_POL
+	jmp	store_in_ram_exit
+ENDIF
+
+store_in_ram_exit:
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Wait 1 second routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+wait1s:
+	mov	Temp5, #5
+wait1s_loop:
+	call wait200ms
+	djnz	Temp5, wait1s_loop
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Success beep routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+success_beep:
+	clr	EA					; Disable all interrupts
+	call beep_f1
+	call beep_f2
+	call beep_f3
+	call beep_f4
+	call wait10ms
+	call beep_f1
+	call beep_f2
+	call beep_f3
+	call beep_f4
+	call wait10ms
+	call beep_f1
+	call beep_f2
+	call beep_f3
+	call beep_f4
+	setb	EA					; Enable all interrupts
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Function and parameter value beep routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+function_paraval_beep:
+	mov	Temp5, Tx_Pgm_Func_No	; Function no
+	mov	Temp6, Tx_Pgm_Paraval_No	; Parameter value no
+	clr	EA					; Disable all interrupts
+function_beep:
+	call beep_f1				
+	call beep_f1
+	call beep_f1
+	call wait10ms
+	djnz	Temp5, function_beep
+paraval_beep:
+	call beep_f4
+	call wait10ms
+	djnz	Temp6, paraval_beep
+	setb	EA					; Enable all interrupts
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Program by TX routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+program_by_tx:	
+	; Start programming mode entry sequence by waiting for low RC pulse
+	clr	EA					; Disable all interrupts
+	call beep_f4
+	setb	EA					; Enable all interrupts
+	call wait100ms
+	clr	C
+	mov	A, New_Rcp			; Load new RC pulse value
+	subb	A, #RCP_STOP			; Below stop?
+	jnc	program_by_tx			; No - start over
+
+	; Continue programming mode entry sequence by waiting for high RC pulse
+wait_for_rc_pulse_max:
+	clr	EA					; Disable all interrupts
+	call beep_f1
+	call wait10ms
+	call beep_f1
+	setb	EA					; Enable all interrupts
+	call wait100ms
+	clr	C
+	mov	A, New_Rcp			; Load new RC pulse value
+	subb	A, #RCP_MAX			; Above max?
+	jc	wait_for_rc_pulse_max	; No - start over
+
+	; Programming mode entry beeps
+	call success_beep
+	call wait1s
+	call wait1s
+
+	; Start at function 1, parameter value 1
+	mov	Tx_Pgm_Func_No, #1
+paraval_no_entry:
+	mov	Tx_Pgm_Paraval_No, #1
+beep_no_entry:
+	mov	Tx_Pgm_Beep_No, #0
+func_paraval:
+	call function_paraval_beep
+	mov	Temp5, #5				; Wait is 5x 200ms
+func_paraval_wait:
+	call wait200ms
+	clr	C
+	mov	A, New_Rcp			; Load new RC pulse value
+	subb	A, #RCP_STOP			; Below stop?
+	jnc	func_paraval_cont_wait	; No - branch
+
+	call	store_in_ram			; Yes - store new value in RAM
+	call	store_all_in_eeprom		; Store all values in EEPROM
+	call success_beep			; Beep success
+	clr	EA					; Disable all interrupts
+	orl	RSTSRC, #10h			; Generate hardware reset
+	call wait1s
+
+func_paraval_cont_wait:
+	djnz	Temp5, func_paraval_wait
+	inc	Tx_Pgm_Beep_No			; Check number of beeps
+	clr	C
+	mov	A, Tx_Pgm_Beep_No		
+	subb	A, #3				; Three beeps done?
+	jnc	paraval_next			; Yes - Next parameter value
+
+	jmp	func_paraval			; No - go back
+
+paraval_next:					
+	call wait1s
+	inc	Tx_Pgm_Paraval_No		; Parameter value no
+	mov	Temp1, #5				; Default 5 parameter values
+IF TAIL == 0
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #3				; Function 3?
+	jnz	paraval_end_a			; No - branch
+	mov	Temp1, #3				; Yes - set max parameter values
+paraval_end_a:
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #4				; Function 4?
+	jnz	paraval_end_b			; No - branch
+	mov	Temp1, #3				; Yes - set max parameter values
+paraval_end_b:
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #5				; Function below 5?
+	jc 	paraval_end_c			; Yes - branch
+	mov	Temp1, #2				; No - set max parameter values
+paraval_end_c:
+ELSE
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #4				; Function below 4?
+	jc 	paraval_end_a			; Yes - branch
+	mov	Temp1, #3				; No - set max parameter values
+paraval_end_a:
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #(4+DAMPED_TAIL_ENABLE)	; Function below 5 (damped tail enabled)?
+	jc 	paraval_end_b			; Yes - branch
+	mov	Temp1, #2				; No - set max parameter values
+paraval_end_b:
+ENDIF
+	inc	Temp1
+	clr	C
+	mov	A, Tx_Pgm_Paraval_No		
+	subb	A, Temp1				
+	jnc 	function_next			; Last parameter value?
+	jmp	beep_no_entry			; No - go back
+
+function_next:					; Yes - Next function value
+	call wait1s
+	call wait1s
+	inc	Tx_Pgm_Func_No			; Function value no
+IF TAIL == 0
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #9				; Main has 8 functions	
+ELSE
+	clr	C
+	mov	A, Tx_Pgm_Func_No		
+	subb	A, #7				; Tail has 6 functions	
+ENDIF
+	jnc 	program_by_tx_exit		; Last function value?
+	jmp	paraval_no_entry		; No - go back
+
+program_by_tx_exit:
+	clr	EA					; Disable all interrupts
+	orl	RSTSRC, #10h			; Generate hardware reset
+	call wait1s
+

SiLabs/C8051F330.INC

@@ -0,0 +1,204 @@
+;---------------------------------------------------------------------------
+; 
+; 
+;
+;
+; FILE NAME: C8051F330.INC
+; TARGET MCUs: C8051F330, F331
+; DESCRIPTION: Register/bit definitions for the C8051F330 product family.
+;
+; REVISION 1.0
+;
+;---------------------------------------------------------------------------
+
+;REGISTER DEFINITIONS
+;
+P0             DATA 080H    ; PORT 0 LATCH
+SP             DATA 081H    ; STACK POINTER
+DPL            DATA 082H    ; DATA POINTER LOW
+DPH            DATA 083H    ; DATA POINTER HIGH
+PCON           DATA 087H    ; POWER CONTROL
+TCON           DATA 088H    ; TIMER/COUNTER CONTROL
+TMOD           DATA 089H    ; TIMER/COUNTER MODE
+TL0            DATA 08AH    ; TIMER/COUNTER 0 LOW
+TL1            DATA 08BH    ; TIMER/COUNTER 1 LOW
+TH0            DATA 08CH    ; TIMER/COUNTER 0 HIGH
+TH1            DATA 08DH    ; TIMER/COUNTER 1 HIGH
+CKCON          DATA 08EH    ; CLOCK CONTROL
+PSCTL          DATA 08FH    ; PROGRAM STORE R/W CONTROL
+P1             DATA 090H    ; PORT 1 LATCH
+TMR3CN         DATA 091H    ; TIMER/COUNTER 3 CONTROL
+TMR3RLL        DATA 092H    ; TIMER/COUNTER 3 RELOAD LOW
+TMR3RLH        DATA 093H    ; TIMER/COUNTER 3 RELOAD HIGH
+TMR3L          DATA 094H    ; TIMER/COUNTER 3 LOW
+TMR3H          DATA 095H    ; TIMER/COUNTER 3 HIGH
+IDA0L          DATA 096H    ; CURRENT MODE DAC0 LOW
+IDA0H          DATA 097H    ; CURRENT MODE DAC0 HIGH
+SCON0          DATA 098H    ; UART0 CONTROL
+SBUF0          DATA 099H    ; UART0 DATA BUFFER
+CPT0CN         DATA 09BH    ; COMPARATOR0 CONTROL
+CPT0MD         DATA 09DH    ; COMPARATOR0 MODE SELECTION
+CPT0MX         DATA 09FH    ; COMPARATOR0 MUX SELECTION
+P2             DATA 0A0H    ; PORT 2 LATCH
+SPI0CFG        DATA 0A1H    ; SPI CONFIGURATION
+SPI0CKR        DATA 0A2H    ; SPI CLOCK RATE CONTROL
+SPI0DAT        DATA 0A3H    ; SPI DATA
+P0MDOUT        DATA 0A4H    ; PORT 0 OUTPUT MODE CONFIGURATION
+P1MDOUT        DATA 0A5H    ; PORT 1 OUTPUT MODE CONFIGURATION
+P2MDOUT        DATA 0A6H    ; PORT 2 OUTPUT MODE CONFIGURATION
+IE             DATA 0A8H    ; INTERRUPT ENABLE
+CLKSEL         DATA 0A9H    ; CLOCK SELECT
+EMI0CN         DATA 0AAH    ; EXTERNAL MEMORY INTERFACE CONTROL
+OSCXCN         DATA 0B1H    ; EXTERNAL OSCILLATOR CONTROL
+OSCICN         DATA 0B2H    ; INTERNAL OSCILLATOR CONTROL
+OSCICL         DATA 0B3H    ; INTERNAL OSCILLATOR CALIBRATION
+FLSCL          DATA 0B6H    ; FLASH SCALE
+FLKEY          DATA 0B7H    ; FLASH LOCK AND KEY
+IP             DATA 0B8H    ; INTERRUPT PRIORITY
+IDA0CN         DATA 0B9H    ; CURRENT MODE DAC0 CONTROL
+AMX0N          DATA 0BAH    ; AMUX0 NEGATIVE CHANNEL SELECT
+AMX0P          DATA 0BBH    ; AMUX0 POSITIVE CHANNEL SELECT
+ADC0CF         DATA 0BCH    ; ADC0 CONFIGURATION
+ADC0L          DATA 0BDH    ; ADC0 LOW
+ADC0H          DATA 0BEH    ; ADC0 HIGH
+SMB0CN         DATA 0C0H    ; SMBUS CONTROL
+SMB0CF         DATA 0C1H    ; SMBUS CONFIGURATION
+SMB0DAT        DATA 0C2H    ; SMBUS DATA
+ADC0GTL        DATA 0C3H    ; ADC0 GREATER-THAN COMPARE LOW
+ADC0GTH        DATA 0C4H    ; ADC0 GREATER-THAN COMPARE HIGH
+ADC0LTL        DATA 0C5H    ; ADC0 LESS-THAN COMPARE WORD LOW
+ADC0LTH        DATA 0C6H    ; ADC0 LESS-THAN COMPARE WORD HIGH
+TMR2CN         DATA 0C8H    ; TIMER/COUNTER 2 CONTROL
+TMR2RLL        DATA 0CAH    ; TIMER/COUNTER 2 RELOAD LOW
+TMR2RLH        DATA 0CBH    ; TIMER/COUNTER 2 RELOAD HIGH
+TMR2L          DATA 0CCH    ; TIMER/COUNTER 2 LOW
+TMR2H          DATA 0CDH    ; TIMER/COUNTER 2 HIGH
+PSW            DATA 0D0H    ; PROGRAM STATUS WORD
+REF0CN         DATA 0D1H    ; VOLTAGE REFERENCE CONTROL
+P0SKIP         DATA 0D4H    ; PORT 0 SKIP
+P1SKIP         DATA 0D5H    ; PORT 1 SKIP
+PCA0CN         DATA 0D8H    ; PCA CONTROL
+PCA0MD         DATA 0D9H    ; PCA MODE
+PCA0CPM0       DATA 0DAH    ; PCA MODULE 0 MODE REGISTER
+PCA0CPM1       DATA 0DBH    ; PCA MODULE 1 MODE REGISTER
+PCA0CPM2       DATA 0DCH    ; PCA MODULE 2 MODE REGISTER
+ACC            DATA 0E0H    ; ACCUMULATOR
+XBR0           DATA 0E1H    ; PORT I/O CROSSBAR CONTROL 0
+XBR1           DATA 0E2H    ; PORT I/O CROSSBAR CONTROL 1
+OSCLCN         DATA 0E3H    ; LOW-FREQUENCY OSCILLATOR CONTROL
+IT01CF         DATA 0E4H    ; INT0/INT1 CONFIGURATION
+EIE1           DATA 0E6H    ; EXTENDED INTERRUPT ENABLE 1
+ADC0CN         DATA 0E8H    ; ADC0 CONTROL
+PCA0CPL1       DATA 0E9H    ; PCA CAPTURE 1 LOW
+PCA0CPH1       DATA 0EAH    ; PCA CAPTURE 1 HIGH
+PCA0CPL2       DATA 0EBH    ; PCA CAPTURE 2 LOW
+PCA0CPH2       DATA 0ECH    ; PCA CAPTURE 2 HIGH
+RSTSRC         DATA 0EFH    ; RESET SOURCE CONFIGURATION/STATUS
+B              DATA 0F0H    ; B REGISTER
+P0MDIN         DATA 0F1H    ; PORT 0 INPUT MODE CONFIGURATION
+P1MDIN         DATA 0F2H    ; PORT 1 INPUT MODE CONFIGURATION
+EIP1           DATA 0F6H    ; EXTENDED INTERRUPT PRIORITY 1
+SPI0CN         DATA 0F8H    ; SPI CONTROL
+PCA0L          DATA 0F9H    ; PCA COUNTER LOW
+PCA0H          DATA 0FAH    ; PCA COUNTER HIGH
+PCA0CPL0       DATA 0FBH    ; PCA CAPTURE 0 LOW
+PCA0CPH0       DATA 0FCH    ; PCA CAPTURE 0 HIGH
+VDM0CN         DATA 0FFH    ; VDD MONITOR CONTROL
+
+;
+;------------------------------------------------------------------------------
+;BIT DEFINITIONS
+;
+; TCON 088H
+TF1            BIT 08FH     ; TIMER 1 OVERFLOW FLAG
+TR1            BIT 08EH     ; TIMER 1 ON/OFF CONTROL
+TF0            BIT 08DH     ; TIMER 0 OVERFLOW FLAG
+TR0            BIT 08CH     ; TIMER 0 ON/OFF CONTROL
+IE1            BIT 08BH     ; EXT. INTERRUPT 1 EDGE FLAG
+IT1            BIT 08AH     ; EXT. INTERRUPT 1 TYPE
+IE0            BIT 089H     ; EXT. INTERRUPT 0 EDGE FLAG
+IT0            BIT 088H     ; EXT. INTERRUPT 0 TYPE
+
+; SCON0 098H
+S0MODE         BIT 09FH     ; UART 0 MODE
+MCE0           BIT 09DH     ; UART 0 MCE
+REN0           BIT 09CH     ; UART 0 RX ENABLE
+TB80           BIT 09BH     ; UART 0 TX BIT 8
+RB80           BIT 09AH     ; UART 0 RX BIT 8
+TI0            BIT 099H     ; UART 0 TX INTERRUPT FLAG
+RI0            BIT 098H     ; UART 0 RX INTERRUPT FLAG
+
+; IE 0A8H
+EA             BIT 0AFH     ; GLOBAL INTERRUPT ENABLE
+ESPI0          BIT 0AEH     ; SPI0 INTERRUPT ENABLE
+ET2            BIT 0ADH     ; TIMER 2 INTERRUPT ENABLE
+ES0            BIT 0ACH     ; UART0 INTERRUPT ENABLE
+ET1            BIT 0ABH     ; TIMER 1 INTERRUPT ENABLE
+EX1            BIT 0AAH     ; EXTERNAL INTERRUPT 1 ENABLE
+ET0            BIT 0A9H     ; TIMER 0 INTERRUPT ENABLE
+EX0            BIT 0A8H     ; EXTERNAL INTERRUPT 0 ENABLE
+
+; IP 0B8H
+PSPI0          BIT 0BEH     ; SPI0 PRIORITY
+PT2            BIT 0BDH     ; TIMER 2 PRIORITY
+PS0            BIT 0BCH     ; UART0 PRIORITY
+PT1            BIT 0BBH     ; TIMER 1 PRIORITY
+PX1            BIT 0BAH     ; EXTERNAL INTERRUPT 1 PRIORITY
+PT0            BIT 0B9H     ; TIMER 0 PRIORITY
+PX0            BIT 0B8H     ; EXTERNAL INTERRUPT 0 PRIORITY
+
+; SMB0CN 0C0H
+MASTER         BIT 0C7H     ; SMBUS 0 MASTER/SLAVE
+TXMODE         BIT 0C6H     ; SMBUS 0 TRANSMIT MODE
+STA            BIT 0C5H     ; SMBUS 0 START FLAG
+STO            BIT 0C4H     ; SMBUS 0 STOP FLAG
+ACKRQ          BIT 0C3H     ; SMBUS 0 ACKNOWLEDGE REQUEST
+ARBLOST        BIT 0C2H     ; SMBUS 0 ARBITRATION LOST
+ACK            BIT 0C1H     ; SMBUS 0 ACKNOWLEDGE FLAG
+SI             BIT 0C0H     ; SMBUS 0 INTERRUPT PENDING FLAG
+
+; TMR2CN 0C8H
+TF2H           BIT 0CFH     ; TIMER 2 HIGH BYTE OVERFLOW FLAG
+TF2L           BIT 0CEH     ; TIMER 2 LOW BYTE OVERFLOW FLAG
+TF2LEN         BIT 0CDH     ; TIMER 2 LOW BYTE INTERRUPT ENABLE
+TF2CEN         BIT 0CCH     ; TIMER 2 LFO CAPTURE ENABLE
+T2SPLIT        BIT 0CBH     ; TIMER 2 SPLIT MODE ENABLE
+TR2            BIT 0CAH     ; TIMER 2 ON/OFF CONTROL
+T2XCLK         BIT 0C8H     ; TIMER 2 EXTERNAL CLOCK SELECT
+
+; PSW 0D0H
+CY             BIT 0D7H     ; CARRY FLAG
+AC             BIT 0D6H     ; AUXILIARY CARRY FLAG
+F0             BIT 0D5H     ; USER FLAG 0
+RS1            BIT 0D4H     ; REGISTER BANK SELECT 1
+RS0            BIT 0D3H     ; REGISTER BANK SELECT 0
+OV             BIT 0D2H     ; OVERFLOW FLAG
+F1             BIT 0D1H     ; USER FLAG 1
+P              BIT 0D0H     ; ACCUMULATOR PARITY FLAG
+
+; PCA0CN 0D8H
+CF             BIT 0DFH     ; PCA 0 COUNTER OVERFLOW FLAG
+CR             BIT 0DEH     ; PCA 0 COUNTER RUN CONTROL BIT
+CCF2           BIT 0DAH     ; PCA 0 MODULE 2 INTERRUPT FLAG
+CCF1           BIT 0D9H     ; PCA 0 MODULE 1 INTERRUPT FLAG
+CCF0           BIT 0D8H     ; PCA 0 MODULE 0 INTERRUPT FLAG
+                            ; ADC 0 WINDOW INTERRUPT FLAG
+; ADC0CN 0E8H
+AD0EN          BIT 0EFH     ; ADC 0 ENABLE
+AD0TM          BIT 0EEH     ; ADC 0 TRACK MODE
+AD0INT         BIT 0EDH     ; ADC 0 EOC INTERRUPT FLAG
+AD0BUSY        BIT 0ECH     ; ADC 0 BUSY FLAG
+AD0WINT        BIT 0EBH     ; ADC 0 WINDOW INTERRUPT FLAG
+AD0CM2         BIT 0EAH     ; ADC 0 CONVERT START MODE BIT 2
+AD0CM1         BIT 0E9H     ; ADC 0 CONVERT START MODE BIT 1
+AD0CM0         BIT 0E8H     ; ADC 0 CONVERT START MODE BIT 0
+
+; SPI0CN 0F8H
+SPIF           BIT 0FFH     ; SPI 0 INTERRUPT FLAG
+WCOL           BIT 0FEH     ; SPI 0 WRITE COLLISION FLAG
+MODF           BIT 0FDH     ; SPI 0 MODE FAULT FLAG
+RXOVRN         BIT 0FCH     ; SPI 0 RX OVERRUN FLAG
+NSSMD1         BIT 0FBH     ; SPI 0 SLAVE SELECT MODE 1
+NSSMD0         BIT 0FAH     ; SPI 0 SLAVE SELECT MODE 0
+TXBMT          BIT 0F9H     ; SPI 0 TX BUFFER EMPTY FLAG
+SPIEN          BIT 0F8H     ; SPI 0 SPI ENABLE

SiLabs/DP_3A.inc

@@ -0,0 +1,256 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; DP 3A hardware definition file
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs F330
+;*********************
+$include (c8051f330.inc)
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+CSEG AT 1A40h
+Eep_ESC_Layout:		DB	"#DP3A#          "	; ESC layout tag
+DAMPED_TAIL_ENABLE		EQU	1	; Damped tail mode enabled
+NFETON_DELAY			EQU	2	; Wait delay from pfets off to nfets on
+PFETON_DELAY			EQU	1	; Wait delay from nfets off to pfets on
+ADC_LIMIT_L			EQU 	128	; Power supply measurement ADC value for which main motor power is limited (low byte)
+ADC_LIMIT_H			EQU	2	; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+Rcp_In		EQU	6	;i
+Mux_A		EQU	5	;i
+;			EQU	4	;i
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	NOT(1 SHL Rcp_In) AND 0FFh
+
+MACRO Read_Rcp_Int
+	mov	A, P0
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+4)	; Is pwm polarity negative?
+	cpl	A						; Yes - invert
+ENDM
+MACRO Rcp_Int_Enable
+	orl	PCA0CPM0, #01h				; Interrupt enabled
+ENDM
+MACRO Rcp_Int_Disable
+	anl	PCA0CPM0, #0FEh			; Interrupt disabled
+ENDM
+MACRO Rcp_Int_First
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+ENDM
+MACRO Rcp_Int_Second
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+ENDM
+MACRO Rcp_Clear_Int_Flag
+	clr 	CCF0						; Clear interrupt flag
+ENDM		
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+Ref_Gnd		EQU	7	;o
+Adc_Ip		EQU	6	;i
+CpFET		EQU	5	;o
+BpFET		EQU	4	;o
+ApFET		EQU	3	;o
+CnFET		EQU	2	;o
+BnFET		EQU	1	;i
+AnFET		EQU	0	;i
+
+P1_DIGITAL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)+(1 SHL Ref_Gnd)
+P1_INIT		EQU 	(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)+(1 SHL Adc_Ip)		; Setting pFET outputs turn them off
+P1_PUSHPULL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_SKIP		EQU	0
+
+MACRO AnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+ENDM
+MACRO AnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+ENDM
+MACRO BnFET_on
+	setb	P1.BnFET
+ENDM
+MACRO BnFET_off
+	clr	P1.BnFET
+ENDM
+MACRO CnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+ENDM
+MACRO CnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+ENDM
+MACRO All_nFETs_Off
+	clr	P1.AnFET
+	clr	P1.BnFET
+	clr	P1.CnFET
+ENDM
+
+MACRO ApFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+ENDM
+MACRO ApFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+ENDM
+MACRO BpFET_on
+	clr	P1.BpFET
+ENDM
+MACRO BpFET_off
+	setb	P1.BpFET
+ENDM
+MACRO CpFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+ENDM
+MACRO CpFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+ENDM
+MACRO All_pFETs_Off
+	setb	P1.ApFET
+	setb	P1.BpFET
+	setb	P1.CpFET
+ENDM
+MACRO All_pFETs_On
+	clr	P1.ApFET
+	clr	P1.BpFET
+	clr	P1.CpFET
+ENDM
+
+MACRO Set_Comp_Phase_A
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h	; Set comparator multiplexer to phase A
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h
+ENDM
+MACRO Set_Comp_Phase_B
+	mov	CPT0MX, #11h	; Set comparator multiplexer to phase B
+ENDM
+MACRO Set_Comp_Phase_C
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h	; Set comparator multiplexer to phase C
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h
+ENDM
+MACRO Read_Comp_Out
+	mov	A, CPT0CN		; Read comparator output
+	cpl	A			; Invert output
+ENDM
+
+
+;*********************
+; PORT B definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+MACRO Interrupt_Table_Definition
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 0Bh			; Timer0 interrupt	
+	jmp	t0_int	
+CSEG AT 2Bh			; Timer2 interrupt	
+	jmp	t2_int	
+CSEG AT 5Bh			; PCA interrupt	
+	jmp	pca_int	
+CSEG AT 73h			; Timer3 interrupt	
+	jmp	t3_int	
+ENDM
+
+MACRO Initialize_Adc
+	mov	REF0CN, #01h		; Enable reference buffer
+	mov	ADC0CF, #0B8h		; ADC clock 1MHz
+	mov	AMX0P, #(8+Adc_Ip)	; Select positive input
+	mov	AMX0N, #11h		; Select negative input as ground
+	mov	ADC0CN, #80h		; ADC enabled
+ENDM
+MACRO Start_Adc
+	mov	ADC0CN, #90h	; ADC start
+ENDM
+MACRO Get_Adc_Status
+	mov	A, ADC0CN		
+ENDM
+MACRO Read_Adc_Result
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+MACRO Stop_Adc
+ENDM

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SiLabs/Hex files/DP 3A Tail.hex

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SiLabs/Hex files/Supermicro_3p5A Main.hex

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SiLabs/Hex files/Supermicro_3p5A Tail.hex

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SiLabs/Hex files/XP 12A Main.hex

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SiLabs/Hex files/XP 12A Tail.hex

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SiLabs/Hex files/XP 3A Main.hex

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SiLabs/Hex files/XP 3A Tail.hex

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SiLabs/Hex files/XP 7A Main.hex

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SiLabs/Hex files/XP 7A Tail.hex

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SiLabs/README

@@ -0,0 +1,31 @@
+This tree contains the BLHeli assembly code for sensorless brushless motor electronic speed control (ESC) boards.
+It is designed specifically for use with Eflite mCP X, but may also be used on other copters/planes.
+
+This tree contains SiLabs assembly code for SiLabs MCU based ESCs. 
+
+Features and Changes
+--------------------
+- Can be configured for main motor or tail motor operation
+- Main motor operation has governor functionality
+- Tail motor operation can be damped for fast motor retardation
+- Many parmeters can be programmed from the TX
+- Supports 1kHz, 2kHz, 4kHz or 8kHz positive or negative pwm as input signal
+
+Supported Hardware
+------------------
+- DP 3A
+- Supermicro 3.5A
+- XP 3A
+- XP 7A
+- XP 12A
+- Turnigy 6A
+
+Installation and use
+--------------------
+The software is written and debugged in the SiLabs IDE.
+Compilation is done using Raisonance Ride7 and Rkit-51 toolchain.
+
+For more information, check out this thread:
+
+http://www.helifreak.com/showthread.php?t=390517
+

SiLabs/Supermicro_3p5A.inc

@@ -0,0 +1,256 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Supermicro 3.5A hardware definition file
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs F330
+;*********************
+$include (c8051f330.inc)
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+CSEG AT 1A40h
+Eep_ESC_Layout:		DB	"#Supermicro3p5A#"	; ESC layout tag
+DAMPED_TAIL_ENABLE		EQU	1	; Damped tail mode enabled
+NFETON_DELAY			EQU	2	; Wait delay from pfets off to nfets on
+PFETON_DELAY			EQU	1	; Wait delay from nfets off to pfets on
+ADC_LIMIT_L			EQU 	128	; Power supply measurement ADC value for which main motor power is limited (low byte)
+ADC_LIMIT_H			EQU	2	; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+Rcp_In		EQU	6	;i
+Mux_A		EQU	5	;i
+;			EQU	4	;i
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	NOT(1 SHL Rcp_In) AND 0FFh
+
+MACRO Read_Rcp_Int
+	mov	A, P0
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+4)	; Is pwm polarity negative?
+	cpl	A						; Yes - invert
+ENDM
+MACRO Rcp_Int_Enable
+	orl	PCA0CPM0, #01h				; Interrupt enabled
+ENDM
+MACRO Rcp_Int_Disable
+	anl	PCA0CPM0, #0FEh			; Interrupt disabled
+ENDM
+MACRO Rcp_Int_First
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+ENDM
+MACRO Rcp_Int_Second
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+ENDM
+MACRO Rcp_Clear_Int_Flag
+	clr 	CCF0						; Clear interrupt flag
+ENDM		
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+Ref_Gnd		EQU	7	;o
+Adc_Ip		EQU	6	;i
+CpFET		EQU	5	;o
+BpFET		EQU	4	;o
+ApFET		EQU	3	;o
+CnFET		EQU	2	;o
+BnFET		EQU	1	;i
+AnFET		EQU	0	;i
+
+P1_DIGITAL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)+(1 SHL Ref_Gnd)
+P1_INIT		EQU 	(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)+(1 SHL Adc_Ip)		; Setting pFET outputs turn them off
+P1_PUSHPULL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_SKIP		EQU	0
+
+MACRO AnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+ENDM
+MACRO AnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+ENDM
+MACRO BnFET_on
+	setb	P1.BnFET
+ENDM
+MACRO BnFET_off
+	clr	P1.BnFET
+ENDM
+MACRO CnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+ENDM
+MACRO CnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+ENDM
+MACRO All_nFETs_Off
+	clr	P1.AnFET
+	clr	P1.BnFET
+	clr	P1.CnFET
+ENDM
+
+MACRO ApFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+ENDM
+MACRO ApFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+ENDM
+MACRO BpFET_on
+	clr	P1.BpFET
+ENDM
+MACRO BpFET_off
+	setb	P1.BpFET
+ENDM
+MACRO CpFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+ENDM
+MACRO CpFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+ENDM
+MACRO All_pFETs_Off
+	setb	P1.ApFET
+	setb	P1.BpFET
+	setb	P1.CpFET
+ENDM
+MACRO All_pFETs_On
+	clr	P1.ApFET
+	clr	P1.BpFET
+	clr	P1.CpFET
+ENDM
+
+MACRO Set_Comp_Phase_A
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h	; Set comparator multiplexer to phase A
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h
+ENDM
+MACRO Set_Comp_Phase_B
+	mov	CPT0MX, #11h	; Set comparator multiplexer to phase B
+ENDM
+MACRO Set_Comp_Phase_C
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h	; Set comparator multiplexer to phase C
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h
+ENDM
+MACRO Read_Comp_Out
+	mov	A, CPT0CN		; Read comparator output
+	cpl	A			; Invert output
+ENDM
+
+
+;*********************
+; PORT B definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+MACRO Interrupt_Table_Definition
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 0Bh			; Timer0 interrupt	
+	jmp	t0_int	
+CSEG AT 2Bh			; Timer2 interrupt	
+	jmp	t2_int	
+CSEG AT 5Bh			; PCA interrupt	
+	jmp	pca_int	
+CSEG AT 73h			; Timer3 interrupt	
+	jmp	t3_int	
+ENDM
+
+MACRO Initialize_Adc
+	mov	REF0CN, #01h		; Enable reference buffer
+	mov	ADC0CF, #0B8h		; ADC clock 1MHz
+	mov	AMX0P, #(8+Adc_Ip)	; Select positive input
+	mov	AMX0N, #11h		; Select negative input as ground
+	mov	ADC0CN, #80h		; ADC enabled
+ENDM
+MACRO Start_Adc
+	mov	ADC0CN, #90h	; ADC start
+ENDM
+MACRO Get_Adc_Status
+	mov	A, ADC0CN		
+ENDM
+MACRO Read_Adc_Result
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+MACRO Stop_Adc
+ENDM

SiLabs/Turnigy6A.inc

@@ -0,0 +1,255 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Turnigy 6A hardware definition file
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs F330
+;*********************
+$include (c8051f330.inc)
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+CSEG AT 1A40h
+Eep_ESC_Layout:		DB	"#Turnigy6A#     "	; ESC layout tag
+DAMPED_TAIL_ENABLE		EQU	0	; Damped tail mode disabled
+NFETON_DELAY			EQU	22	; Wait delay from pfets off to nfets on
+PFETON_DELAY			EQU	12	; Wait delay from nfets off to pfets on
+ADC_LIMIT_L			EQU 	136	; Power supply measurement ADC value for which main motor power is limited (low byte)
+ADC_LIMIT_H			EQU	1	; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+Mux_B		EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i
+Comp_Com		EQU	3	;i
+Mux_A		EQU	2	;i
+;			EQU	1	;i
+Mux_C		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	NOT(1 SHL Rcp_In)
+
+MACRO Read_Rcp_Int
+	mov	A, P0
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+4)	; Is pwm polarity negative?
+	cpl	A						; Yes - invert
+ENDM
+MACRO Rcp_Int_Enable
+	orl	PCA0CPM0, #01h				; Interrupt enabled
+ENDM
+MACRO Rcp_Int_Disable
+	anl	PCA0CPM0, #0FEh			; Interrupt disabled
+ENDM
+MACRO Rcp_Int_First
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+ENDM
+MACRO Rcp_Int_Second
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+ENDM
+MACRO Rcp_Clear_Int_Flag
+	clr 	CCF0						; Clear interrupt flag
+ENDM		
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+AnFET		EQU	7	;o
+ApFET		EQU	6	;o
+CnFET		EQU	5	;o
+CpFET		EQU	4	;o
+BnFET		EQU	3	;o
+BpFET		EQU	2	;o
+;			EQU	1	;i
+Adc_Ip		EQU	0	;i
+
+P1_DIGITAL	EQU	NOT(1 SHL Adc_Ip)
+P1_INIT		EQU 	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL Adc_Ip)		; Setting nFET outputs turn them off. Setting ADC ip sets it tristate
+P1_PUSHPULL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_SKIP		EQU	(1 SHL Adc_Ip)
+
+MACRO AnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+ENDM
+MACRO AnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+ENDM
+MACRO CnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+ENDM
+MACRO CnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+ENDM
+MACRO BnFET_on
+	clr	P1.BnFET
+ENDM
+MACRO BnFET_off
+	setb	P1.BnFET
+ENDM
+MACRO All_nFETs_Off
+	setb	P1.AnFET
+	setb	P1.CnFET
+	setb	P1.BnFET
+ENDM
+
+MACRO ApFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+ENDM
+MACRO ApFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+ENDM
+MACRO CpFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+ENDM
+MACRO CpFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+ENDM
+MACRO BpFET_on
+	setb	P1.BpFET
+ENDM
+MACRO BpFET_off
+	clr	P1.BpFET
+ENDM
+MACRO All_pFETs_Off
+	clr	P1.ApFET
+	clr	P1.CpFET
+	clr	P1.BpFET
+ENDM
+MACRO All_pFETs_On
+	setb	P1.ApFET
+	setb	P1.CpFET
+	setb	P1.BpFET
+ENDM
+
+MACRO Set_Comp_Phase_A
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #11h	; Set comparator multiplexer to phase A
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #10h
+ENDM
+MACRO Set_Comp_Phase_C
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #10h	; Set comparator multiplexer to phase C
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #11h
+ENDM
+MACRO Set_Comp_Phase_B
+	mov	CPT0MX, #13h	; Set comparator multiplexer to phase B
+ENDM
+MACRO Read_Comp_Out
+	mov	A, CPT0CN		; Read comparator output
+ENDM
+
+
+;*********************
+; PORT B definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+MACRO Interrupt_Table_Definition
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 0Bh			; Timer0 interrupt	
+	jmp	t0_int	
+CSEG AT 2Bh			; Timer2 interrupt	
+	jmp	t2_int	
+CSEG AT 5Bh			; PCA interrupt	
+	jmp	pca_int	
+CSEG AT 73h			; Timer3 interrupt	
+	jmp	t3_int	
+ENDM
+
+MACRO Initialize_Adc
+	mov	REF0CN, #04h	; Set vdd (3.3V) as reference
+	mov	ADC0CF, #0B8h	; ADC clock 1MHz
+	mov	AMX0P, #Adc_Ip	; Select positive input
+	mov	AMX0N, #11h	; Select negative input as ground
+	mov	ADC0CN, #80h	; ADC enabled
+ENDM
+MACRO Start_Adc
+	mov	ADC0CN, #90h	; ADC start
+ENDM
+MACRO Get_Adc_Status
+	mov	A, ADC0CN		
+ENDM
+MACRO Read_Adc_Result
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+MACRO Stop_Adc
+ENDM

SiLabs/XP_12A.inc

@@ -0,0 +1,256 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; XP 12A hardware definition file
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs F330
+;*********************
+$include (c8051f330.inc)
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+CSEG AT 1A40h
+Eep_ESC_Layout:		DB	"#XP12A#         "	; ESC layout tag
+DAMPED_TAIL_ENABLE		EQU	0	; Damped tail mode disabled
+NFETON_DELAY			EQU	22	; Wait delay from pfets off to nfets on
+PFETON_DELAY			EQU	5	; Wait delay from nfets off to pfets on
+ADC_LIMIT_L			EQU 	116	; Power supply measurement ADC value for which main motor power is limited (low byte)
+ADC_LIMIT_H			EQU	0	; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Rcp_In		EQU	7	;i
+Adc_Ip		EQU	6	;i
+Mux_A		EQU	5	;i
+;			EQU	4	;i
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)+(1 SHL Adc_Ip))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	NOT(1 SHL Rcp_In) AND 0FFh
+
+MACRO Read_Rcp_Int
+	mov	A, P0
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+4)	; Is pwm polarity negative?
+	cpl	A						; Yes - invert
+ENDM
+MACRO Rcp_Int_Enable
+	orl	PCA0CPM0, #01h				; Interrupt enabled
+ENDM
+MACRO Rcp_Int_Disable
+	anl	PCA0CPM0, #0FEh			; Interrupt disabled
+ENDM
+MACRO Rcp_Int_First
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+ENDM
+MACRO Rcp_Int_Second
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+ENDM
+MACRO Rcp_Clear_Int_Flag
+	clr 	CCF0						; Clear interrupt flag
+ENDM		
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;o
+;			EQU	6	;o
+ApFET		EQU	5	;o
+BpFET		EQU	4	;o
+CpFET		EQU	3	;o
+AnFET		EQU	2	;o
+BnFET		EQU	1	;i
+CnFET		EQU	0	;i
+
+P1_DIGITAL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_INIT		EQU 	0		
+P1_PUSHPULL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_SKIP		EQU	0
+
+MACRO AnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+ENDM
+MACRO AnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+ENDM
+MACRO BnFET_on
+	setb	P1.BnFET
+ENDM
+MACRO BnFET_off
+	clr	P1.BnFET
+ENDM
+MACRO CnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+ENDM
+MACRO CnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+ENDM
+MACRO All_nFETs_Off
+	clr	P1.AnFET
+	clr	P1.BnFET
+	clr	P1.CnFET
+ENDM
+
+MACRO ApFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+ENDM
+MACRO ApFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+ENDM
+MACRO BpFET_on
+	setb	P1.BpFET
+ENDM
+MACRO BpFET_off
+	clr	P1.BpFET
+ENDM
+MACRO CpFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+ENDM
+MACRO CpFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+ENDM
+MACRO All_pFETs_Off
+	clr	P1.ApFET
+	clr	P1.BpFET
+	clr	P1.CpFET
+ENDM
+MACRO All_pFETs_On
+	setb	P1.ApFET
+	setb	P1.BpFET
+	setb	P1.CpFET
+ENDM
+
+MACRO Set_Comp_Phase_A
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h	; Set comparator multiplexer to phase A
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h
+ENDM
+MACRO Set_Comp_Phase_B
+	mov	CPT0MX, #11h	; Set comparator multiplexer to phase B
+ENDM
+MACRO Set_Comp_Phase_C
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h	; Set comparator multiplexer to phase C
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h
+ENDM
+MACRO Read_Comp_Out
+	mov	A, CPT0CN		; Read comparator output
+	cpl	A			; Invert output
+ENDM
+
+
+;*********************
+; PORT B definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+MACRO Interrupt_Table_Definition
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 0Bh			; Timer0 interrupt	
+	jmp	t0_int	
+CSEG AT 2Bh			; Timer2 interrupt	
+	jmp	t2_int	
+CSEG AT 5Bh			; PCA interrupt	
+	jmp	pca_int	
+CSEG AT 73h			; Timer3 interrupt	
+	jmp	t3_int	
+ENDM
+
+MACRO Initialize_Adc
+	mov	REF0CN, #01h	; Enable reference buffer
+	mov	ADC0CF, #0B8h	; ADC clock 1MHz
+	mov	AMX0P, #Adc_Ip	; Select positive input
+	mov	AMX0N, #11h	; Select negative input as ground
+	mov	ADC0CN, #80h	; ADC enabled
+ENDM
+MACRO Start_Adc
+	mov	ADC0CN, #90h	; ADC start
+ENDM
+MACRO Get_Adc_Status
+	mov	A, ADC0CN		
+ENDM
+MACRO Read_Adc_Result
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+MACRO Stop_Adc
+ENDM

SiLabs/XP_3A.inc

@@ -0,0 +1,256 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; XP 3A hardware definition file
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs F330
+;*********************
+$include (c8051f330.inc)
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+CSEG AT 1A40h
+Eep_ESC_Layout:		DB	"#XP3A#          "	; ESC layout tag
+DAMPED_TAIL_ENABLE		EQU	1	; Damped tail mode enabled
+NFETON_DELAY			EQU	2	; Wait delay from pfets off to nfets on
+PFETON_DELAY			EQU	1	; Wait delay from nfets off to pfets on
+ADC_LIMIT_L			EQU 	171	; Power supply measurement ADC value for which main motor power is limited (low byte)
+ADC_LIMIT_H			EQU	1	; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Rcp_In		EQU	7	;i
+Adc_Ip		EQU	6	;i
+Mux_A		EQU	5	;i
+;			EQU	4	;i
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)+(1 SHL Adc_Ip))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	NOT(1 SHL Rcp_In) AND 0FFh
+
+MACRO Read_Rcp_Int
+	mov	A, P0
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+4)	; Is pwm polarity negative?
+	cpl	A						; Yes - invert
+ENDM
+MACRO Rcp_Int_Enable
+	orl	PCA0CPM0, #01h				; Interrupt enabled
+ENDM
+MACRO Rcp_Int_Disable
+	anl	PCA0CPM0, #0FEh			; Interrupt disabled
+ENDM
+MACRO Rcp_Int_First
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+ENDM
+MACRO Rcp_Int_Second
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+ENDM
+MACRO Rcp_Clear_Int_Flag
+	clr 	CCF0						; Clear interrupt flag
+ENDM		
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;o
+;			EQU	6	;o
+CpFET		EQU	5	;o
+BpFET		EQU	4	;o
+ApFET		EQU	3	;o
+CnFET		EQU	2	;o
+BnFET		EQU	1	;i
+AnFET		EQU	0	;i
+
+P1_DIGITAL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_INIT		EQU 	(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)		; Setting pFET outputs turn them off
+P1_PUSHPULL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_SKIP		EQU	0
+
+MACRO AnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+ENDM
+MACRO AnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+ENDM
+MACRO BnFET_on
+	setb	P1.BnFET
+ENDM
+MACRO BnFET_off
+	clr	P1.BnFET
+ENDM
+MACRO CnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+ENDM
+MACRO CnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+ENDM
+MACRO All_nFETs_Off
+	clr	P1.AnFET
+	clr	P1.BnFET
+	clr	P1.CnFET
+ENDM
+
+MACRO ApFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+ENDM
+MACRO ApFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+ENDM
+MACRO BpFET_on
+	clr	P1.BpFET
+ENDM
+MACRO BpFET_off
+	setb	P1.BpFET
+ENDM
+MACRO CpFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+ENDM
+MACRO CpFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+ENDM
+MACRO All_pFETs_Off
+	setb	P1.ApFET
+	setb	P1.BpFET
+	setb	P1.CpFET
+ENDM
+MACRO All_pFETs_On
+	clr	P1.ApFET
+	clr	P1.BpFET
+	clr	P1.CpFET
+ENDM
+
+MACRO Set_Comp_Phase_A
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h	; Set comparator multiplexer to phase A
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h
+ENDM
+MACRO Set_Comp_Phase_B
+	mov	CPT0MX, #11h	; Set comparator multiplexer to phase B
+ENDM
+MACRO Set_Comp_Phase_C
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h	; Set comparator multiplexer to phase C
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h
+ENDM
+MACRO Read_Comp_Out
+	mov	A, CPT0CN		; Read comparator output
+	cpl	A			; Invert output
+ENDM
+
+
+;*********************
+; PORT B definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+MACRO Interrupt_Table_Definition
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 0Bh			; Timer0 interrupt	
+	jmp	t0_int	
+CSEG AT 2Bh			; Timer2 interrupt	
+	jmp	t2_int	
+CSEG AT 5Bh			; PCA interrupt	
+	jmp	pca_int	
+CSEG AT 73h			; Timer3 interrupt	
+	jmp	t3_int	
+ENDM
+
+MACRO Initialize_Adc
+	mov	REF0CN, #01h	; Enable reference buffer
+	mov	ADC0CF, #0B8h	; ADC clock 1MHz
+	mov	AMX0P, #Adc_Ip	; Select positive input
+	mov	AMX0N, #11h	; Select negative input as ground
+	mov	ADC0CN, #80h	; ADC enabled
+ENDM
+MACRO Start_Adc
+	mov	ADC0CN, #90h	; ADC start
+ENDM
+MACRO Get_Adc_Status
+	mov	A, ADC0CN		
+ENDM
+MACRO Read_Adc_Result
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+MACRO Stop_Adc
+ENDM

SiLabs/XP_7A.inc

@@ -0,0 +1,256 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; XP 7A hardware definition file
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs F330
+;*********************
+$include (c8051f330.inc)
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+CSEG AT 1A40h
+Eep_ESC_Layout:		DB	"#XP7A#          "	; ESC layout tag
+DAMPED_TAIL_ENABLE		EQU	0	; Damped tail mode disabled
+NFETON_DELAY			EQU	22	; Wait delay from pfets off to nfets on
+PFETON_DELAY			EQU	5	; Wait delay from nfets off to pfets on
+ADC_LIMIT_L			EQU 	116	; Power supply measurement ADC value for which main motor power is limited (low byte)
+ADC_LIMIT_H			EQU	0	; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Rcp_In		EQU	7	;i
+Adc_Ip		EQU	6	;i
+Mux_A		EQU	5	;i
+;			EQU	4	;i
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)+(1 SHL Adc_Ip))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	NOT(1 SHL Rcp_In) AND 0FFh
+
+MACRO Read_Rcp_Int
+	mov	A, P0
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+4)	; Is pwm polarity negative?
+	cpl	A						; Yes - invert
+ENDM
+MACRO Rcp_Int_Enable
+	orl	PCA0CPM0, #01h				; Interrupt enabled
+ENDM
+MACRO Rcp_Int_Disable
+	anl	PCA0CPM0, #0FEh			; Interrupt disabled
+ENDM
+MACRO Rcp_Int_First
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+ENDM
+MACRO Rcp_Int_Second
+	anl	PCA0CPM0, #0CFh			
+	jb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity positive?
+	orl	PCA0CPM0, #10h				; Capture falling edge
+	jnb	Flags2.PGM_RCP_PWM_POL, ($+6)	; Is pwm polarity negative?
+	orl	PCA0CPM0, #20h				; Capture rising edge
+ENDM
+MACRO Rcp_Clear_Int_Flag
+	clr 	CCF0						; Clear interrupt flag
+ENDM		
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;o
+;			EQU	6	;o
+ApFET		EQU	5	;o
+BpFET		EQU	4	;o
+CpFET		EQU	3	;o
+AnFET		EQU	2	;o
+BnFET		EQU	1	;i
+CnFET		EQU	0	;i
+
+P1_DIGITAL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_INIT		EQU 	0		
+P1_PUSHPULL	EQU	(1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
+P1_SKIP		EQU	0
+
+MACRO AnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+ENDM
+MACRO AnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+ENDM
+MACRO BnFET_on
+	setb	P1.BnFET
+ENDM
+MACRO BnFET_off
+	clr	P1.BnFET
+ENDM
+MACRO CnFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.AnFET
+ENDM
+MACRO CnFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CnFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.AnFET
+ENDM
+MACRO All_nFETs_Off
+	clr	P1.AnFET
+	clr	P1.BnFET
+	clr	P1.CnFET
+ENDM
+
+MACRO ApFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+ENDM
+MACRO ApFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+ENDM
+MACRO BpFET_on
+	setb	P1.BpFET
+ENDM
+MACRO BpFET_off
+	clr	P1.BpFET
+ENDM
+MACRO CpFET_on
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	setb	P1.ApFET
+ENDM
+MACRO CpFET_off
+	jb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.CpFET
+	jnb	Flags2.PGM_DIRECTION_REV, ($+5)
+	clr	P1.ApFET
+ENDM
+MACRO All_pFETs_Off
+	clr	P1.ApFET
+	clr	P1.BpFET
+	clr	P1.CpFET
+ENDM
+MACRO All_pFETs_On
+	setb	P1.ApFET
+	setb	P1.BpFET
+	setb	P1.CpFET
+ENDM
+
+MACRO Set_Comp_Phase_A
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h	; Set comparator multiplexer to phase A
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h
+ENDM
+MACRO Set_Comp_Phase_B
+	mov	CPT0MX, #11h	; Set comparator multiplexer to phase B
+ENDM
+MACRO Set_Comp_Phase_C
+	jb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #01h	; Set comparator multiplexer to phase C
+	jnb	Flags2.PGM_DIRECTION_REV, ($+6)
+	mov	CPT0MX, #21h
+ENDM
+MACRO Read_Comp_Out
+	mov	A, CPT0CN		; Read comparator output
+	cpl	A			; Invert output
+ENDM
+
+
+;*********************
+; PORT B definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+MACRO Interrupt_Table_Definition
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 0Bh			; Timer0 interrupt	
+	jmp	t0_int	
+CSEG AT 2Bh			; Timer2 interrupt	
+	jmp	t2_int	
+CSEG AT 5Bh			; PCA interrupt	
+	jmp	pca_int	
+CSEG AT 73h			; Timer3 interrupt	
+	jmp	t3_int	
+ENDM
+
+MACRO Initialize_Adc
+	mov	REF0CN, #01h	; Enable reference buffer
+	mov	ADC0CF, #0B8h	; ADC clock 1MHz
+	mov	AMX0P, #Adc_Ip	; Select positive input
+	mov	AMX0N, #11h	; Select negative input as ground
+	mov	ADC0CN, #80h	; ADC enabled
+ENDM
+MACRO Start_Adc
+	mov	ADC0CN, #90h	; ADC start
+ENDM
+MACRO Get_Adc_Status
+	mov	A, ADC0CN		
+ENDM
+MACRO Read_Adc_Result
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+MACRO Stop_Adc
+ENDM