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431 lines
22 KiB
431 lines
22 KiB
;------------------------------------------------------------------------------
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; Copyright 2014 Silicon Laboratories, Inc.
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; All rights reserved. This program and the accompanying materials
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; are made available under the terms of the Silicon Laboratories End User
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; License Agreement which accompanies this distribution, and is available at
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; http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt
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; Original content and implementation provided by Silicon Laboratories.
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;------------------------------------------------------------------------------
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;Supported Devices:
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; EFM8BB21F16G_QFN20
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; EFM8BB21F16G_QSOP24
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; EFM8BB21F16I_QFN20
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; EFM8BB21F16I_QSOP24
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; EFM8BB22F16G_QFN28
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; EFM8BB22F16I_QFN28
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;-----------------------------------------------------------------------------
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; Register Definitions
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;-----------------------------------------------------------------------------
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ACC DATA 0E0H; Accumulator
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ADC0AC DATA 0B3H; ADC0 Accumulator Configuration
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ADC0CF DATA 0BCH; ADC0 Configuration
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ADC0CN0 DATA 0E8H; ADC0 Control 0
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ADC0CN1 DATA 0B2H; ADC0 Control 1
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ADC0GTH DATA 0C4H; ADC0 Greater-Than High Byte
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ADC0GTL DATA 0C3H; ADC0 Greater-Than Low Byte
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ADC0H DATA 0BEH; ADC0 Data Word High Byte
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ADC0L DATA 0BDH; ADC0 Data Word Low Byte
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ADC0LTH DATA 0C6H; ADC0 Less-Than High Byte
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ADC0LTL DATA 0C5H; ADC0 Less-Than Low Byte
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ADC0MX DATA 0BBH; ADC0 Multiplexer Selection
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ADC0PWR DATA 0DFH; ADC0 Power Control
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ADC0TK DATA 0B9H; ADC0 Burst Mode Track Time
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B DATA 0F0H; B Register
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CKCON0 DATA 08EH; Clock Control 0
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CKCON1 DATA 0A6H; Clock Control 1
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CLKSEL DATA 0A9H; Clock Select
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CMP0CN0 DATA 09BH; Comparator 0 Control 0
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CMP0CN1 DATA 099H; Comparator 0 Control 1
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CMP0MD DATA 09DH; Comparator 0 Mode
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CMP0MX DATA 09FH; Comparator 0 Multiplexer Selection
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CMP1CN0 DATA 0BFH; Comparator 1 Control 0
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CMP1CN1 DATA 0ACH; Comparator 1 Control 1
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CMP1MD DATA 0ABH; Comparator 1 Mode
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CMP1MX DATA 0AAH; Comparator 1 Multiplexer Selection
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CRC0CN0 DATA 0CEH; CRC0 Control 0
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CRC0CN1 DATA 086H; CRC0 Control 1
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CRC0CNT DATA 0D3H; CRC0 Automatic Flash Sector Count
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CRC0DAT DATA 0DEH; CRC0 Data Output
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CRC0FLIP DATA 0CFH; CRC0 Bit Flip
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CRC0IN DATA 0DDH; CRC0 Data Input
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CRC0ST DATA 0D2H; CRC0 Automatic Flash Sector Start
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DERIVID DATA 0ADH; Derivative Identification
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DEVICEID DATA 0B5H; Device Identification
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DPH DATA 083H; Data Pointer High
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DPL DATA 082H; Data Pointer Low
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EIE1 DATA 0E6H; Extended Interrupt Enable 1
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EIE2 DATA 0CEH; Extended Interrupt Enable 2
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EIP1 DATA 0F3H; Extended Interrupt Priority 1 Low
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EIP1H DATA 0F5H; Extended Interrupt Priority 1 High
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EIP2 DATA 0F4H; Extended Interrupt Priority 2
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EIP2H DATA 0F6H; Extended Interrupt Priority 2 High
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EMI0CN DATA 0E7H; External Memory Interface Control
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FLKEY DATA 0B7H; Flash Lock and Key
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HFO0CAL DATA 0C7H; High Frequency Oscillator 0 Calibration
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HFO1CAL DATA 0D6H; High Frequency Oscillator 1 Calibration
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HFOCN DATA 0EFH; High Frequency Oscillator Control
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I2C0CN0 DATA 0BAH; I2C0 Control
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I2C0DIN DATA 0BCH; I2C0 Received Data
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I2C0DOUT DATA 0BBH; I2C0 Transmit Data
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I2C0FCN0 DATA 0ADH; I2C0 FIFO Control 0
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I2C0FCN1 DATA 0ABH; I2C0 FIFO Control 1
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I2C0FCT DATA 0F5H; I2C0 FIFO Count
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I2C0SLAD DATA 0BDH; I2C0 Slave Address
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I2C0STAT DATA 0B9H; I2C0 Status
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IE DATA 0A8H; Interrupt Enable
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IP DATA 0B8H; Interrupt Priority
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IPH DATA 0F2H; Interrupt Priority High
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IT01CF DATA 0E4H; INT0/INT1 Configuration
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LFO0CN DATA 0B1H; Low Frequency Oscillator Control
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P0 DATA 080H; Port 0 Pin Latch
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P0MASK DATA 0FEH; Port 0 Mask
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P0MAT DATA 0FDH; Port 0 Match
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P0MDIN DATA 0F1H; Port 0 Input Mode
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P0MDOUT DATA 0A4H; Port 0 Output Mode
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P0SKIP DATA 0D4H; Port 0 Skip
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P1 DATA 090H; Port 1 Pin Latch
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P1MASK DATA 0EEH; Port 1 Mask
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P1MAT DATA 0EDH; Port 1 Match
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P1MDIN DATA 0F2H; Port 1 Input Mode
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P1MDOUT DATA 0A5H; Port 1 Output Mode
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P1SKIP DATA 0D5H; Port 1 Skip
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P2 DATA 0A0H; Port 2 Pin Latch
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P2MASK DATA 0FCH; Port 2 Mask
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P2MAT DATA 0FBH; Port 2 Match
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P2MDIN DATA 0F3H; Port 2 Input Mode
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P2MDOUT DATA 0A6H; Port 2 Output Mode
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P2SKIP DATA 0CCH; Port 2 Skip
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P3 DATA 0B0H; Port 3 Pin Latch
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P3MDIN DATA 0F4H; Port 3 Input Mode
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P3MDOUT DATA 09CH; Port 3 Output Mode
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PCA0CENT DATA 09EH; PCA Center Alignment Enable
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PCA0CLR DATA 09CH; PCA Comparator Clear Control
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PCA0CN0 DATA 0D8H; PCA Control
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PCA0CPH0 DATA 0FCH; PCA Channel 0 Capture Module High Byte
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PCA0CPH1 DATA 0EAH; PCA Channel 1 Capture Module High Byte
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PCA0CPH2 DATA 0ECH; PCA Channel 2 Capture Module High Byte
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PCA0CPL0 DATA 0FBH; PCA Channel 0 Capture Module Low Byte
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PCA0CPL1 DATA 0E9H; PCA Channel 1 Capture Module Low Byte
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PCA0CPL2 DATA 0EBH; PCA Channel 2 Capture Module Low Byte
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PCA0CPM0 DATA 0DAH; PCA Channel 0 Capture/Compare Mode
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PCA0CPM1 DATA 0DBH; PCA Channel 1 Capture/Compare Mode
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PCA0CPM2 DATA 0DCH; PCA Channel 2 Capture/Compare Mode
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PCA0H DATA 0FAH; PCA Counter/Timer High Byte
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PCA0L DATA 0F9H; PCA Counter/Timer Low Byte
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PCA0MD DATA 0D9H; PCA Mode
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PCA0POL DATA 096H; PCA Output Polarity
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PCA0PWM DATA 0F7H; PCA PWM Configuration
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PCON0 DATA 087H; Power Control
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PCON1 DATA 09AH; Power Control 1
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PFE0CN DATA 0C1H; Prefetch Engine Control
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PRTDRV DATA 0F6H; Port Drive Strength
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PSCTL DATA 08FH; Program Store Control
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PSW DATA 0D0H; Program Status Word
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REF0CN DATA 0D1H; Voltage Reference Control
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REG0CN DATA 0C9H; Voltage Regulator 0 Control
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REG1CN DATA 0C6H; Voltage Regulator 1 Control
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REVID DATA 0B6H; Revision Identifcation
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RSTSRC DATA 0EFH; Reset Source
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SBCON1 DATA 094H; UART1 Baud Rate Generator Control
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SBRLH1 DATA 096H; UART1 Baud Rate Generator High Byte
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SBRLL1 DATA 095H; UART1 Baud Rate Generator Low Byte
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SBUF0 DATA 099H; UART0 Serial Port Data Buffer
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SBUF1 DATA 092H; UART1 Serial Port Data Buffer
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SCON0 DATA 098H; UART0 Serial Port Control
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SCON1 DATA 0C8H; UART1 Serial Port Control
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SFRPAGE DATA 0A7H; SFR Page
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SFRPGCN DATA 0CFH; SFR Page Control
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SFRSTACK DATA 0D7H; SFR Page Stack
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SMB0ADM DATA 0D6H; SMBus 0 Slave Address Mask
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SMB0ADR DATA 0D7H; SMBus 0 Slave Address
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SMB0CF DATA 0C1H; SMBus 0 Configuration
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SMB0CN0 DATA 0C0H; SMBus 0 Control
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SMB0DAT DATA 0C2H; SMBus 0 Data
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SMB0FCN0 DATA 0C3H; SMBus 0 FIFO Control 0
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SMB0FCN1 DATA 0C4H; SMBus 0 FIFO Control 1
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SMB0FCT DATA 0EFH; SMBus 0 FIFO Count
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SMB0RXLN DATA 0C5H; SMBus 0 Receive Length Counter
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SMB0TC DATA 0ACH; SMBus 0 Timing and Pin Control
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SMOD1 DATA 093H; UART1 Mode
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SP DATA 081H; Stack Pointer
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SPI0CFG DATA 0A1H; SPI0 Configuration
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SPI0CKR DATA 0A2H; SPI0 Clock Rate
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SPI0CN0 DATA 0F8H; SPI0 Control
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SPI0DAT DATA 0A3H; SPI0 Data
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SPI0FCN0 DATA 09AH; SPI0 FIFO Control 0
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SPI0FCN1 DATA 09BH; SPI0 FIFO Control 1
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SPI0FCT DATA 0F7H; SPI0 FIFO Count
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TCON DATA 088H; Timer 0/1 Control
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TH0 DATA 08CH; Timer 0 High Byte
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TH1 DATA 08DH; Timer 1 High Byte
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TL0 DATA 08AH; Timer 0 Low Byte
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TL1 DATA 08BH; Timer 1 Low Byte
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TMOD DATA 089H; Timer 0/1 Mode
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TMR2CN0 DATA 0C8H; Timer 2 Control 0
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TMR2CN1 DATA 0FDH; Timer 2 Control 1
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TMR2H DATA 0CDH; Timer 2 High Byte
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TMR2L DATA 0CCH; Timer 2 Low Byte
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TMR2RLH DATA 0CBH; Timer 2 Reload High Byte
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TMR2RLL DATA 0CAH; Timer 2 Reload Low Byte
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TMR3CN0 DATA 091H; Timer 3 Control 0
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TMR3CN1 DATA 0FEH; Timer 3 Control 1
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TMR3H DATA 095H; Timer 3 High Byte
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TMR3L DATA 094H; Timer 3 Low Byte
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TMR3RLH DATA 093H; Timer 3 Reload High Byte
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TMR3RLL DATA 092H; Timer 3 Reload Low Byte
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TMR4CN0 DATA 098H; Timer 4 Control 0
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TMR4CN1 DATA 0FFH; Timer 4 Control 1
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TMR4H DATA 0A5H; Timer 4 High Byte
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TMR4L DATA 0A4H; Timer 4 Low Byte
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TMR4RLH DATA 0A3H; Timer 4 Reload High Byte
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TMR4RLL DATA 0A2H; Timer 4 Reload Low Byte
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UART1FCN0 DATA 09DH; UART1 FIFO Control 0
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UART1FCN1 DATA 0D8H; UART1 FIFO Control 1
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UART1FCT DATA 0FAH; UART1 FIFO Count
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UART1LIN DATA 09EH; UART1 LIN Configuration
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VDM0CN DATA 0FFH; Supply Monitor Control
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WDTCN DATA 097H; Watchdog Timer Control
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XBR0 DATA 0E1H; Port I/O Crossbar 0
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XBR1 DATA 0E2H; Port I/O Crossbar 1
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XBR2 DATA 0E3H; Port I/O Crossbar 2
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;------------------------------------------------------------------------------
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; 16-bit Register Definitions (may not work on all compilers)
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;------------------------------------------------------------------------------
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ADC0GT DATA 0C3H ; ADC0 Greater-Than Low Byte
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ADC0 DATA 0BDH ; ADC0 Data Word Low Byte
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ADC0LT DATA 0C5H ; ADC0 Less-Than Low Byte
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DP DATA 082H ; Data Pointer Low
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PCA0CP0 DATA 0FBH ; PCA Channel 0 Capture Module Low Byte
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PCA0CP1 DATA 0E9H ; PCA Channel 1 Capture Module Low Byte
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PCA0CP2 DATA 0EBH ; PCA Channel 2 Capture Module Low Byte
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PCA0 DATA 0F9H ; PCA Counter/Timer Low Byte
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SBRL1 DATA 095H ; UART1 Baud Rate Generator Low Byte
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TMR2 DATA 0CCH ; Timer 2 Low Byte
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TMR2RL DATA 0CAH ; Timer 2 Reload Low Byte
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TMR3 DATA 094H ; Timer 3 Low Byte
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TMR3RL DATA 092H ; Timer 3 Reload Low Byte
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TMR4 DATA 0A4H ; Timer 4 Low Byte
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TMR4RL DATA 0A2H ; Timer 4 Reload Low Byte
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;------------------------------------------------------------------------------
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; Indirect Register Definitions
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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; Bit Definitions
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;------------------------------------------------------------------------------
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; ACC 0xE0 (Accumulator)
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ACC_ACC0 BIT ACC.0 ; Accumulator Bit 0
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ACC_ACC1 BIT ACC.1 ; Accumulator Bit 1
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ACC_ACC2 BIT ACC.2 ; Accumulator Bit 2
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ACC_ACC3 BIT ACC.3 ; Accumulator Bit 3
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ACC_ACC4 BIT ACC.4 ; Accumulator Bit 4
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ACC_ACC5 BIT ACC.5 ; Accumulator Bit 5
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ACC_ACC6 BIT ACC.6 ; Accumulator Bit 6
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ACC_ACC7 BIT ACC.7 ; Accumulator Bit 7
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; ADC0CN0 0xE8 (ADC0 Control 0)
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ADC0CN0_ADCM0 BIT ADC0CN0.0 ; Start of Conversion Mode Select Bit 0
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ADC0CN0_ADCM1 BIT ADC0CN0.1 ; Start of Conversion Mode Select Bit 1
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ADC0CN0_ADCM2 BIT ADC0CN0.2 ; Start of Conversion Mode Select Bit 2
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ADC0CN0_ADWINT BIT ADC0CN0.3 ; Window Compare Interrupt Flag
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ADC0CN0_ADBUSY BIT ADC0CN0.4 ; ADC Busy
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ADC0CN0_ADINT BIT ADC0CN0.5 ; Conversion Complete Interrupt Flag
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ADC0CN0_ADBMEN BIT ADC0CN0.6 ; Burst Mode Enable
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ADC0CN0_ADEN BIT ADC0CN0.7 ; ADC Enable
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; B 0xF0 (B Register)
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B_B0 BIT B.0 ; B Register Bit 0
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B_B1 BIT B.1 ; B Register Bit 1
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B_B2 BIT B.2 ; B Register Bit 2
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B_B3 BIT B.3 ; B Register Bit 3
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B_B4 BIT B.4 ; B Register Bit 4
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B_B5 BIT B.5 ; B Register Bit 5
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B_B6 BIT B.6 ; B Register Bit 6
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B_B7 BIT B.7 ; B Register Bit 7
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; IE 0xA8 (Interrupt Enable)
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IE_EX0 BIT IE.0 ; External Interrupt 0 Enable
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IE_ET0 BIT IE.1 ; Timer 0 Interrupt Enable
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IE_EX1 BIT IE.2 ; External Interrupt 1 Enable
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IE_ET1 BIT IE.3 ; Timer 1 Interrupt Enable
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IE_ES0 BIT IE.4 ; UART0 Interrupt Enable
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IE_ET2 BIT IE.5 ; Timer 2 Interrupt Enable
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IE_ESPI0 BIT IE.6 ; SPI0 Interrupt Enable
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IE_EA BIT IE.7 ; All Interrupts Enable
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; IP 0xB8 (Interrupt Priority)
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IP_PX0 BIT IP.0 ; External Interrupt 0 Priority Control LSB
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IP_PT0 BIT IP.1 ; Timer 0 Interrupt Priority Control LSB
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IP_PX1 BIT IP.2 ; External Interrupt 1 Priority Control LSB
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IP_PT1 BIT IP.3 ; Timer 1 Interrupt Priority Control LSB
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IP_PS0 BIT IP.4 ; UART0 Interrupt Priority Control LSB
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IP_PT2 BIT IP.5 ; Timer 2 Interrupt Priority Control LSB
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IP_PSPI0 BIT IP.6 ; Serial Peripheral Interface (SPI0) Interrupt Priority Control LSB
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; P0 0x80 (Port 0 Pin Latch)
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P0_B0 BIT P0.0 ; Port 0 Bit 0 Latch
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P0_B1 BIT P0.1 ; Port 0 Bit 1 Latch
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P0_B2 BIT P0.2 ; Port 0 Bit 2 Latch
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P0_B3 BIT P0.3 ; Port 0 Bit 3 Latch
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P0_B4 BIT P0.4 ; Port 0 Bit 4 Latch
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P0_B5 BIT P0.5 ; Port 0 Bit 5 Latch
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P0_B6 BIT P0.6 ; Port 0 Bit 6 Latch
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P0_B7 BIT P0.7 ; Port 0 Bit 7 Latch
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; P1 0x90 (Port 1 Pin Latch)
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P1_B0 BIT P1.0 ; Port 1 Bit 0 Latch
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P1_B1 BIT P1.1 ; Port 1 Bit 1 Latch
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P1_B2 BIT P1.2 ; Port 1 Bit 2 Latch
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P1_B3 BIT P1.3 ; Port 1 Bit 3 Latch
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P1_B4 BIT P1.4 ; Port 1 Bit 4 Latch
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P1_B5 BIT P1.5 ; Port 1 Bit 5 Latch
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P1_B6 BIT P1.6 ; Port 1 Bit 6 Latch
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P1_B7 BIT P1.7 ; Port 1 Bit 7 Latch
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; P2 0xA0 (Port 2 Pin Latch)
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P2_B0 BIT P2.0 ; Port 2 Bit 0 Latch
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P2_B1 BIT P2.1 ; Port 2 Bit 1 Latch
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P2_B2 BIT P2.2 ; Port 2 Bit 2 Latch
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P2_B3 BIT P2.3 ; Port 2 Bit 3 Latch
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; P3 0xB0 (Port 3 Pin Latch)
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P3_B0 BIT P3.0 ; Port 3 Bit 0 Latch
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P3_B1 BIT P3.1 ; Port 3 Bit 1 Latch
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; PCA0CN0 0xD8 (PCA Control)
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PCA0CN0_CCF0 BIT PCA0CN0.0 ; PCA Module 0 Capture/Compare Flag
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PCA0CN0_CCF1 BIT PCA0CN0.1 ; PCA Module 1 Capture/Compare Flag
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PCA0CN0_CCF2 BIT PCA0CN0.2 ; PCA Module 2 Capture/Compare Flag
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PCA0CN0_CR BIT PCA0CN0.6 ; PCA Counter/Timer Run Control
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PCA0CN0_CF BIT PCA0CN0.7 ; PCA Counter/Timer Overflow Flag
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; PSW 0xD0 (Program Status Word)
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PSW_PARITY BIT PSW.0 ; Parity Flag
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PSW_F1 BIT PSW.1 ; User Flag 1
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PSW_OV BIT PSW.2 ; Overflow Flag
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PSW_RS0 BIT PSW.3 ; Register Bank Select Bit 0
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PSW_RS1 BIT PSW.4 ; Register Bank Select Bit 1
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PSW_F0 BIT PSW.5 ; User Flag 0
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PSW_AC BIT PSW.6 ; Auxiliary Carry Flag
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PSW_CY BIT PSW.7 ; Carry Flag
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; SCON0 0x98 (UART0 Serial Port Control)
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SCON0_RI BIT SCON0.0 ; Receive Interrupt Flag
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SCON0_TI BIT SCON0.1 ; Transmit Interrupt Flag
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SCON0_RB8 BIT SCON0.2 ; Ninth Receive Bit
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SCON0_TB8 BIT SCON0.3 ; Ninth Transmission Bit
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SCON0_REN BIT SCON0.4 ; Receive Enable
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SCON0_MCE BIT SCON0.5 ; Multiprocessor Communication Enable
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SCON0_SMODE BIT SCON0.7 ; Serial Port 0 Operation Mode
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; SCON1 0xC8 (UART1 Serial Port Control)
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SCON1_RI BIT SCON1.0 ; Receive Interrupt Flag
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SCON1_TI BIT SCON1.1 ; Transmit Interrupt Flag
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SCON1_RBX BIT SCON1.2 ; Extra Receive Bit
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SCON1_TBX BIT SCON1.3 ; Extra Transmission Bit
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SCON1_REN BIT SCON1.4 ; Receive Enable
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SCON1_PERR BIT SCON1.6 ; Parity Error Flag
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SCON1_OVR BIT SCON1.7 ; Receive FIFO Overrun Flag
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; SMB0CN0 0xC0 (SMBus 0 Control)
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SMB0CN0_SI BIT SMB0CN0.0 ; SMBus Interrupt Flag
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SMB0CN0_ACK BIT SMB0CN0.1 ; SMBus Acknowledge
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SMB0CN0_ARBLOST BIT SMB0CN0.2 ; SMBus Arbitration Lost Indicator
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SMB0CN0_ACKRQ BIT SMB0CN0.3 ; SMBus Acknowledge Request
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SMB0CN0_STO BIT SMB0CN0.4 ; SMBus Stop Flag
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SMB0CN0_STA BIT SMB0CN0.5 ; SMBus Start Flag
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SMB0CN0_TXMODE BIT SMB0CN0.6 ; SMBus Transmit Mode Indicator
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SMB0CN0_MASTER BIT SMB0CN0.7 ; SMBus Master/Slave Indicator
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; SPI0CN0 0xF8 (SPI0 Control)
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SPI0CN0_SPIEN BIT SPI0CN0.0 ; SPI0 Enable
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SPI0CN0_TXNF BIT SPI0CN0.1 ; TX FIFO Not Full
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SPI0CN0_NSSMD0 BIT SPI0CN0.2 ; Slave Select Mode Bit 0
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SPI0CN0_NSSMD1 BIT SPI0CN0.3 ; Slave Select Mode Bit 1
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SPI0CN0_RXOVRN BIT SPI0CN0.4 ; Receive Overrun Flag
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SPI0CN0_MODF BIT SPI0CN0.5 ; Mode Fault Flag
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SPI0CN0_WCOL BIT SPI0CN0.6 ; Write Collision Flag
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SPI0CN0_SPIF BIT SPI0CN0.7 ; SPI0 Interrupt Flag
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; TCON 0x88 (Timer 0/1 Control)
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TCON_IT0 BIT TCON.0 ; Interrupt 0 Type Select
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TCON_IE0 BIT TCON.1 ; External Interrupt 0
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TCON_IT1 BIT TCON.2 ; Interrupt 1 Type Select
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TCON_IE1 BIT TCON.3 ; External Interrupt 1
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TCON_TR0 BIT TCON.4 ; Timer 0 Run Control
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TCON_TF0 BIT TCON.5 ; Timer 0 Overflow Flag
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TCON_TR1 BIT TCON.6 ; Timer 1 Run Control
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TCON_TF1 BIT TCON.7 ; Timer 1 Overflow Flag
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; TMR2CN0 0xC8 (Timer 2 Control 0)
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TMR2CN0_T2XCLK0 BIT TMR2CN0.0 ; Timer 2 External Clock Select Bit 0
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TMR2CN0_T2XCLK1 BIT TMR2CN0.1 ; Timer 2 External Clock Select Bit 1
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TMR2CN0_TR2 BIT TMR2CN0.2 ; Timer 2 Run Control
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TMR2CN0_T2SPLIT BIT TMR2CN0.3 ; Timer 2 Split Mode Enable
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TMR2CN0_TF2CEN BIT TMR2CN0.4 ; Timer 2 Capture Enable
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TMR2CN0_TF2LEN BIT TMR2CN0.5 ; Timer 2 Low Byte Interrupt Enable
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TMR2CN0_TF2L BIT TMR2CN0.6 ; Timer 2 Low Byte Overflow Flag
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TMR2CN0_TF2H BIT TMR2CN0.7 ; Timer 2 High Byte Overflow Flag
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; TMR4CN0 0x98 (Timer 4 Control 0)
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TMR4CN0_T4XCLK0 BIT TMR4CN0.0 ; Timer 4 External Clock Select Bit 0
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TMR4CN0_T4XCLK1 BIT TMR4CN0.1 ; Timer 4 External Clock Select Bit 1
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TMR4CN0_TR4 BIT TMR4CN0.2 ; Timer 4 Run Control
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TMR4CN0_T4SPLIT BIT TMR4CN0.3 ; Timer 4 Split Mode Enable
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TMR4CN0_TF4CEN BIT TMR4CN0.4 ; Timer 4 Capture Enable
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TMR4CN0_TF4LEN BIT TMR4CN0.5 ; Timer 4 Low Byte Interrupt Enable
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TMR4CN0_TF4L BIT TMR4CN0.6 ; Timer 4 Low Byte Overflow Flag
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TMR4CN0_TF4H BIT TMR4CN0.7 ; Timer 4 High Byte Overflow Flag
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; UART1FCN1 0xD8 (UART1 FIFO Control 1)
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UART1FCN1_RIE BIT UART1FCN1.0 ; Receive Interrupt Enable
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UART1FCN1_RXTO0 BIT UART1FCN1.1 ; Receive Timeout Bit 0
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UART1FCN1_RXTO1 BIT UART1FCN1.2 ; Receive Timeout Bit 1
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UART1FCN1_RFRQ BIT UART1FCN1.3 ; Receive FIFO Request
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UART1FCN1_TIE BIT UART1FCN1.4 ; Transmit Interrupt Enable
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UART1FCN1_TXHOLD BIT UART1FCN1.5 ; Transmit Hold
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UART1FCN1_TXNF BIT UART1FCN1.6 ; TX FIFO Not Full
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UART1FCN1_TFRQ BIT UART1FCN1.7 ; Transmit FIFO Request
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;------------------------------------------------------------------------------
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; Interrupt Definitions
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;------------------------------------------------------------------------------
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INT0_IRQn EQU 0 ; External Interrupt 0
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TIMER0_IRQn EQU 1 ; Timer 0 Overflow
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INT1_IRQn EQU 2 ; External Interrupt 1
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TIMER1_IRQn EQU 3 ; Timer 1 Overflow
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UART0_IRQn EQU 4 ; UART0
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TIMER2_IRQn EQU 5 ; Timer 2 Overflow / Capture
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SPI0_IRQn EQU 6 ; SPI0
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SMBUS0_IRQn EQU 7 ; SMBus 0
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PMATCH_IRQn EQU 8 ; Port Match
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ADC0WC_IRQn EQU 9 ; ADC0 Window Compare
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ADC0EOC_IRQn EQU 10 ; ADC0 End of Conversion
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PCA0_IRQn EQU 11 ; PCA0
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CMP0_IRQn EQU 12 ; Comparator 0
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CMP1_IRQn EQU 13 ; Comparator 1
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TIMER3_IRQn EQU 14 ; Timer 3 Overflow / Capture
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UART1_IRQn EQU 17 ; UART1
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I2C0_IRQn EQU 18 ; I2C0 Slave
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TIMER4_IRQn EQU 19 ; Timer 4 Overflow / Capture
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;------------------------------------------------------------------------------
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; SFR Page Definitions
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;------------------------------------------------------------------------------
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CRC0_PAGE EQU 000H ; CRC0 Page
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LEGACY_PAGE EQU 000H ; Legacy SFR Page
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PCA0_PAGE EQU 000H ; PCA0 Page
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PG2_PAGE EQU 010H ; Page2
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TIMER2_PAGE EQU 010H ; Timer 2 Page
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TIMER3_PAGE EQU 010H ; Timer 3 Page
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TIMER4_PAGE EQU 010H ; Timer 4 Page
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I2CSLAVE0_PAGE EQU 020H ; I2C Slave 0 Page
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PG3_PAGE EQU 020H ; Page3
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SMB0_PAGE EQU 020H ; SMBus 0 Page
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SPI0_PAGE EQU 020H ; SPI0 Page
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UART0_PAGE EQU 020H ; UART0 Page
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UART1_PAGE EQU 020H ; UART1 Page
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