BLHeli_S source code

A.inc

@@ -0,0 +1,553 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "A"
+; X  X  RC X  MC MB MA CC    X  X  Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#A_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#A_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#A_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#A_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#A_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#A_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#A_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#A_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#A_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#A_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#A_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#A_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#A_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#A_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#A_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#A_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#A_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#A_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#A_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#A_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#A_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#A_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_A		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CcomFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+BcomFET		EQU	3	;o
+BpwmFET		EQU	2	;o
+AcomFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

B.inc

@@ -0,0 +1,558 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "B". Equals "A", but with A and C fets swapped and pwm and com fets swapped
+; X  X  RC X  MC MB MA CC    X  X  Ap Ac Bp Bc Cp Cc
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#B_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#B_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#B_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#B_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#B_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#B_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#B_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#B_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#B_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#B_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#B_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#B_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#B_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#B_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#B_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#B_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#B_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#B_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#B_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#B_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#B_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#B_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_A		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+ApwmFET		EQU	5	;o
+AcomFET		EQU	4	;o
+BpwmFET		EQU	3	;o
+BcomFET		EQU	2	;o
+CpwmFET		EQU	1	;o
+CcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #1Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #37h
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

BLHeliBootLoad.inc

@@ -0,0 +1,385 @@
+; BLHeli bootloader for SiLabs MCUs. Based upon AVRootloader (copyright HR)
+
+XTAL					EQU	25000000
+
+BOOT_START			EQU	1C00h	; Bootloader segment address
+BOOT_DELAY			EQU	XTAL/4	; About 250ms (don't set to fast to avoid connection problems)
+BOOT_BAUDRATE			EQU	19200	; Only used if no baudrate detection activated, XTAL is than important
+BOOT_VERSION			EQU	6		; Version 6 (must be not changed)
+BOOT_PAGES			EQU	1		; Number of flash segments for bootloader
+
+UART_LOOP				EQU	26		; Depends upon timing of putc, getc
+BAUDTIME				EQU	((XTAL/BOOT_BAUDRATE)/3)-UART_LOOP
+
+SUCCESS				EQU	030h
+ERRORVERIFY			EQU	0C0h
+ERRORCOMMAND			EQU	0C1h
+ERRORCRC				EQU	0C2h
+ERRORPROG				EQU	0C5h
+
+POLYNOM				EQU	0A001h	; CRC Polynom
+
+Xl					EQU	R0		; Temporary X
+Xh					EQU	R1
+Paral				EQU	R2		; Params for UART
+Parah				EQU	R3
+Cmdl					EQU	R4		; Commands
+Cmdh					EQU	R5
+Cntl					EQU	R6		; Baudtime
+Cnth					EQU	R7
+
+DSEG AT 20h
+Bit_Reg:				DS	1		; Bit storage register
+Byte_Reg:				DS	1		; Byte storage register
+Crcl:				DS	1		; CRC 16Bit
+Crch:				DS	1
+Baudl:				DS	1		; Baudtime
+Baudh:				DS	1
+Bit_Cnt:				DS	1		; Counter in UART loops
+Byte_Cntl:			DS	1		; Generic counter
+Byte_Cnth:			DS	1
+BL_Flash_Key_1:		DS	1		; Flash keys
+BL_Flash_Key_2:		DS	1
+
+CSEG AT BOOT_START		; Bootloader start
+init:clr	IE_EA
+	; Select register bank 0 for main program routines
+	clr	PSW.3				; Select register bank 0 for main program routines
+	; Disable the WDT.
+	mov	WDTCN, #0DEh			; Disable watchdog
+	mov	WDTCN, #0ADh
+	; Initialize stack
+	mov	SP, #0c0h				; Stack = 64 upper bytes of RAM
+	; Initialize clock
+	mov	CLKSEL, #00h			; Set clock divider to 1
+	; Initialize VDD monitor
+	orl	VDM0CN, #080h			; Enable the VDD monitor
+	mov	Baudl, #38h			; Wait 100us
+	mov	Baudh, #03h
+	acall waitf
+	; Initialize flash keys
+	mov	BL_Flash_Key_1, #0A5h	; First key code
+	mov	BL_Flash_Key_2, #0F1h	; Second key code
+	; Initialize ports
+	orl	RTX_MDIN, #(1 SHL RTX_PIN)		; Set digital
+	anl	RTX_MDOUT, #NOT(1 SHL RTX_PIN)	; Disable pushpull
+	setb	RTX_PORT.RTX_PIN				; Set data high
+	mov	RTX_SKIP, #0FFh
+	mov	XBR2, #40h;					; Enable crossbar
+	; Set number of connect attempts before exiting bootloader
+	mov	Cmdh, #250
+
+	; Identifier scanning
+abd:	mov	Xl, #(low(BOOT_DELAY / 6)+1)
+	mov	Xh, #(high(BOOT_DELAY / 6)+1)
+	mov	Cmdl, #(high((BOOT_DELAY / 6) SHR 8)+1)
+	mov	Crcl, #0
+	mov	Crch, #0
+	mov	DPTR, #BOOT_SIGN
+	mov	Parah, #(BOOT_MSG - BOOT_SIGN)
+	mov	Baudl, #low(BAUDTIME)
+	mov	Baudh, #high(BAUDTIME)
+
+wait_for_low:
+	jnb	RTX_PORT.RTX_PIN, ($+5)
+	ajmp wait_for_low
+
+	; Identifier (BOOT_SIGN) scanning with timeout and checksum
+id1:	jb	RTX_PORT.RTX_PIN, id3	; Look for high
+	djnz	Xl, id1				; Subtract 1 from X (BOOT_DELAY)
+	djnz	Xh, id1
+	djnz	Cmdl, id1
+
+	ajmp	exit
+
+id3:	jnb	RTX_PORT.RTX_PIN, id4	; Look for low
+	djnz	Xl, id3				; Subtract 1 from X (BOOT_DELAY)
+	djnz	Xh, id3
+	djnz	Cmdl, id3
+
+	ajmp	exit
+
+id4:	acall getx				; Read character
+	clr	A
+	movc A, @A+DPTR			; Load BOOT_SIGN character
+	inc	DPTR
+	clr	C
+	subb	A, Paral				; Compare with read character
+	jz	id5
+	djnz	Cmdh, abd				; Retry if not last connect attempt
+	ajmp	exit
+
+id5:
+	djnz	Parah, id1
+
+	acall getw				; Read CRC
+	jz	($+4)				; Check CRC
+	ajmp	abd
+
+	; Send info about chip/bootloader (BOOT_MSG + BOOT_INFO)
+	mov	Parah, #((BOOT_INFO - BOOT_MSG) + 4)
+in1:	clr	A
+	movc A, @A+DPTR			; Load character
+	mov	Paral, A
+	inc	DPTR
+	acall putc
+	djnz	Parah, in1
+
+
+	; Main commandloop
+	; 0=Run/restart
+	; 1=Program flash, 2=Erase flash, 3=Read flash
+	; 0xFF=Set address, 0xFE=Set buffer, 0xFD=Keep alive
+main:mov	Paral, #SUCCESS
+mai1:acall putc
+	mov	Crcl, #0				; Reset CRC
+	mov	Crch, #0
+	acall getw				; Get command
+	mov	A, Paral
+	mov	Cmdl, A
+	mov	A, Parah
+	mov	Cmdh, A
+	clr	C
+	mov	A, Cmdh
+	subb	A, #0FEh
+	jc	mai2					; Jump if not set address or set buffer
+
+	acall getw				; Address or number of bytes
+	mov	Byte_Cntl, Paral		; Store number of bytes for set buffer
+	mov	Byte_Cnth, Parah
+	mov	A, Cmdh
+	jnb	ACC.0, mai2			; Jump if set buffer
+
+	mov	DPL, Paral			; Store flash address (for set address)
+	mov	DPH, Parah
+
+mai2:acall getw				; Get CRC
+	mov	Paral, #ERRORCRC
+	jnz	mai1
+	clr	C
+	mov	A, Cmdh
+	subb	A, #0FEh
+	jz	setbuf				; If command is set buffer, receive data
+	jnc	main
+
+	cjne	Cmdh, #0, mai4			; Jump if command != 0 (and not set buffer)
+
+	; Run application/restart bootloader
+	mov	A, Cmdl
+	jz	rst
+exit:mov	Bit_Access, #0			; Clear variable used by flash lock detect
+	mov	Bit_Access_Int, #0FFh	; Set variable to indicate that program execution came from bootloader
+	mov	BL_Flash_Key_1, #0		; Set flash keys to invalid values
+	mov	BL_Flash_Key_2, #0
+	ljmp	0000h
+rst:	ajmp	init
+
+	; Set buffer
+setbuf:mov Xl, Byte_Cntl			; Set number of bytes
+	mov	Xh, Byte_Cnth
+	inc	Xl
+	inc	Xh
+set4:djnz	Xl, set5
+	djnz	Xh, set5
+	ajmp	set6
+
+set5:acall getc				; Receive data
+	mov	A, Paral
+	movx	@Xl, A				; Store data in XRAM
+	ajmp	set4
+
+set6:inc	Cmdh
+	ajmp	mai2
+
+mai4:clr	C
+	mov	A, Cmdh
+	subb	A, #3
+	jnc	mai5					; Jump if command >= 3
+
+	; Program/erase
+	mov	A, Cmdh
+	mov	C, ACC.0
+	mov	Bit_Reg.0, C
+	mov	Paral, #ERRORPROG
+	clr	C
+	mov	A, DPL
+	subb	A, #low(BOOT_START)
+	mov	A, DPH
+	subb	A, #high(BOOT_START)
+	jnc	mai1					; Jump if in bootloader segment
+	jb	Bit_Reg.0, pro3		; Jump if program command
+
+	; Erase flash
+	orl	PSCTL, #02h			; Set the PSEE bit
+	orl	PSCTL, #01h			; Set the PSWE bit
+	mov	FLKEY, BL_Flash_Key_1	; First key code
+	mov	FLKEY, BL_Flash_Key_2	; Second key code
+	movx	@DPTR, A
+	jnb	Bit_Reg.0, pro6		; Jump if erase command
+
+	; Program flash
+pro3:mov	Xl, Byte_Cntl			; Set number of bytes
+	mov	Xh, Byte_Cnth
+	inc	Xl
+	inc	Xh
+	orl	PSCTL, #01h			; Set the PSWE bit
+	anl	PSCTL, #0FDh			; Clear the PSEE bit
+pro4:djnz	Xl, pro5
+	djnz	Xh, pro5
+	ajmp	pro6
+
+pro5:
+	clr	C
+	mov	A, DPH				; Check that address is not in bootloader area
+	subb	A, #1Ch
+	jc	($+5)
+
+	inc	DPTR					; Increment flash address
+	ajmp	pro4
+
+	movx	A, @Xl				; Read from XRAM
+	mov	FLKEY, BL_Flash_Key_1	; First key code
+	mov	FLKEY, BL_Flash_Key_2	; Second key code
+	movx	@DPTR, A				; Write to flash
+	inc	DPTR					; Increment flash address
+	ajmp	pro4
+
+pro6:anl	PSCTL, #0FCh			; Clear the PSEE and PSWE bits
+	ajmp	main					; Successfully done erase or program
+
+	; Read flash
+mai5:mov	Paral, #ERRORCOMMAND	; Illegal command
+	cjne	Cmdh, #3, mai6			; Jump if not read flash command
+
+rd1:	clr	A
+	movc	A, @A+DPTR			; Read from flash
+	inc	DPTR					; Increment flash address
+	mov	Paral, A
+	acall putp
+	djnz	Cmdl, rd1			; Decrement bytes to read
+
+	acall putw				; CRC
+	ajmp	main
+
+mai6:ajmp	mai1
+
+
+
+
+	; Send char with crc
+putw:mov	Paral, Crcl
+	mov	Parah, Crch
+	acall putc
+	mov	A, Parah
+	mov	Paral, A
+putp:mov	A, Paral
+	xrl	Crcl, A
+	mov	Bit_Cnt, #8
+put1:clr	C
+	mov	A, Crch
+	rrc	A
+	mov	Crch, A
+	mov	A, Crcl
+	rrc	A
+	mov	Crcl, A
+	jnc	put2
+
+	xrl	Crch, #high(POLYNOM)
+	xrl	Crcl, #low(POLYNOM)
+
+put2:djnz	Bit_Cnt, put1
+
+
+	; Send char
+putc:acall waitf
+	acall waitf
+	mov	Bit_Cnt, #10
+	mov	A, Paral
+	cpl	A
+put3:jb	Bit_Reg.1, ($+5)
+	setb	RTX_PORT.RTX_PIN		; Set pin high
+	jnb	Bit_Reg.1, ($+5)
+	clr	RTX_PORT.RTX_PIN		; Set pin low
+	acall waitf
+	clr	C
+	rrc	A
+	jc	put4
+
+	clr	Bit_Reg.1
+
+put4:djnz	Bit_Cnt, put3
+
+	ret
+
+
+	; Receive char/word
+getw:acall getc
+	mov	A, Paral
+	mov	Parah, A
+getc:jb	RTX_PORT.RTX_PIN, ($+5)	; Wait for high
+	ajmp	getc
+
+get1:jnb	RTX_PORT.RTX_PIN, ($+5)	; Wait for low
+	ajmp	get1
+
+getx:mov	Bit_Cnt, #8
+	mov	Cntl, Baudl
+	mov	Cnth, Baudh
+	clr	C
+	mov	A, Cnth				; Wait half a baud
+	rrc	A
+	mov	Cnth, A
+	mov	A, Cntl
+	rrc	A
+	mov	Cntl, A
+	acall waith
+get2:acall waitf				; Wait one baud
+	clr	C
+	mov	A, Paral
+	rrc	A
+	jnb	RTX_PORT.RTX_PIN, ($+5)
+	orl	A, #080h
+
+	mov	Paral, A
+	jnb	ACC.7, ($+6)
+	xrl	Crcl, #low(POLYNOM)
+
+	clr	C
+	mov	A, Crch
+	rrc	A
+	mov	Crch, A
+	mov	A, Crcl
+	rrc	A
+	mov	Crcl, A
+	jnc	get3
+
+	xrl	Crch, #high(POLYNOM)
+	xrl	Crcl, #low(POLYNOM)
+
+get3:djnz	Bit_Cnt, get2
+
+	mov	A, Crcl
+	xrl	A, Crch
+	xrl	A, Crch
+	mov	Crcl, A
+	ret
+
+
+	; UART delays
+waitf:mov	Cntl, Baudl
+	mov	Cnth, Baudh
+waith:inc Cntl
+	inc	Cnth
+wait1:djnz Cntl, wait1
+	djnz Cnth, wait1
+
+	setb	Bit_Reg.1
+	ret
+
+
+BOOT_SIGN:	DB	"BLHeli"
+
+BOOT_MSG:		DB	"471d"		; Interface-MCU_BootlaoderRevision
+
+BOOT_INFO:	DB	SIGNATURE_001, SIGNATURE_002, BOOT_VERSION, BOOT_PAGES
+

BLHeliPgm.inc

@@ -0,0 +1,329 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; BLHeliTxPgm SiLabs
+;
+; EEPROM is not available in SiLabs MCUs
+; Therefore a segment of the flash is used as "EEPROM"
+;
+;**** **** **** **** ****
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read all eeprom parameters routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_all_eeprom_parameters:
+	; Check initialized signature
+	mov	DPTR, #Eep_Initialized_L
+	mov	Temp1, #Bit_Access
+	call read_eeprom_byte
+	mov	A, Bit_Access
+	cjne	A, #055h, read_eeprom_store_defaults
+	inc	DPTR				; Now Eep_Initialized_H
+	call read_eeprom_byte
+	mov	A, Bit_Access
+	cjne	A, #0AAh, read_eeprom_store_defaults
+	jmp	read_eeprom_read
+
+
+read_eeprom_store_defaults:
+	mov	Flash_Key_1, #0A5h
+	mov	Flash_Key_2, #0F1h
+	call set_default_parameters
+	call erase_and_store_all_in_eeprom
+	mov	Flash_Key_1, #0
+	mov	Flash_Key_2, #0
+	jmp	read_eeprom_exit
+
+read_eeprom_read:
+	; Read eeprom
+	mov	DPTR, #_Eep_Pgm_Gov_P_Gain
+	mov	Temp1, #_Pgm_Gov_P_Gain
+	mov	Temp4, #10
+read_eeprom_block1:
+	call read_eeprom_byte
+	inc	DPTR
+	inc	Temp1
+	djnz	Temp4, read_eeprom_block1
+
+	mov	DPTR, #Eep_Enable_TX_Program
+	mov	Temp1, #Pgm_Enable_TX_Program
+	mov	Temp4, #26	; 26 parameters
+read_eeprom_block2:
+	call read_eeprom_byte
+	inc	DPTR
+	inc	Temp1
+	djnz	Temp4, read_eeprom_block2
+
+	mov	DPTR, #Eep_Dummy			; Set pointer to uncritical area
+
+read_eeprom_exit:
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Erase flash and store all parameter value in EEPROM routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+erase_and_store_all_in_eeprom:
+	clr	IE_EA					; Disable interrupts
+	call	read_tags
+	call	erase_flash				; Erase flash
+
+	mov	DPTR, #Eep_FW_Main_Revision	; Store firmware main revision
+	mov	A, #EEPROM_FW_MAIN_REVISION
+	call write_eeprom_byte_from_acc
+
+	inc	DPTR						; Now firmware sub revision
+	mov	A, #EEPROM_FW_SUB_REVISION
+	call write_eeprom_byte_from_acc
+
+	inc	DPTR						; Now layout revision
+	mov	A, #EEPROM_LAYOUT_REVISION
+	call write_eeprom_byte_from_acc
+
+	; Write eeprom
+	mov	DPTR, #_Eep_Pgm_Gov_P_Gain
+	mov	Temp1, #_Pgm_Gov_P_Gain
+	mov	Temp4, #10
+write_eeprom_block1:
+	call write_eeprom_byte
+	inc	DPTR
+	inc	Temp1
+	djnz	Temp4, write_eeprom_block1
+
+	mov	DPTR, #Eep_Enable_TX_Program
+	mov	Temp1, #Pgm_Enable_TX_Program
+	mov	Temp4, #26	; 26 parameters
+write_eeprom_block2:
+	call write_eeprom_byte
+	inc	DPTR
+	inc	Temp1
+	djnz	Temp4, write_eeprom_block2
+
+	call	write_tags
+	call write_eeprom_signature
+	mov	DPTR, #Eep_Dummy			; Set pointer to uncritical area
+	ret
+
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read eeprom byte routine
+;
+; Gives data in A and in address given by Temp1. Assumes address in DPTR
+; Also assumes address high byte to be zero
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_eeprom_byte:
+	clr	A
+	movc	A, @A+DPTR			; Read from flash
+	mov	@Temp1, A
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write eeprom byte routine
+;
+; Assumes data in address given by Temp1, or in accumulator. Assumes address in DPTR
+; Also assumes address high byte to be zero
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_eeprom_byte:
+	mov	A, @Temp1
+write_eeprom_byte_from_acc:
+	orl	PSCTL, #01h			; Set the PSWE bit
+	anl	PSCTL, #0FDh			; Clear the PSEE bit
+	mov	Temp8, A
+	clr	C
+	mov	A, DPH				; Check that address is not in bootloader area
+	subb	A, #1Ch
+	jc	($+3)
+
+	ret
+
+	mov	A, Temp8
+	mov	FLKEY, Flash_Key_1		; First key code
+	mov	FLKEY, Flash_Key_2		; Second key code
+	movx	@DPTR, A				; Write to flash
+	anl	PSCTL, #0FEh			; Clear the PSWE bit
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Erase flash routine (erases the flash segment used for "eeprom" variables)
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+erase_flash:
+	orl	PSCTL, #02h			; Set the PSEE bit
+	orl	PSCTL, #01h			; Set the PSWE bit
+	mov	FLKEY, Flash_Key_1		; First key code
+	mov	FLKEY, Flash_Key_2		; Second key code
+	mov	DPTR, #Eep_Initialized_L
+	movx	@DPTR, A
+	anl	PSCTL, #0FCh			; Clear the PSEE and PSWE bits
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write eeprom signature routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_eeprom_signature:
+	mov	DPTR, #Eep_Initialized_L
+	mov	A, #055h
+	call write_eeprom_byte_from_acc
+
+	mov	DPTR, #Eep_Initialized_H
+	mov	A, #0AAh
+	call write_eeprom_byte_from_acc
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Read all tags from flash and store in temporary storage
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+read_tags:
+	mov	Temp3, #48			; Number of tags
+	mov	Temp2, #Temp_Storage	; Set RAM address
+	mov	Temp1, #Bit_Access
+	mov	DPTR, #Eep_ESC_Layout	; Set flash address
+read_tag:
+	call read_eeprom_byte
+	mov	A, Bit_Access
+	mov	@Temp2, A				; Write to RAM
+	inc	Temp2
+	inc	DPTR
+	djnz Temp3, read_tag
+	ret
+
+
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Write all tags from temporary storage and store in flash
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+write_tags:
+	mov	Temp3, #48			; Number of tags
+	mov	Temp2, #Temp_Storage	; Set RAM address
+	mov	DPTR, #Eep_ESC_Layout	; Set flash address
+write_tag:
+	mov	A, @Temp2				; Read from RAM
+	call write_eeprom_byte_from_acc
+	inc	Temp2
+	inc	DPTR
+	djnz Temp3, write_tag
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Wait 1 second routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+wait1s:
+	mov	Temp5, #5
+wait1s_loop:
+	call wait200ms
+	djnz	Temp5, wait1s_loop
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Success beep routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+success_beep:
+	clr	IE_EA				; Disable all interrupts
+	call beep_f1
+	call beep_f2
+	call beep_f3
+	call beep_f4
+	call wait10ms
+	call beep_f1
+	call beep_f2
+	call beep_f3
+	call beep_f4
+	call wait10ms
+	call beep_f1
+	call beep_f2
+	call beep_f3
+	call beep_f4
+	setb	IE_EA				; Enable all interrupts
+	ret
+
+
+;**;**** **** **** **** **** **** **** **** **** **** **** **** ****
+;
+; Success beep inverted routine
+;
+; No assumptions
+;
+;**** **** **** **** **** **** **** **** **** **** **** **** ****
+success_beep_inverted:
+	clr	IE_EA				; Disable all interrupts
+	call beep_f4
+	call beep_f3
+	call beep_f2
+	call beep_f1
+	call wait10ms
+	call beep_f4
+	call beep_f3
+	call beep_f2
+	call beep_f1
+	call wait10ms
+	call beep_f4
+	call beep_f3
+	call beep_f2
+	call beep_f1
+	setb	IE_EA				; Enable all interrupts
+	ret
+
+

C.inc

@@ -0,0 +1,560 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "C"
+; Ac Ap MC MB MA CC X  RC    X  X  X  X  Cc Cp Bc Bp
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#C_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#C_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#C_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#C_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#C_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#C_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#C_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#C_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#C_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#C_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#C_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#C_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#C_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#C_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#C_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#C_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#C_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#C_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#C_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#C_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#C_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#C_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	0		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+AcomFET		EQU	7	;o
+ApwmFET		EQU	6	;o
+Mux_C		EQU	5	;i
+Mux_B		EQU	4	;i
+Mux_A		EQU	3	;i
+Comp_Com		EQU	2	;i
+;			EQU	1	;i
+Rcp_In		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	NOT((1 SHL ApwmFET)+(1 SHL AcomFET))
+P0_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL AcomFET)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+;			EQU	5	;i
+;			EQU	4	;i
+CcomFET		EQU	3	;o
+CpwmFET		EQU	2	;o
+BcomFET		EQU	1	;o
+BpwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	0Fh
+
+ApwmFET_on MACRO
+	setb	P0.ApwmFET
+IF FETON_DELAY == 0
+	setb	P0.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P0.ApwmFET
+ELSE
+	clr	P0.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P0.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P0.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P0.ApwmFET
+ENDIF
+	setb	P0.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P0.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P0.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P0.AcomFET
+	mov	P0SKIP, #0BFh
+	mov	P1SKIP, #0Fh
+ELSE
+	mov	P0SKIP, #03Fh
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #0Eh
+ELSE
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #0Ch
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #0Bh
+ELSE
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #03h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #0Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #32h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #42h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #52h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

COPYING

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble 
+
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+
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+<http://www.gnu.org/philosophy/why-not-lgpl.html>.

D.inc

@@ -0,0 +1,553 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "D". Com fets are active low for H/L_N driver and EN_N/PWM driver
+; X  X  RC X  CC MA MC MB    X  X  Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#D_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#D_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#D_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#D_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#D_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#D_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#D_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#D_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#D_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#D_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#D_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#D_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#D_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#D_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#D_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#D_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#D_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#D_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#D_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#D_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#D_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#D_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Comp_Com		EQU	3	;i
+Mux_A		EQU	2	;i
+Mux_C		EQU	1	;i
+Mux_B		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #00h				; Damping noninverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CcomFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+BcomFET		EQU	3	;o
+BpwmFET		EQU	2	;o
+AcomFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	clr	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	setb	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	clr	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	setb	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	clr	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	setb	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	setb	P1.AcomFET
+	setb	P1.BcomFET
+	setb	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	clr	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	setb	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	clr	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	setb	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	clr	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	setb	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	setb	P1.AcomFET
+	setb	P1.BcomFET
+	setb	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	clr	P1.AcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	clr	P1.BcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	clr	P1.CcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #03h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

Dshotprog spec BLHeli_S.txt

@@ -0,0 +1,27 @@
+0  DSHOT_CMD_MOTOR_STOP,		// Currently not implemented
+1  DSHOT_CMD_BEEP1,			// Wait at least length of beep (380ms) before next command
+2  DSHOT_CMD_BEEP2,			// Wait at least length of beep (380ms) before next command
+3  DSHOT_CMD_BEEP3,			// Wait at least length of beep (400ms) before next command
+4  DSHOT_CMD_BEEP4,			// Wait at least length of beep (400ms) before next command
+5  DSHOT_CMD_BEEP5,			// Wait at least length of beep (400ms) before next command
+6  DSHOT_CMD_ESC_INFO, 			// Currently not implemented
+7  DSHOT_CMD_SPIN_DIRECTION_1,		// Need 6x, no wait required
+8  DSHOT_CMD_SPIN_DIRECTION_2,		// Need 6x, no wait required
+9  DSHOT_CMD_3D_MODE_OFF,		// Need 6x, no wait required
+10 DSHOT_CMD_3D_MODE_ON, 		// Need 6x, no wait required
+11 DSHOT_CMD_SETTINGS_REQUEST, 		// Currently not implemented
+12 DSHOT_CMD_SAVE_SETTINGS, 		// Need 6x, wait at least 12ms before next command
+20 DSHOT_CMD_SPIN_DIRECTION_NORMAL,	// Need 6x, no wait required
+21 DSHOT_CMD_SPIN_DIRECTION_REVERSED,	// Need 6x, no wait required
+22 DSHOT_CMD_LED0_ON,			// Currently not implemented
+23 DSHOT_CMD_LED1_ON,			// Currently not implemented
+24 DSHOT_CMD_LED2_ON,			// Currently not implemented
+25 DSHOT_CMD_LED3_ON,			// Currently not implemented
+26 DSHOT_CMD_LED0_OFF,			// Currently not implemented
+27 DSHOT_CMD_LED1_OFF,			// Currently not implemented
+28 DSHOT_CMD_LED2_OFF,			// Currently not implemented
+29 DSHOT_CMD_LED3_OFF,			// Currently not implemented
+   DSHOT_CMD_MAX = 47
+
+
+

E.inc

@@ -0,0 +1,566 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "E". Equals "A", but with LED control. And with HIP2103/4 driver initialization
+; L1 L0 RC X  MC MB MA CC    X  L2 Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#E_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#E_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#E_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#E_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#E_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#E_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#E_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#E_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#E_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#E_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#E_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#E_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#E_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#E_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#E_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#E_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#E_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#E_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#E_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#E_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#E_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#E_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+LED_1		EQU	7	;o
+LED_0		EQU	6	;o
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_A		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	NOT((1 SHL LED_0)+(1 SHL LED_1))
+P0_PUSHPULL	EQU	(1 SHL LED_0)+(1 SHL LED_1)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+LED_2		EQU	6	;o
+CcomFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+BcomFET		EQU	3	;o
+BpwmFET		EQU	2	;o
+AcomFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)+(1 SHL LED_2)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)+(1 SHL LED_2)
+P1_SKIP		EQU	7Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #7Eh
+ELSE
+	mov	P1SKIP, #7Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #7Bh
+ELSE
+	mov	P1SKIP, #73h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #6Fh
+ELSE
+	mov	P1SKIP, #4Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+	All_pwmFETs_off	; For unlocking of HIP2103/4 driver circuits
+	call wait100ms
+	AcomFET_on
+	BcomFET_on
+	CcomFET_on
+	call wait1ms
+	All_comFETs_off
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+	setb	P0.LED_0
+ENDM
+Clear_LED_0 MACRO
+	clr	P0.LED_0
+ENDM
+Set_LED_1 MACRO
+	setb	P0.LED_1
+ENDM
+Clear_LED_1 MACRO
+	clr	P0.LED_1
+ENDM
+Set_LED_2 MACRO
+	setb	P1.LED_2
+ENDM
+Clear_LED_2 MACRO
+	clr	P1.LED_2
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

F.inc

@@ -0,0 +1,553 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "F". Equals "A", but with Mux_A and Mux_C swapped
+; X  X  RC X  MA MB MC CC    X  X  Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#F_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#F_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#F_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#F_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#F_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#F_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#F_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#F_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#F_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#F_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#F_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#F_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#F_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#F_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#F_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#F_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#F_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#F_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#F_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#F_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#F_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#F_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_A		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_C		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CcomFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+BcomFET		EQU	3	;o
+BpwmFET		EQU	2	;o
+AcomFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

G.inc

@@ -0,0 +1,553 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "G"
+; X  X  RC X  CC MA MC MB    X  X  Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#G_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#G_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#G_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#G_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#G_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#G_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#G_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#G_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#G_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#G_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#G_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#G_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#G_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#G_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#G_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#G_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#G_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#G_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#G_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#G_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#G_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#G_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Comp_Com		EQU	3	;i
+Mux_A		EQU	2	;i
+Mux_C		EQU	1	;i
+Mux_B		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CcomFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+BcomFET		EQU	3	;o
+BpwmFET		EQU	2	;o
+AcomFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #03h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

H.inc

@@ -0,0 +1,558 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "H". 
+; RC X  X  X  MA MB CC MC    X  Ap Bp Cp X  Ac Bc Cc 
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#H_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#H_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#H_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#H_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#H_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#H_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#H_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#H_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#H_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#H_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#H_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#H_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#H_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#H_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#H_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#H_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#H_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#H_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#H_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#H_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#H_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#H_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	7		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Rcp_In		EQU	7	;i
+;			EQU	6	;i
+;  			EQU	5	;i
+;			EQU	4	;i 
+Mux_A		EQU	3	;i
+Mux_B		EQU	2	;i
+Comp_Com		EQU	1	;i
+Mux_C		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+ApwmFET		EQU	6	;o
+BpwmFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+;			EQU	3	;i
+AcomFET		EQU	2	;o 
+BcomFET		EQU	1	;o
+CcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	7Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Fh
+ELSE
+	mov	P1SKIP, #3Bh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #5Fh
+ELSE
+	mov	P1SKIP, #5Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #6Fh
+ELSE
+	mov	P1SKIP, #6Eh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #31h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #21h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #01h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

I.inc

@@ -0,0 +1,552 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "I"
+; X  X  RC X  MC MB MA CC    X  X  Ac Bc Cc Ap Bp Cp
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#I_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#I_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#I_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#I_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#I_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#I_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#I_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#I_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#I_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#I_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#I_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#I_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#I_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#I_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#I_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#I_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#I_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#I_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#I_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#I_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#I_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#I_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_A		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+AcomFET		EQU	5	;o
+BcomFET		EQU	4	;o
+CcomFET		EQU	3	;o
+ApwmFET		EQU	2	;o
+BpwmFET		EQU	1	;o
+CpwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #1Bh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #2Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #36h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

J.inc

@@ -0,0 +1,558 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "J"
+; L2 L1 L0 RC CC MB MC MA    X  X  Cc Bc Ac Cp Bp Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#J_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#J_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#J_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#J_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#J_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#J_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#J_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#J_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#J_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#J_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#J_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#J_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#J_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#J_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#J_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#J_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#J_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#J_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#J_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#J_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#J_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#J_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	4		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+LED_2		EQU	7	;o
+LED_1		EQU	6	;o
+LED_0		EQU	5	;o
+Rcp_In		EQU	4	;i
+Comp_Com		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_C		EQU	1	;i
+Mux_A		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	(1 SHL LED_0)+(1 SHL LED_1)+(1 SHL LED_2)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CcomFET		EQU	5	;o
+BcomFET		EQU	4	;o
+AcomFET		EQU	3	;o
+CpwmFET		EQU	2	;o
+BpwmFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #36h
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #2Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #1Bh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #03h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+	clr	P0.LED_0
+ENDM
+Clear_LED_0 MACRO
+	setb	P0.LED_0
+ENDM
+Set_LED_1 MACRO
+	clr	P0.LED_1
+ENDM
+Clear_LED_1 MACRO
+	setb	P0.LED_1
+ENDM
+Set_LED_2 MACRO
+	clr	P0.LED_2
+ENDM
+Clear_LED_2 MACRO
+	setb	P0.LED_2
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

K.inc

@@ -0,0 +1,554 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "K". Com fets are active low for H/L_N driver and EN_N/PWM driver
+; X  X  MC X  MB CC MA RC    X  X  Ap Bp Cp Cc Bc Ac	Com fets inverted
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#K_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#K_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#K_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#K_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#K_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#K_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#K_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#K_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#K_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#K_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#K_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#K_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#K_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#K_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#K_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#K_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#K_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#K_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#K_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#K_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#K_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#K_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	0		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;  			EQU	7	;i
+;			EQU	6	;i
+Mux_C		EQU	5	;i
+;			EQU	4	;i
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_A		EQU	1	;i
+Rcp_In		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #00h				; Damping noninverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+ApwmFET		EQU	5	;o
+BpwmFET		EQU	4	;o
+CpwmFET		EQU	3	;o
+CcomFET		EQU	2	;o
+BcomFET		EQU	1	;o
+AcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	clr	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	setb	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	clr	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	setb	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	clr	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	setb	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	setb	P1.AcomFET
+	setb	P1.BcomFET
+	setb	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	clr	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	setb	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	clr	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	setb	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	clr	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	setb	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	setb	P1.AcomFET
+	setb	P1.BcomFET
+	setb	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	clr	P1.AcomFET
+	mov	P1SKIP, #1Fh
+ELSE
+	mov	P1SKIP, #1Eh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	clr	P1.BcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #2Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	clr	P1.CcomFET
+	mov	P1SKIP, #37h
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #12h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #32h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #52h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

L.inc

@@ -0,0 +1,552 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "L"
+; X  X  RC X  CC MA MB MC    X  X  Ac Bc Cc Ap Bp Cp
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#L_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#L_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#L_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#L_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#L_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#L_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#L_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#L_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#L_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#L_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#L_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#L_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#L_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#L_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#L_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#L_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#L_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#L_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#L_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#L_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#L_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#L_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Comp_Com		EQU	3	;i
+Mux_A		EQU	2	;i
+Mux_B		EQU	1	;i
+Mux_C		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+AcomFET		EQU	5	;o
+BcomFET		EQU	4	;o
+CcomFET		EQU	3	;o
+ApwmFET		EQU	2	;o
+BpwmFET		EQU	1	;o
+CpwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #1Bh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #2Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #36h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #03h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

M.inc

@@ -0,0 +1,557 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "M".
+; MA MC CC MB RC L0 X  X     X  Cc Bc Ac Cp Bp Ap X     
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#M_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#M_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#M_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#M_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#M_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#M_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#M_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#M_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#M_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#M_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#M_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#M_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#M_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#M_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#M_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#M_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#M_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#M_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#M_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#M_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#M_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#M_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	3		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Mux_A		EQU	7	;i
+Mux_C		EQU	6	;i
+Comp_Com  	EQU	5	;i
+Mux_B		EQU	4	;i
+Rcp_In		EQU	3	;i
+LED_0		EQU	2	;i
+;			EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	NOT(1 SHL LED_0)
+P0_PUSHPULL	EQU	(1 SHL LED_0)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+CcomFET		EQU	6	;o
+BcomFET		EQU	5	;o
+AcomFET		EQU	4	;o
+CpwmFET		EQU	3	;i
+BpwmFET		EQU	2	;o 
+ApwmFET		EQU	1	;o
+;			EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	7Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #7Dh
+ELSE
+	mov	P1SKIP, #6Dh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #7Bh
+ELSE
+	mov	P1SKIP, #5Bh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #77h
+ELSE
+	mov	P1SKIP, #37h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #75h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #45h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #65h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+	setb	P0.LED_0
+ENDM
+Clear_LED_0 MACRO
+     clr	P0.LED_0
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

MakeHexfiles.bat

@@ -0,0 +1,267 @@
+@ECHO off
+@ECHO ***** Batch file for BlHeli_S (from 4712)  v.2         *****
+@ECHO ***** All Messages will be saved to MakeHex_Result.txt *****
+@ECHO ***** Start compile with any key  - CTRL-C to abort    *****
+Break ON
+@pause
+DEL MakeHex_Result.txt /Q
+
+rem ***** Adapt settings to your enviroment ****
+DEL Output\Hex\*.* /Q
+RMDIR Output\Hex
+DEL Output\*.* /Q
+RMDIR Output
+MKDIR Output
+MKDIR Output\Hex
+SET Revision=REV16_7
+SET KeilPath=C:\SiliconLabs\SimplicityStudio\v4\developer\toolchains\keil_8051\9.53\BIN
+
+@ECHO Revision: %Revision% >> MakeHex_Result.txt
+@ECHO Path for Keil toolchain: %KeilPath% >> MakeHex_Result.txt
+@ECHO Start compile ..... >> MakeHex_Result.txt
+
+
+SET ESCNO=1
+SET ESC=A_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=A_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=B_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=B_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=C_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=C_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=D_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=D_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=E_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=E_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=F_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=F_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=G_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=G_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=H_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=H_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=I_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=I_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=J_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=J_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=K_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=K_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=L_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=L_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=M_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=M_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=N_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=N_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=O_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=O_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=P_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=P_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=Q_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=Q_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=R_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=R_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=S_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=S_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=T_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=T_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=U_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=U_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=V_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=V_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+SET ESC=W_L_
+SET MCU_48MHZ=0
+call:compile
+SET ESC=W_H_
+SET MCU_48MHZ=1
+call:compile
+SET /A ESCNO+=1
+
+
+goto :end
+
+
+:compile
+SET FETON_DELAY=0
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=5
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=10
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=15
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=20
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=25
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=30
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=40
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=50
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=70
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+SET /A FETON_DELAY=90
+SET ESCNAME=%ESC%%FETON_DELAY%
+call :compile_code
+goto :eof
+
+
+:compile_code
+@ECHO compiling %ESCNAME%  
+@ECHO. >> MakeHex_Result.txt
+@ECHO ********************************************************************  >> MakeHex_Result.txt
+@ECHO %ESCNAME%  >> MakeHex_Result.txt
+@ECHO ********************************************************************  >> MakeHex_Result.txt
+%KeilPath%\AX51.exe "BLHeli_S.asm" DEFINE(ESCNO=%ESCNO%) DEFINE(MCU_48MHZ=%MCU_48MHZ%) DEFINE(FETON_DELAY=%FETON_DELAY%) OBJECT(Output\%ESCNAME%_%Revision%.OBJ) DEBUG MACRO NOMOD51 COND SYMBOLS PAGEWIDTH(120) PAGELENGTH(65) >> MakeHex_Result.txt
+%KeilPath%\LX51.exe "Output\%ESCNAME%_%Revision%.OBJ" TO "Output\%ESCNAME%_%Revision%.OMF" PAGEWIDTH (120) PAGELENGTH (65) >> MakeHex_Result.txt
+%KeilPath%\Ohx51 "Output\%ESCNAME%_%Revision%.OMF" "HEXFILE (Output\%ESCNAME%_%Revision%.HEX)" "H386" >> MakeHex_Result.txt
+copy "Output\%ESCNAME%_%Revision%.HEX" "Output\Hex\%ESCNAME%_%Revision%.HEX" > nul
+del "Output\%ESCNAME%_%Revision%.HEX" > nul
+@ECHO. >> MakeHex_Result.txt
+goto :eof
+
+:end
+
+@pause
+exit

Makefile

@@ -0,0 +1,127 @@
+# set current revision
+REVISION ?= REV16_7
+
+# targets
+TARGETS      = A B C D E F G H I J K L M N O P Q R S T U V W
+MCUS         = H L
+FETON_DELAYS = 0 5 10 15 20 25 30 40 50 70 90
+
+# example single target
+VARIANT     ?= A
+MCU         ?= H
+FETON_DELAY ?= 5
+
+# configure the script to use the wine installation delivered with
+# SimplicityStudio. these wine settings are quite important. if you get
+#  ERROR L250: CODE SIZE LIMIT IN RESTRICTED VERSION EXCEEDED
+# you messed up your simplicity studio install/path settins below:
+SIMPLICITY_PATH ?= ~/local/SimplicityStudio_v4/
+WINE_PREFIX     ?= ~/.config/SimplicityStudio/v4/studio-wine
+WINE_BIN        ?= $(SIMPLICITY_PATH)/support/common/wine/usr/bin/wine
+WINE            = export WINEPREFIX=`realpath $(WINE_PREFIX)`; $(WINE_BIN)
+
+# path to the keil binaries
+KEIL_PATH       = $(SIMPLICITY_PATH)/developer/toolchains/keil_8051/9.53/BIN
+
+# some directory config
+OUTPUT_DIR     ?= build
+OUTPUT_DIR_HEX ?= $(OUTPUT_DIR)/hex
+LOG_DIR        ?= $(OUTPUT_DIR)/log
+
+# define the assembler/linker scripts
+AX51_BIN = $(KEIL_PATH)/AX51.exe
+LX51_BIN = $(KEIL_PATH)/LX51.exe
+OX51_BIN = $(KEIL_PATH)/Ohx51.exe
+AX51 = $(WINE) $(AX51_BIN)
+LX51 = $(WINE) $(LX51_BIN)
+OX51 = $(WINE) $(OX51_BIN)
+
+# set up flags
+AX51_FLAGS = DEBUG MACRO NOMOD51 COND SYMBOLS PAGEWIDTH(120) PAGELENGTH(65)
+LX51_FLAGS = PAGEWIDTH (120) PAGELENGTH (65)
+
+# set up sources
+ASM_SRC = BLHeli_S.asm
+ASM_INC = $(TARGETS:=.inc) BLHeliBootLoad.inc BLHeliPgm.inc SI_EFM8BB1_Defs.inc SI_EFM8BB2_Defs.inc
+
+# check that wine/simplicity studio is available
+EXECUTABLES = $(WINE_BIN) $(AX51_BIN) $(LX51_BIN) $(OX51_BIN) 
+DUMMYVAR := $(foreach exec, $(EXECUTABLES), \
+		$(if $(wildcard $(exec)),found, \
+		$(error "Could not find $(exec). Make sure to set the correct paths to the simplicity install location")))
+
+# make sure the list of obj files is expanded twice
+.SECONDEXPANSION:
+OBJS = 
+
+define MAKE_OBJ
+OBJS += $(OUTPUT_DIR)/$(1)_$(2)_$(3)_$(REVISION).OBJ
+$(OUTPUT_DIR)/$(1)_$(2)_$(3)_$(REVISION).OBJ : $(ASM_SRC) $(ASM_INC)
+	$(eval _ESC         := $(1))
+	$(eval _ESC_INT     := $(shell printf "%d" "'${_ESC}"))
+	$(eval _ESCNO       := $(shell echo $$(( $(_ESC_INT) - 65 + 1))))
+        $(eval _MCU_48MHZ   := $(subst L,0,$(subst H,1,$(2))))
+	$(eval _FETON_DELAY := $(3))
+	$(eval _LOG         := $(LOG_DIR)/$(1)_$(2)_$(3)_$(REVISION).log)
+	@mkdir -p $(OUTPUT_DIR)
+	@mkdir -p $(LOG_DIR)
+	@echo "AX51 : $$@"
+	@$(AX51) $(ASM_SRC) \
+		"DEFINE(ESCNO=$(_ESCNO)) " \
+                "DEFINE(MCU_48MHZ=$(_MCU_48MHZ)) "\
+                "DEFINE(FETON_DELAY=$(_FETON_DELAY)) "\
+                "OBJECT($$@) "\
+                "$(AX51_FLAGS)" >> $(_LOG) 2>&1; test $$$$? -lt 2 || tail $(_LOG)
+
+endef
+
+HEX_TARGETS = $(OBJS:.OBJ=.HEX)
+
+EFM8_LOAD_BIN  ?= efm8load.py
+EFM8_LOAD_PORT ?= /dev/ttyUSB0
+EFM8_LOAD_BAUD ?= 57600
+
+SINGLE_TARGET_HEX = $(OUTPUT_DIR)/$(VARIANT)_$(MCU)_$(FETON_DELAY)_$(REVISION).HEX
+
+single_target : $(SINGLE_TARGET_HEX)
+
+all : $$(HEX_TARGETS)
+	@echo "\nbuild finished. built $(shell ls -l $(OUTPUT_DIR_HEX) | wc -l) hex targets\n"
+
+# create all obj targets using macro expansion
+$(foreach _e,$(TARGETS), \
+	$(foreach _m, $(MCUS), \
+		$(foreach _f, $(FETON_DELAYS), \
+			$(eval $(call MAKE_OBJ,$(_e),$(_m),$(_f))))))
+	
+
+$(OUTPUT_DIR)/%.OMF : $(OUTPUT_DIR)/%.OBJ
+	$(eval LOG         := $(LOG_DIR)/$(basename $(notdir $@)).log)
+	@echo "LX51 : linking $< to $@"
+	@$(LX51) "$<" TO "$@" "$(LX51_FLAGS)" >> $(LOG) 2>&1; test $$? -lt 2 || tail $(LOG)
+
+$(OUTPUT_DIR)/%.HEX : $(OUTPUT_DIR)/%.OMF
+	$(eval LOG         := $(LOG_DIR)/$(basename $(notdir $@)).log)
+	@mkdir -p $(OUTPUT_DIR_HEX)
+	@echo "OHX  : generating hex file $@"
+	@$(OX51) "$<" "HEXFILE ($@)" "H386" >> $(LOG) 2>&1; test $$? -lt 2 || tail $(LOG)
+	@cp $@ $(OUTPUT_DIR_HEX)/$(notdir $@)
+
+help:
+	@echo ""
+	@echo "usage examples:"
+	@echo "================================================================="
+	@echo "make all                              # build all targets"
+	@echo "make VARIANT=A MCU=H FETON_DELAY=5    # to build a single target" 
+	@echo
+
+clean:
+	@rm -rf $(LOG_DIR)/*
+	@rm -rf $(OUTPUT_DIR)/*
+
+efm8load: single_target
+	$(EFM8_LOAD_BIN) -p $(EFM8_LOAD_PORT) -b $(EFM8_LOAD_BAUD) -w $(SINGLE_TARGET_HEX)
+
+
+.PHONY: all clean help efm8load
+

N.inc

@@ -0,0 +1,558 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "N"
+; X  X  RC X  MC MB MA CC    X  X  Cp Cc Bp Bc Ap Ac
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#N_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#N_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#N_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#N_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#N_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#N_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#N_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#N_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#N_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#N_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#N_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#N_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#N_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#N_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#N_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#N_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#N_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#N_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#N_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#N_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#N_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#N_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_A		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CpwmFET		EQU	5	;o
+CcomFET		EQU	4	;o
+BpwmFET		EQU	3	;o
+BcomFET		EQU	2	;o
+ApwmFET		EQU	1	;o
+AcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #37h
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #1Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

O.inc

@@ -0,0 +1,554 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "O". Com fets are active low for H/L_N driver and EN_N/PWM driver. Low side pwm and 1S flag set
+; X  X  RC X  CC MA MC MB    X  X  Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#O_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#O_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#O_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#O_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#O_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#O_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#O_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#O_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#O_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#O_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#O_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#O_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#O_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#O_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#O_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#O_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#O_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#O_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#O_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#O_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#O_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#O_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Comp_Com		EQU	3	;i
+Mux_A		EQU	2	;i
+Mux_C		EQU	1	;i
+Mux_B		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #00h				; Damping noninverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CcomFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+BcomFET		EQU	3	;o
+BpwmFET		EQU	2	;o
+AcomFET		EQU	1	;o
+ApwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	clr	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	setb	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	clr	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	setb	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	clr	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	setb	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	setb	P1.AcomFET
+	setb	P1.BcomFET
+	setb	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	clr	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	setb	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	clr	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	setb	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	clr	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	setb	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	setb	P1.AcomFET
+	setb	P1.BcomFET
+	setb	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	clr	P1.AcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	clr	P1.BcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	clr	P1.CcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #03h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+	cpl A
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

P.inc

@@ -0,0 +1,555 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "P".
+; X  X  RC MA CC MB MC X     X  Cc Bc Ac Cp Bp Ap X    
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#P_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#P_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#P_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#P_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#P_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#P_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#P_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#P_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#P_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#P_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#P_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#P_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#P_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#P_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#P_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#P_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#P_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#P_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#P_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#P_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#P_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#P_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In 		EQU	5	;i
+Mux_A		EQU	4	;i
+Comp_Com		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+CcomFET		EQU	6	;o
+BcomFET		EQU	5	;o
+AcomFET		EQU	4	;o
+CpwmFET		EQU	3	;i
+BpwmFET		EQU	2	;o 
+ApwmFET		EQU	1	;o
+;			EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	7Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #7Dh
+ELSE
+	mov	P1SKIP, #6Dh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #7Bh
+ELSE
+	mov	P1SKIP, #5Bh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #77h
+ELSE
+	mov	P1SKIP, #37h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #43h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

Q.inc

@@ -0,0 +1,564 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "Q"
+; Cp Bp Ap L1 L0 X  RC X     X  MA MB MC CC Cc Bc Ac
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#Q_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#Q_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#Q_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#Q_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#Q_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#Q_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#Q_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#Q_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#Q_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#Q_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#Q_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#Q_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#Q_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#Q_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#Q_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#Q_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#Q_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#Q_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#Q_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#Q_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#Q_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#Q_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	1		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+CpwmFET		EQU	7	;o
+BpwmFET		EQU	6	;o
+ApwmFET		EQU	5	;o
+LED_1		EQU	4	;i
+LED_0		EQU	3	;i
+;			EQU	2	;i
+Rcp_In		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	0FFh
+P0_INIT		EQU	(1 SHL Rcp_In)
+P0_PUSHPULL	EQU	(1 SHL LED_0)+(1 SHL LED_1)+(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+Mux_A		EQU	6	;i
+Mux_B		EQU	5	;i
+Mux_C		EQU	4	;i
+Comp_Com		EQU	3	;o
+CcomFET		EQU	2	;o
+BcomFET		EQU	1	;o
+AcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	07h
+
+ApwmFET_on MACRO
+	setb	P0.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P0.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P0.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P0.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P0.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P0.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P0.ApwmFET
+	clr	P0.BpwmFET
+	clr	P0.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P0.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P0.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P0.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P0SKIP, #0DFh
+	mov	P1SKIP, #07h
+ELSE
+	mov	P0SKIP, #0DFh
+	mov	P1SKIP, #06h
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P0SKIP, #0BFh
+	mov	P1SKIP, #07h
+ELSE
+	mov	P0SKIP, #0BFh
+	mov	P1SKIP, #05h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P0SKIP, #07Fh
+	mov	P1SKIP, #07h
+ELSE
+	mov	P0SKIP, #07Fh
+	mov	P1SKIP, #03h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #07h
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP1MX, #63h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP1MX, #53h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP1MX, #43h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP1CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP1CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP1MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+	setb	P0.LED_0
+ENDM
+Clear_LED_0 MACRO
+	clr	P0.LED_0
+ENDM
+Set_LED_1 MACRO
+	setb	P0.LED_1
+ENDM
+Clear_LED_1 MACRO
+	clr	P0.LED_1
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

R.inc

@@ -0,0 +1,552 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "R".
+; X  X  RC X  MC MB MA CC    X  X  Ac Bc Cc Ap Bp Cp
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#R_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#R_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#R_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#R_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#R_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#R_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#R_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#R_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#R_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#R_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#R_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#R_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#R_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#R_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#R_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#R_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#R_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#R_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#R_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#R_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#R_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#R_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;  			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Mux_B		EQU	2	;i
+Mux_A		EQU	1	;i
+Comp_Com		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+AcomFET		EQU	5	;o
+BcomFET		EQU	4	;o
+CcomFET		EQU	3	;o
+ApwmFET		EQU	2	;o
+BpwmFET		EQU	1	;o
+CpwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Bh
+ELSE
+	mov	P1SKIP, #1Bh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #2Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #3Eh
+ELSE
+	mov	P1SKIP, #36h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #10h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #20h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #30h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

README.md

@@ -0,0 +1,16 @@
+This tree contains BLHeli code for sensorless brushless motor electronic speed control (ESC) boards.  
+  
+To view and use the files, click the "Clone or download" button on this page,  
+and then select "Download ZIP" to download the repository to your computer.  
+  
+For flashing and configuration, download the BLHeliSuite PC software:  
+https://www.mediafire.com/folder/dx6kfaasyo24l/BLHeliSuite  
+  
+For more information, check out these threads:  
+https://www.rcgroups.com/forums/showthread.php?2640796 (for BLHeli_S)  
+http://www.rcgroups.com/forums/showthread.php?t=2136895 (for BLHeli)  
+  
+And look in the "BLHeli_32 ARM" folder for info on BLHeli_32.
+
+October 2018,
+Steffen Skaug

S.inc

@@ -0,0 +1,557 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "S". like "O" but Com fets are active high, Pwm fets are active low
+; X  X  RC X  CC MA MC MB    X  X  Cc Cp Bc Bp Ac Ap
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#S_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#S_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#S_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#S_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#S_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#S_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#S_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#S_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#S_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#S_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#S_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#S_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#S_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#S_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#S_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#S_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#S_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#S_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#S_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#S_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#S_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#S_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+;			EQU	7	;i
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Comp_Com		EQU	3	;i
+Mux_A		EQU	2	;i
+Mux_C		EQU	1	;i
+Mux_B		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CpwmFET		EQU	5	;o
+CcomFET		EQU	4	;o
+BpwmFET		EQU	3	;o
+BcomFET		EQU	2	;o
+ApwmFET		EQU	1	;o
+AcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	(0 SHL AcomFET)+(0 SHL BcomFET)+(0 SHL CcomFET)
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #3Dh
+ELSE
+	mov	P1SKIP, #3Ch
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #37h
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #1Fh
+ELSE
+	mov	P1SKIP, #0Fh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #23h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #03h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #13h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

SI_EFM8BB1_Defs.inc

@@ -0,0 +1,323 @@
+;------------------------------------------------------------------------------
+; Copyright 2014 Silicon Laboratories, Inc.
+; All rights reserved. This program and the accompanying materials
+; are made available under the terms of the Silicon Laboratories End User
+; License Agreement which accompanies this distribution, and is available at
+; http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt
+; Original content and implementation provided by Silicon Laboratories.
+;------------------------------------------------------------------------------
+;Supported Devices:
+;  EFM8BB10F2G
+;  EFM8BB10F2I
+;  EFM8BB10F2Y
+;  EFM8BB10F4G
+;  EFM8BB10F4I
+;  EFM8BB10F4Y
+;  EFM8BB10F8G
+;  EFM8BB10F8G
+;  EFM8BB10F8G
+;  EFM8BB10F8I
+;  EFM8BB10F8I
+;  EFM8BB10F8I
+;  EFM8BB10F8Y
+;  EFM8BB10F8Y
+;  EFM8BB10F8Y
+
+;-----------------------------------------------------------------------------
+; Register Definitions
+;-----------------------------------------------------------------------------
+ACC      DATA 0E0H; Accumulator                            
+ADC0AC   DATA 0B3H; ADC0 Accumulator Configuration         
+ADC0CF   DATA 0BCH; ADC0 Configuration                     
+ADC0CN0  DATA 0E8H; ADC0 Control 0                         
+ADC0CN1  DATA 0B2H; ADC0 Control 1                         
+ADC0GTH  DATA 0C4H; ADC0 Greater-Than High Byte            
+ADC0GTL  DATA 0C3H; ADC0 Greater-Than Low Byte             
+ADC0H    DATA 0BEH; ADC0 Data Word High Byte               
+ADC0L    DATA 0BDH; ADC0 Data Word Low Byte                
+ADC0LTH  DATA 0C6H; ADC0 Less-Than High Byte               
+ADC0LTL  DATA 0C5H; ADC0 Less-Than Low Byte                
+ADC0MX   DATA 0BBH; ADC0 Multiplexer Selection             
+ADC0PWR  DATA 0DFH; ADC0 Power Control                     
+ADC0TK   DATA 0B9H; ADC0 Burst Mode Track Time             
+B        DATA 0F0H; B Register                             
+CKCON0   DATA 08EH; Clock Control 0                        
+CLKSEL   DATA 0A9H; Clock Select                           
+CMP0CN0  DATA 09BH; Comparator 0 Control 0                 
+CMP0MD   DATA 09DH; Comparator 0 Mode                      
+CMP0MX   DATA 09FH; Comparator 0 Multiplexer Selection     
+CMP1CN0  DATA 0BFH; Comparator 1 Control 0                 
+CMP1MD   DATA 0ABH; Comparator 1 Mode                      
+CMP1MX   DATA 0AAH; Comparator 1 Multiplexer Selection     
+CRC0AUTO DATA 0D2H; CRC0 Automatic Control                 
+CRC0CN0  DATA 0CEH; CRC0 Control 0                         
+CRC0CNT  DATA 0D3H; CRC0 Automatic Flash Sector Count      
+CRC0DAT  DATA 0DEH; CRC0 Data Output                       
+CRC0FLIP DATA 0CFH; CRC0 Bit Flip                          
+CRC0IN   DATA 0DDH; CRC0 Data Input                        
+DERIVID  DATA 0ADH; Derivative Identification              
+DEVICEID DATA 0B5H; Device Identification                  
+DPH      DATA 083H; Data Pointer High                      
+DPL      DATA 082H; Data Pointer Low                       
+EIE1     DATA 0E6H; Extended Interrupt Enable 1            
+EIP1     DATA 0F3H; Extended Interrupt Priority 1          
+FLKEY    DATA 0B7H; Flash Lock and Key                     
+HFO0CAL  DATA 0C7H; High Frequency Oscillator 0 Calibration
+IE       DATA 0A8H; Interrupt Enable                       
+IP       DATA 0B8H; Interrupt Priority                     
+IT01CF   DATA 0E4H; INT0/INT1 Configuration                
+LFO0CN   DATA 0B1H; Low Frequency Oscillator Control       
+P0       DATA 080H; Port 0 Pin Latch                       
+P0MASK   DATA 0FEH; Port 0 Mask                            
+P0MAT    DATA 0FDH; Port 0 Match                           
+P0MDIN   DATA 0F1H; Port 0 Input Mode                      
+P0MDOUT  DATA 0A4H; Port 0 Output Mode                     
+P0SKIP   DATA 0D4H; Port 0 Skip                            
+P1       DATA 090H; Port 1 Pin Latch                       
+P1MASK   DATA 0EEH; Port 1 Mask                            
+P1MAT    DATA 0EDH; Port 1 Match                           
+P1MDIN   DATA 0F2H; Port 1 Input Mode                      
+P1MDOUT  DATA 0A5H; Port 1 Output Mode                     
+P1SKIP   DATA 0D5H; Port 1 Skip                            
+P2       DATA 0A0H; Port 2 Pin Latch                       
+P2MDOUT  DATA 0A6H; Port 2 Output Mode                     
+PCA0CENT DATA 09EH; PCA Center Alignment Enable            
+PCA0CLR  DATA 09CH; PCA Comparator Clear Control           
+PCA0CN0  DATA 0D8H; PCA Control                            
+PCA0CPH0 DATA 0FCH; PCA Channel 0 Capture Module High Byte 
+PCA0CPH1 DATA 0EAH; PCA Channel 1 Capture Module High Byte 
+PCA0CPH2 DATA 0ECH; PCA Channel 2 Capture Module High Byte 
+PCA0CPL0 DATA 0FBH; PCA Channel 0 Capture Module Low Byte  
+PCA0CPL1 DATA 0E9H; PCA Channel 1 Capture Module Low Byte  
+PCA0CPL2 DATA 0EBH; PCA Channel 2 Capture Module Low Byte  
+PCA0CPM0 DATA 0DAH; PCA Channel 0 Capture/Compare Mode     
+PCA0CPM1 DATA 0DBH; PCA Channel 1 Capture/Compare Mode     
+PCA0CPM2 DATA 0DCH; PCA Channel 2 Capture/Compare Mode     
+PCA0H    DATA 0FAH; PCA Counter/Timer High Byte            
+PCA0L    DATA 0F9H; PCA Counter/Timer Low Byte             
+PCA0MD   DATA 0D9H; PCA Mode                               
+PCA0POL  DATA 096H; PCA Output Polarity                    
+PCA0PWM  DATA 0F7H; PCA PWM Configuration                  
+PCON0    DATA 087H; Power Control                          
+PRTDRV   DATA 0F6H; Port Drive Strength                    
+PSCTL    DATA 08FH; Program Store Control                  
+PSW      DATA 0D0H; Program Status Word                    
+REF0CN   DATA 0D1H; Voltage Reference Control              
+REG0CN   DATA 0C9H; Voltage Regulator 0 Control            
+REVID    DATA 0B6H; Revision Identifcation                 
+RSTSRC   DATA 0EFH; Reset Source                           
+SBUF0    DATA 099H; UART0 Serial Port Data Buffer          
+SCON0    DATA 098H; UART0 Serial Port Control              
+SMB0ADM  DATA 0D6H; SMBus 0 Slave Address Mask             
+SMB0ADR  DATA 0D7H; SMBus 0 Slave Address                  
+SMB0CF   DATA 0C1H; SMBus 0 Configuration                  
+SMB0CN0  DATA 0C0H; SMBus 0 Control                        
+SMB0DAT  DATA 0C2H; SMBus 0 Data                           
+SMB0TC   DATA 0ACH; SMBus 0 Timing and Pin Control         
+SP       DATA 081H; Stack Pointer                          
+SPI0CFG  DATA 0A1H; SPI0 Configuration                     
+SPI0CKR  DATA 0A2H; SPI0 Clock Rate                        
+SPI0CN0  DATA 0F8H; SPI0 Control                           
+SPI0DAT  DATA 0A3H; SPI0 Data                              
+TCON     DATA 088H; Timer 0/1 Control                      
+TH0      DATA 08CH; Timer 0 High Byte                      
+TH1      DATA 08DH; Timer 1 High Byte                      
+TL0      DATA 08AH; Timer 0 Low Byte                       
+TL1      DATA 08BH; Timer 1 Low Byte                       
+TMOD     DATA 089H; Timer 0/1 Mode                         
+TMR2CN0  DATA 0C8H; Timer 2 Control 0                      
+TMR2H    DATA 0CDH; Timer 2 High Byte                      
+TMR2L    DATA 0CCH; Timer 2 Low Byte                       
+TMR2RLH  DATA 0CBH; Timer 2 Reload High Byte               
+TMR2RLL  DATA 0CAH; Timer 2 Reload Low Byte                
+TMR3CN0  DATA 091H; Timer 3 Control 0                      
+TMR3H    DATA 095H; Timer 3 High Byte                      
+TMR3L    DATA 094H; Timer 3 Low Byte                       
+TMR3RLH  DATA 093H; Timer 3 Reload High Byte               
+TMR3RLL  DATA 092H; Timer 3 Reload Low Byte                
+VDM0CN   DATA 0FFH; Supply Monitor Control                 
+WDTCN    DATA 097H; Watchdog Timer Control                 
+XBR0     DATA 0E1H; Port I/O Crossbar 0                    
+XBR1     DATA 0E2H; Port I/O Crossbar 1                    
+XBR2     DATA 0E3H; Port I/O Crossbar 2                    
+
+;------------------------------------------------------------------------------
+; 16-bit Register Definitions (may not work on all compilers)
+;------------------------------------------------------------------------------
+ADC0GT  DATA 0C3H ; ADC0 Greater-Than Low Byte           
+ADC0    DATA 0BDH ; ADC0 Data Word Low Byte              
+ADC0LT  DATA 0C5H ; ADC0 Less-Than Low Byte              
+DP      DATA 082H ; Data Pointer Low                     
+PCA0CP0 DATA 0FBH ; PCA Channel 0 Capture Module Low Byte
+PCA0CP1 DATA 0E9H ; PCA Channel 1 Capture Module Low Byte
+PCA0CP2 DATA 0EBH ; PCA Channel 2 Capture Module Low Byte
+PCA0    DATA 0F9H ; PCA Counter/Timer Low Byte           
+TMR2    DATA 0CCH ; Timer 2 Low Byte                     
+TMR2RL  DATA 0CAH ; Timer 2 Reload Low Byte              
+TMR3    DATA 094H ; Timer 3 Low Byte                     
+TMR3RL  DATA 092H ; Timer 3 Reload Low Byte              
+
+;------------------------------------------------------------------------------
+; Indirect Register Definitions
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+; Bit Definitions
+;------------------------------------------------------------------------------
+
+; ACC 0xE0 (Accumulator)
+ACC_ACC0 BIT ACC.0 ; Accumulator Bit 0
+ACC_ACC1 BIT ACC.1 ; Accumulator Bit 1
+ACC_ACC2 BIT ACC.2 ; Accumulator Bit 2
+ACC_ACC3 BIT ACC.3 ; Accumulator Bit 3
+ACC_ACC4 BIT ACC.4 ; Accumulator Bit 4
+ACC_ACC5 BIT ACC.5 ; Accumulator Bit 5
+ACC_ACC6 BIT ACC.6 ; Accumulator Bit 6
+ACC_ACC7 BIT ACC.7 ; Accumulator Bit 7
+
+; ADC0CN0 0xE8 (ADC0 Control 0)
+ADC0CN0_ADCM0  BIT ADC0CN0.0 ; Start of Conversion Mode Select Bit 0
+ADC0CN0_ADCM1  BIT ADC0CN0.1 ; Start of Conversion Mode Select Bit 1
+ADC0CN0_ADCM2  BIT ADC0CN0.2 ; Start of Conversion Mode Select Bit 2
+ADC0CN0_ADWINT BIT ADC0CN0.3 ; Window Compare Interrupt Flag        
+ADC0CN0_ADBUSY BIT ADC0CN0.4 ; ADC Busy                             
+ADC0CN0_ADINT  BIT ADC0CN0.5 ; Conversion Complete Interrupt Flag   
+ADC0CN0_ADBMEN BIT ADC0CN0.6 ; Burst Mode Enable                    
+ADC0CN0_ADEN   BIT ADC0CN0.7 ; ADC Enable                           
+
+; B 0xF0 (B Register)
+B_B0 BIT B.0 ; B Register Bit 0
+B_B1 BIT B.1 ; B Register Bit 1
+B_B2 BIT B.2 ; B Register Bit 2
+B_B3 BIT B.3 ; B Register Bit 3
+B_B4 BIT B.4 ; B Register Bit 4
+B_B5 BIT B.5 ; B Register Bit 5
+B_B6 BIT B.6 ; B Register Bit 6
+B_B7 BIT B.7 ; B Register Bit 7
+
+; IE 0xA8 (Interrupt Enable)
+IE_EX0   BIT IE.0 ; External Interrupt 0 Enable
+IE_ET0   BIT IE.1 ; Timer 0 Interrupt Enable   
+IE_EX1   BIT IE.2 ; External Interrupt 1 Enable
+IE_ET1   BIT IE.3 ; Timer 1 Interrupt Enable   
+IE_ES0   BIT IE.4 ; UART0 Interrupt Enable     
+IE_ET2   BIT IE.5 ; Timer 2 Interrupt Enable   
+IE_ESPI0 BIT IE.6 ; SPI0 Interrupt Enable      
+IE_EA    BIT IE.7 ; All Interrupts Enable      
+
+; IP 0xB8 (Interrupt Priority)
+IP_PX0   BIT IP.0 ; External Interrupt 0 Priority Control                        
+IP_PT0   BIT IP.1 ; Timer 0 Interrupt Priority Control                           
+IP_PX1   BIT IP.2 ; External Interrupt 1 Priority Control                        
+IP_PT1   BIT IP.3 ; Timer 1 Interrupt Priority Control                           
+IP_PS0   BIT IP.4 ; UART0 Interrupt Priority Control                             
+IP_PT2   BIT IP.5 ; Timer 2 Interrupt Priority Control                           
+IP_PSPI0 BIT IP.6 ; Serial Peripheral Interface (SPI0) Interrupt Priority Control
+
+; P0 0x80 (Port 0 Pin Latch)
+P0_B0 BIT P0.0 ; Port 0 Bit 0 Latch
+P0_B1 BIT P0.1 ; Port 0 Bit 1 Latch
+P0_B2 BIT P0.2 ; Port 0 Bit 2 Latch
+P0_B3 BIT P0.3 ; Port 0 Bit 3 Latch
+P0_B4 BIT P0.4 ; Port 0 Bit 4 Latch
+P0_B5 BIT P0.5 ; Port 0 Bit 5 Latch
+P0_B6 BIT P0.6 ; Port 0 Bit 6 Latch
+P0_B7 BIT P0.7 ; Port 0 Bit 7 Latch
+
+; P1 0x90 (Port 1 Pin Latch)
+P1_B0 BIT P1.0 ; Port 1 Bit 0 Latch
+P1_B1 BIT P1.1 ; Port 1 Bit 1 Latch
+P1_B2 BIT P1.2 ; Port 1 Bit 2 Latch
+P1_B3 BIT P1.3 ; Port 1 Bit 3 Latch
+P1_B4 BIT P1.4 ; Port 1 Bit 4 Latch
+P1_B5 BIT P1.5 ; Port 1 Bit 5 Latch
+P1_B6 BIT P1.6 ; Port 1 Bit 6 Latch
+P1_B7 BIT P1.7 ; Port 1 Bit 7 Latch
+
+; P2 0xA0 (Port 2 Pin Latch)
+P2_B0 BIT P2.0 ; Port 2 Bit 0 Latch
+P2_B1 BIT P2.1 ; Port 2 Bit 1 Latch
+
+; PCA0CN0 0xD8 (PCA Control)
+PCA0CN0_CCF0 BIT PCA0CN0.0 ; PCA Module 0 Capture/Compare Flag
+PCA0CN0_CCF1 BIT PCA0CN0.1 ; PCA Module 1 Capture/Compare Flag
+PCA0CN0_CCF2 BIT PCA0CN0.2 ; PCA Module 2 Capture/Compare Flag
+PCA0CN0_CR   BIT PCA0CN0.6 ; PCA Counter/Timer Run Control    
+PCA0CN0_CF   BIT PCA0CN0.7 ; PCA Counter/Timer Overflow Flag  
+
+; PSW 0xD0 (Program Status Word)
+PSW_PARITY BIT PSW.0 ; Parity Flag               
+PSW_F1     BIT PSW.1 ; User Flag 1               
+PSW_OV     BIT PSW.2 ; Overflow Flag             
+PSW_RS0    BIT PSW.3 ; Register Bank Select Bit 0
+PSW_RS1    BIT PSW.4 ; Register Bank Select Bit 1
+PSW_F0     BIT PSW.5 ; User Flag 0               
+PSW_AC     BIT PSW.6 ; Auxiliary Carry Flag      
+PSW_CY     BIT PSW.7 ; Carry Flag                
+
+; SCON0 0x98 (UART0 Serial Port Control)
+SCON0_RI    BIT SCON0.0 ; Receive Interrupt Flag             
+SCON0_TI    BIT SCON0.1 ; Transmit Interrupt Flag            
+SCON0_RB8   BIT SCON0.2 ; Ninth Receive Bit                  
+SCON0_TB8   BIT SCON0.3 ; Ninth Transmission Bit             
+SCON0_REN   BIT SCON0.4 ; Receive Enable                     
+SCON0_MCE   BIT SCON0.5 ; Multiprocessor Communication Enable
+SCON0_SMODE BIT SCON0.7 ; Serial Port 0 Operation Mode       
+
+; SMB0CN0 0xC0 (SMBus 0 Control)
+SMB0CN0_SI      BIT SMB0CN0.0 ; SMBus Interrupt Flag            
+SMB0CN0_ACK     BIT SMB0CN0.1 ; SMBus Acknowledge               
+SMB0CN0_ARBLOST BIT SMB0CN0.2 ; SMBus Arbitration Lost Indicator
+SMB0CN0_ACKRQ   BIT SMB0CN0.3 ; SMBus Acknowledge Request       
+SMB0CN0_STO     BIT SMB0CN0.4 ; SMBus Stop Flag                 
+SMB0CN0_STA     BIT SMB0CN0.5 ; SMBus Start Flag                
+SMB0CN0_TXMODE  BIT SMB0CN0.6 ; SMBus Transmit Mode Indicator   
+SMB0CN0_MASTER  BIT SMB0CN0.7 ; SMBus Master/Slave Indicator    
+
+; SPI0CN0 0xF8 (SPI0 Control)
+SPI0CN0_SPIEN  BIT SPI0CN0.0 ; SPI0 Enable            
+SPI0CN0_TXBMT  BIT SPI0CN0.1 ; Transmit Buffer Empty  
+SPI0CN0_NSSMD0 BIT SPI0CN0.2 ; Slave Select Mode Bit 0
+SPI0CN0_NSSMD1 BIT SPI0CN0.3 ; Slave Select Mode Bit 1
+SPI0CN0_RXOVRN BIT SPI0CN0.4 ; Receive Overrun Flag   
+SPI0CN0_MODF   BIT SPI0CN0.5 ; Mode Fault Flag        
+SPI0CN0_WCOL   BIT SPI0CN0.6 ; Write Collision Flag   
+SPI0CN0_SPIF   BIT SPI0CN0.7 ; SPI0 Interrupt Flag    
+
+; TCON 0x88 (Timer 0/1 Control)
+TCON_IT0 BIT TCON.0 ; Interrupt 0 Type Select
+TCON_IE0 BIT TCON.1 ; External Interrupt 0   
+TCON_IT1 BIT TCON.2 ; Interrupt 1 Type Select
+TCON_IE1 BIT TCON.3 ; External Interrupt 1   
+TCON_TR0 BIT TCON.4 ; Timer 0 Run Control    
+TCON_TF0 BIT TCON.5 ; Timer 0 Overflow Flag  
+TCON_TR1 BIT TCON.6 ; Timer 1 Run Control    
+TCON_TF1 BIT TCON.7 ; Timer 1 Overflow Flag  
+
+; TMR2CN0 0xC8 (Timer 2 Control 0)
+TMR2CN0_T2XCLK  BIT TMR2CN0.0 ; Timer 2 External Clock Select    
+TMR2CN0_TR2     BIT TMR2CN0.2 ; Timer 2 Run Control              
+TMR2CN0_T2SPLIT BIT TMR2CN0.3 ; Timer 2 Split Mode Enable        
+TMR2CN0_TF2CEN  BIT TMR2CN0.4 ; Timer 2 Capture Enable           
+TMR2CN0_TF2LEN  BIT TMR2CN0.5 ; Timer 2 Low Byte Interrupt Enable
+TMR2CN0_TF2L    BIT TMR2CN0.6 ; Timer 2 Low Byte Overflow Flag   
+TMR2CN0_TF2H    BIT TMR2CN0.7 ; Timer 2 High Byte Overflow Flag  
+
+;------------------------------------------------------------------------------
+; Interrupt Definitions
+;------------------------------------------------------------------------------
+INT0_IRQn    EQU 0  ; External Interrupt 0      
+TIMER0_IRQn  EQU 1  ; Timer 0 Overflow          
+INT1_IRQn    EQU 2  ; External Interrupt 1      
+TIMER1_IRQn  EQU 3  ; Timer 1 Overflow          
+UART0_IRQn   EQU 4  ; UART0                     
+TIMER2_IRQn  EQU 5  ; Timer 2 Overflow / Capture
+SPI0_IRQn    EQU 6  ; SPI0                      
+SMBUS0_IRQn  EQU 7  ; SMBus 0                   
+PMATCH_IRQn  EQU 8  ; Port Match                
+ADC0WC_IRQn  EQU 9  ; ADC0 Window Compare       
+ADC0EOC_IRQn EQU 10 ; ADC0 End of Conversion    
+PCA0_IRQn    EQU 11 ; PCA0                      
+CMP0_IRQn    EQU 12 ; Comparator 0              
+CMP1_IRQn    EQU 13 ; Comparator 1              
+TIMER3_IRQn  EQU 14 ; Timer 3 Overflow / Capture

SI_EFM8BB2_Defs.inc

@@ -0,0 +1,431 @@
+;------------------------------------------------------------------------------
+; Copyright 2014 Silicon Laboratories, Inc.
+; All rights reserved. This program and the accompanying materials
+; are made available under the terms of the Silicon Laboratories End User
+; License Agreement which accompanies this distribution, and is available at
+; http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt
+; Original content and implementation provided by Silicon Laboratories.
+;------------------------------------------------------------------------------
+;Supported Devices:
+;  EFM8BB21F16G_QFN20
+;  EFM8BB21F16G_QSOP24
+;  EFM8BB21F16I_QFN20
+;  EFM8BB21F16I_QSOP24
+;  EFM8BB22F16G_QFN28
+;  EFM8BB22F16I_QFN28
+
+;-----------------------------------------------------------------------------
+; Register Definitions
+;-----------------------------------------------------------------------------
+ACC       DATA 0E0H; Accumulator                            
+ADC0AC    DATA 0B3H; ADC0 Accumulator Configuration         
+ADC0CF    DATA 0BCH; ADC0 Configuration                     
+ADC0CN0   DATA 0E8H; ADC0 Control 0                         
+ADC0CN1   DATA 0B2H; ADC0 Control 1                         
+ADC0GTH   DATA 0C4H; ADC0 Greater-Than High Byte            
+ADC0GTL   DATA 0C3H; ADC0 Greater-Than Low Byte             
+ADC0H     DATA 0BEH; ADC0 Data Word High Byte               
+ADC0L     DATA 0BDH; ADC0 Data Word Low Byte                
+ADC0LTH   DATA 0C6H; ADC0 Less-Than High Byte               
+ADC0LTL   DATA 0C5H; ADC0 Less-Than Low Byte                
+ADC0MX    DATA 0BBH; ADC0 Multiplexer Selection             
+ADC0PWR   DATA 0DFH; ADC0 Power Control                     
+ADC0TK    DATA 0B9H; ADC0 Burst Mode Track Time             
+B         DATA 0F0H; B Register                             
+CKCON0    DATA 08EH; Clock Control 0                        
+CKCON1    DATA 0A6H; Clock Control 1
+CLKSEL    DATA 0A9H; Clock Select                           
+CMP0CN0   DATA 09BH; Comparator 0 Control 0                 
+CMP0CN1   DATA 099H; Comparator 0 Control 1
+CMP0MD    DATA 09DH; Comparator 0 Mode                      
+CMP0MX    DATA 09FH; Comparator 0 Multiplexer Selection     
+CMP1CN0   DATA 0BFH; Comparator 1 Control 0                 
+CMP1CN1   DATA 0ACH; Comparator 1 Control 1                 
+CMP1MD    DATA 0ABH; Comparator 1 Mode                      
+CMP1MX    DATA 0AAH; Comparator 1 Multiplexer Selection     
+CRC0CN0   DATA 0CEH; CRC0 Control 0                         
+CRC0CN1   DATA 086H; CRC0 Control 1                         
+CRC0CNT   DATA 0D3H; CRC0 Automatic Flash Sector Count      
+CRC0DAT   DATA 0DEH; CRC0 Data Output                       
+CRC0FLIP  DATA 0CFH; CRC0 Bit Flip                          
+CRC0IN    DATA 0DDH; CRC0 Data Input                        
+CRC0ST    DATA 0D2H; CRC0 Automatic Flash Sector Start      
+DERIVID   DATA 0ADH; Derivative Identification              
+DEVICEID  DATA 0B5H; Device Identification                  
+DPH       DATA 083H; Data Pointer High                      
+DPL       DATA 082H; Data Pointer Low                       
+EIE1      DATA 0E6H; Extended Interrupt Enable 1            
+EIE2      DATA 0CEH; Extended Interrupt Enable 2            
+EIP1      DATA 0F3H; Extended Interrupt Priority 1 Low      
+EIP1H     DATA 0F5H; Extended Interrupt Priority 1 High     
+EIP2      DATA 0F4H; Extended Interrupt Priority 2          
+EIP2H     DATA 0F6H; Extended Interrupt Priority 2 High     
+EMI0CN    DATA 0E7H; External Memory Interface Control      
+FLKEY     DATA 0B7H; Flash Lock and Key                     
+HFO0CAL   DATA 0C7H; High Frequency Oscillator 0 Calibration
+HFO1CAL   DATA 0D6H; High Frequency Oscillator 1 Calibration
+HFOCN     DATA 0EFH; High Frequency Oscillator Control      
+I2C0CN0   DATA 0BAH; I2C0 Control                           
+I2C0DIN   DATA 0BCH; I2C0 Received Data                     
+I2C0DOUT  DATA 0BBH; I2C0 Transmit Data                     
+I2C0FCN0  DATA 0ADH; I2C0 FIFO Control 0                    
+I2C0FCN1  DATA 0ABH; I2C0 FIFO Control 1                    
+I2C0FCT   DATA 0F5H; I2C0 FIFO Count                        
+I2C0SLAD  DATA 0BDH; I2C0 Slave Address                     
+I2C0STAT  DATA 0B9H; I2C0 Status                            
+IE        DATA 0A8H; Interrupt Enable                       
+IP        DATA 0B8H; Interrupt Priority                     
+IPH       DATA 0F2H; Interrupt Priority High                
+IT01CF    DATA 0E4H; INT0/INT1 Configuration                
+LFO0CN    DATA 0B1H; Low Frequency Oscillator Control       
+P0        DATA 080H; Port 0 Pin Latch                       
+P0MASK    DATA 0FEH; Port 0 Mask                            
+P0MAT     DATA 0FDH; Port 0 Match                           
+P0MDIN    DATA 0F1H; Port 0 Input Mode                      
+P0MDOUT   DATA 0A4H; Port 0 Output Mode                     
+P0SKIP    DATA 0D4H; Port 0 Skip                            
+P1        DATA 090H; Port 1 Pin Latch                       
+P1MASK    DATA 0EEH; Port 1 Mask                            
+P1MAT     DATA 0EDH; Port 1 Match                           
+P1MDIN    DATA 0F2H; Port 1 Input Mode                      
+P1MDOUT   DATA 0A5H; Port 1 Output Mode                     
+P1SKIP    DATA 0D5H; Port 1 Skip                            
+P2        DATA 0A0H; Port 2 Pin Latch                       
+P2MASK    DATA 0FCH; Port 2 Mask                            
+P2MAT     DATA 0FBH; Port 2 Match                           
+P2MDIN    DATA 0F3H; Port 2 Input Mode                      
+P2MDOUT   DATA 0A6H; Port 2 Output Mode                     
+P2SKIP    DATA 0CCH; Port 2 Skip                            
+P3        DATA 0B0H; Port 3 Pin Latch                       
+P3MDIN    DATA 0F4H; Port 3 Input Mode                      
+P3MDOUT   DATA 09CH; Port 3 Output Mode                     
+PCA0CENT  DATA 09EH; PCA Center Alignment Enable            
+PCA0CLR   DATA 09CH; PCA Comparator Clear Control           
+PCA0CN0   DATA 0D8H; PCA Control                            
+PCA0CPH0  DATA 0FCH; PCA Channel 0 Capture Module High Byte 
+PCA0CPH1  DATA 0EAH; PCA Channel 1 Capture Module High Byte 
+PCA0CPH2  DATA 0ECH; PCA Channel 2 Capture Module High Byte 
+PCA0CPL0  DATA 0FBH; PCA Channel 0 Capture Module Low Byte  
+PCA0CPL1  DATA 0E9H; PCA Channel 1 Capture Module Low Byte  
+PCA0CPL2  DATA 0EBH; PCA Channel 2 Capture Module Low Byte  
+PCA0CPM0  DATA 0DAH; PCA Channel 0 Capture/Compare Mode     
+PCA0CPM1  DATA 0DBH; PCA Channel 1 Capture/Compare Mode     
+PCA0CPM2  DATA 0DCH; PCA Channel 2 Capture/Compare Mode     
+PCA0H     DATA 0FAH; PCA Counter/Timer High Byte            
+PCA0L     DATA 0F9H; PCA Counter/Timer Low Byte             
+PCA0MD    DATA 0D9H; PCA Mode                               
+PCA0POL   DATA 096H; PCA Output Polarity                    
+PCA0PWM   DATA 0F7H; PCA PWM Configuration                  
+PCON0     DATA 087H; Power Control                          
+PCON1     DATA 09AH; Power Control 1                        
+PFE0CN    DATA 0C1H; Prefetch Engine Control                
+PRTDRV    DATA 0F6H; Port Drive Strength                    
+PSCTL     DATA 08FH; Program Store Control                  
+PSW       DATA 0D0H; Program Status Word                    
+REF0CN    DATA 0D1H; Voltage Reference Control              
+REG0CN    DATA 0C9H; Voltage Regulator 0 Control            
+REG1CN    DATA 0C6H; Voltage Regulator 1 Control            
+REVID     DATA 0B6H; Revision Identifcation                 
+RSTSRC    DATA 0EFH; Reset Source                           
+SBCON1    DATA 094H; UART1 Baud Rate Generator Control      
+SBRLH1    DATA 096H; UART1 Baud Rate Generator High Byte    
+SBRLL1    DATA 095H; UART1 Baud Rate Generator Low Byte     
+SBUF0     DATA 099H; UART0 Serial Port Data Buffer          
+SBUF1     DATA 092H; UART1 Serial Port Data Buffer          
+SCON0     DATA 098H; UART0 Serial Port Control              
+SCON1     DATA 0C8H; UART1 Serial Port Control              
+SFRPAGE   DATA 0A7H; SFR Page                               
+SFRPGCN   DATA 0CFH; SFR Page Control                       
+SFRSTACK  DATA 0D7H; SFR Page Stack                         
+SMB0ADM   DATA 0D6H; SMBus 0 Slave Address Mask             
+SMB0ADR   DATA 0D7H; SMBus 0 Slave Address                  
+SMB0CF    DATA 0C1H; SMBus 0 Configuration                  
+SMB0CN0   DATA 0C0H; SMBus 0 Control                        
+SMB0DAT   DATA 0C2H; SMBus 0 Data                           
+SMB0FCN0  DATA 0C3H; SMBus 0 FIFO Control 0                 
+SMB0FCN1  DATA 0C4H; SMBus 0 FIFO Control 1                 
+SMB0FCT   DATA 0EFH; SMBus 0 FIFO Count                     
+SMB0RXLN  DATA 0C5H; SMBus 0 Receive Length Counter         
+SMB0TC    DATA 0ACH; SMBus 0 Timing and Pin Control         
+SMOD1     DATA 093H; UART1 Mode                             
+SP        DATA 081H; Stack Pointer                          
+SPI0CFG   DATA 0A1H; SPI0 Configuration                     
+SPI0CKR   DATA 0A2H; SPI0 Clock Rate                        
+SPI0CN0   DATA 0F8H; SPI0 Control                           
+SPI0DAT   DATA 0A3H; SPI0 Data                              
+SPI0FCN0  DATA 09AH; SPI0 FIFO Control 0                    
+SPI0FCN1  DATA 09BH; SPI0 FIFO Control 1                    
+SPI0FCT   DATA 0F7H; SPI0 FIFO Count                        
+TCON      DATA 088H; Timer 0/1 Control                      
+TH0       DATA 08CH; Timer 0 High Byte                      
+TH1       DATA 08DH; Timer 1 High Byte                      
+TL0       DATA 08AH; Timer 0 Low Byte                       
+TL1       DATA 08BH; Timer 1 Low Byte                       
+TMOD      DATA 089H; Timer 0/1 Mode                         
+TMR2CN0   DATA 0C8H; Timer 2 Control 0                      
+TMR2CN1   DATA 0FDH; Timer 2 Control 1                      
+TMR2H     DATA 0CDH; Timer 2 High Byte                      
+TMR2L     DATA 0CCH; Timer 2 Low Byte                       
+TMR2RLH   DATA 0CBH; Timer 2 Reload High Byte               
+TMR2RLL   DATA 0CAH; Timer 2 Reload Low Byte                
+TMR3CN0   DATA 091H; Timer 3 Control 0                      
+TMR3CN1   DATA 0FEH; Timer 3 Control 1                      
+TMR3H     DATA 095H; Timer 3 High Byte                      
+TMR3L     DATA 094H; Timer 3 Low Byte                       
+TMR3RLH   DATA 093H; Timer 3 Reload High Byte               
+TMR3RLL   DATA 092H; Timer 3 Reload Low Byte                
+TMR4CN0   DATA 098H; Timer 4 Control 0                      
+TMR4CN1   DATA 0FFH; Timer 4 Control 1                      
+TMR4H     DATA 0A5H; Timer 4 High Byte                      
+TMR4L     DATA 0A4H; Timer 4 Low Byte                       
+TMR4RLH   DATA 0A3H; Timer 4 Reload High Byte               
+TMR4RLL   DATA 0A2H; Timer 4 Reload Low Byte                
+UART1FCN0 DATA 09DH; UART1 FIFO Control 0                   
+UART1FCN1 DATA 0D8H; UART1 FIFO Control 1                   
+UART1FCT  DATA 0FAH; UART1 FIFO Count                       
+UART1LIN  DATA 09EH; UART1 LIN Configuration                
+VDM0CN    DATA 0FFH; Supply Monitor Control                 
+WDTCN     DATA 097H; Watchdog Timer Control                 
+XBR0      DATA 0E1H; Port I/O Crossbar 0                    
+XBR1      DATA 0E2H; Port I/O Crossbar 1                    
+XBR2      DATA 0E3H; Port I/O Crossbar 2                    
+
+;------------------------------------------------------------------------------
+; 16-bit Register Definitions (may not work on all compilers)
+;------------------------------------------------------------------------------
+ADC0GT  DATA 0C3H ; ADC0 Greater-Than Low Byte           
+ADC0    DATA 0BDH ; ADC0 Data Word Low Byte              
+ADC0LT  DATA 0C5H ; ADC0 Less-Than Low Byte              
+DP      DATA 082H ; Data Pointer Low                     
+PCA0CP0 DATA 0FBH ; PCA Channel 0 Capture Module Low Byte
+PCA0CP1 DATA 0E9H ; PCA Channel 1 Capture Module Low Byte
+PCA0CP2 DATA 0EBH ; PCA Channel 2 Capture Module Low Byte
+PCA0    DATA 0F9H ; PCA Counter/Timer Low Byte           
+SBRL1   DATA 095H ; UART1 Baud Rate Generator Low Byte   
+TMR2    DATA 0CCH ; Timer 2 Low Byte                     
+TMR2RL  DATA 0CAH ; Timer 2 Reload Low Byte              
+TMR3    DATA 094H ; Timer 3 Low Byte                     
+TMR3RL  DATA 092H ; Timer 3 Reload Low Byte              
+TMR4    DATA 0A4H ; Timer 4 Low Byte                     
+TMR4RL  DATA 0A2H ; Timer 4 Reload Low Byte              
+
+;------------------------------------------------------------------------------
+; Indirect Register Definitions
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+; Bit Definitions
+;------------------------------------------------------------------------------
+
+; ACC 0xE0 (Accumulator)
+ACC_ACC0 BIT ACC.0 ; Accumulator Bit 0
+ACC_ACC1 BIT ACC.1 ; Accumulator Bit 1
+ACC_ACC2 BIT ACC.2 ; Accumulator Bit 2
+ACC_ACC3 BIT ACC.3 ; Accumulator Bit 3
+ACC_ACC4 BIT ACC.4 ; Accumulator Bit 4
+ACC_ACC5 BIT ACC.5 ; Accumulator Bit 5
+ACC_ACC6 BIT ACC.6 ; Accumulator Bit 6
+ACC_ACC7 BIT ACC.7 ; Accumulator Bit 7
+
+; ADC0CN0 0xE8 (ADC0 Control 0)
+ADC0CN0_ADCM0  BIT ADC0CN0.0 ; Start of Conversion Mode Select Bit 0
+ADC0CN0_ADCM1  BIT ADC0CN0.1 ; Start of Conversion Mode Select Bit 1
+ADC0CN0_ADCM2  BIT ADC0CN0.2 ; Start of Conversion Mode Select Bit 2
+ADC0CN0_ADWINT BIT ADC0CN0.3 ; Window Compare Interrupt Flag        
+ADC0CN0_ADBUSY BIT ADC0CN0.4 ; ADC Busy                             
+ADC0CN0_ADINT  BIT ADC0CN0.5 ; Conversion Complete Interrupt Flag   
+ADC0CN0_ADBMEN BIT ADC0CN0.6 ; Burst Mode Enable                    
+ADC0CN0_ADEN   BIT ADC0CN0.7 ; ADC Enable                           
+
+; B 0xF0 (B Register)
+B_B0 BIT B.0 ; B Register Bit 0
+B_B1 BIT B.1 ; B Register Bit 1
+B_B2 BIT B.2 ; B Register Bit 2
+B_B3 BIT B.3 ; B Register Bit 3
+B_B4 BIT B.4 ; B Register Bit 4
+B_B5 BIT B.5 ; B Register Bit 5
+B_B6 BIT B.6 ; B Register Bit 6
+B_B7 BIT B.7 ; B Register Bit 7
+
+; IE 0xA8 (Interrupt Enable)
+IE_EX0   BIT IE.0 ; External Interrupt 0 Enable
+IE_ET0   BIT IE.1 ; Timer 0 Interrupt Enable   
+IE_EX1   BIT IE.2 ; External Interrupt 1 Enable
+IE_ET1   BIT IE.3 ; Timer 1 Interrupt Enable   
+IE_ES0   BIT IE.4 ; UART0 Interrupt Enable     
+IE_ET2   BIT IE.5 ; Timer 2 Interrupt Enable   
+IE_ESPI0 BIT IE.6 ; SPI0 Interrupt Enable      
+IE_EA    BIT IE.7 ; All Interrupts Enable      
+
+; IP 0xB8 (Interrupt Priority)
+IP_PX0   BIT IP.0 ; External Interrupt 0 Priority Control LSB                        
+IP_PT0   BIT IP.1 ; Timer 0 Interrupt Priority Control LSB                           
+IP_PX1   BIT IP.2 ; External Interrupt 1 Priority Control LSB                        
+IP_PT1   BIT IP.3 ; Timer 1 Interrupt Priority Control LSB                           
+IP_PS0   BIT IP.4 ; UART0 Interrupt Priority Control LSB                             
+IP_PT2   BIT IP.5 ; Timer 2 Interrupt Priority Control LSB                           
+IP_PSPI0 BIT IP.6 ; Serial Peripheral Interface (SPI0) Interrupt Priority Control LSB
+
+; P0 0x80 (Port 0 Pin Latch)
+P0_B0 BIT P0.0 ; Port 0 Bit 0 Latch
+P0_B1 BIT P0.1 ; Port 0 Bit 1 Latch
+P0_B2 BIT P0.2 ; Port 0 Bit 2 Latch
+P0_B3 BIT P0.3 ; Port 0 Bit 3 Latch
+P0_B4 BIT P0.4 ; Port 0 Bit 4 Latch
+P0_B5 BIT P0.5 ; Port 0 Bit 5 Latch
+P0_B6 BIT P0.6 ; Port 0 Bit 6 Latch
+P0_B7 BIT P0.7 ; Port 0 Bit 7 Latch
+
+; P1 0x90 (Port 1 Pin Latch)
+P1_B0 BIT P1.0 ; Port 1 Bit 0 Latch
+P1_B1 BIT P1.1 ; Port 1 Bit 1 Latch
+P1_B2 BIT P1.2 ; Port 1 Bit 2 Latch
+P1_B3 BIT P1.3 ; Port 1 Bit 3 Latch
+P1_B4 BIT P1.4 ; Port 1 Bit 4 Latch
+P1_B5 BIT P1.5 ; Port 1 Bit 5 Latch
+P1_B6 BIT P1.6 ; Port 1 Bit 6 Latch
+P1_B7 BIT P1.7 ; Port 1 Bit 7 Latch
+
+; P2 0xA0 (Port 2 Pin Latch)
+P2_B0 BIT P2.0 ; Port 2 Bit 0 Latch
+P2_B1 BIT P2.1 ; Port 2 Bit 1 Latch
+P2_B2 BIT P2.2 ; Port 2 Bit 2 Latch
+P2_B3 BIT P2.3 ; Port 2 Bit 3 Latch
+
+; P3 0xB0 (Port 3 Pin Latch)
+P3_B0 BIT P3.0 ; Port 3 Bit 0 Latch
+P3_B1 BIT P3.1 ; Port 3 Bit 1 Latch
+
+; PCA0CN0 0xD8 (PCA Control)
+PCA0CN0_CCF0 BIT PCA0CN0.0 ; PCA Module 0 Capture/Compare Flag
+PCA0CN0_CCF1 BIT PCA0CN0.1 ; PCA Module 1 Capture/Compare Flag
+PCA0CN0_CCF2 BIT PCA0CN0.2 ; PCA Module 2 Capture/Compare Flag
+PCA0CN0_CR   BIT PCA0CN0.6 ; PCA Counter/Timer Run Control    
+PCA0CN0_CF   BIT PCA0CN0.7 ; PCA Counter/Timer Overflow Flag  
+
+; PSW 0xD0 (Program Status Word)
+PSW_PARITY BIT PSW.0 ; Parity Flag               
+PSW_F1     BIT PSW.1 ; User Flag 1               
+PSW_OV     BIT PSW.2 ; Overflow Flag             
+PSW_RS0    BIT PSW.3 ; Register Bank Select Bit 0
+PSW_RS1    BIT PSW.4 ; Register Bank Select Bit 1
+PSW_F0     BIT PSW.5 ; User Flag 0               
+PSW_AC     BIT PSW.6 ; Auxiliary Carry Flag      
+PSW_CY     BIT PSW.7 ; Carry Flag                
+
+; SCON0 0x98 (UART0 Serial Port Control)
+SCON0_RI    BIT SCON0.0 ; Receive Interrupt Flag             
+SCON0_TI    BIT SCON0.1 ; Transmit Interrupt Flag            
+SCON0_RB8   BIT SCON0.2 ; Ninth Receive Bit                  
+SCON0_TB8   BIT SCON0.3 ; Ninth Transmission Bit             
+SCON0_REN   BIT SCON0.4 ; Receive Enable                     
+SCON0_MCE   BIT SCON0.5 ; Multiprocessor Communication Enable
+SCON0_SMODE BIT SCON0.7 ; Serial Port 0 Operation Mode       
+
+; SCON1 0xC8 (UART1 Serial Port Control)
+SCON1_RI   BIT SCON1.0 ; Receive Interrupt Flag   
+SCON1_TI   BIT SCON1.1 ; Transmit Interrupt Flag  
+SCON1_RBX  BIT SCON1.2 ; Extra Receive Bit        
+SCON1_TBX  BIT SCON1.3 ; Extra Transmission Bit   
+SCON1_REN  BIT SCON1.4 ; Receive Enable           
+SCON1_PERR BIT SCON1.6 ; Parity Error Flag        
+SCON1_OVR  BIT SCON1.7 ; Receive FIFO Overrun Flag
+
+; SMB0CN0 0xC0 (SMBus 0 Control)
+SMB0CN0_SI      BIT SMB0CN0.0 ; SMBus Interrupt Flag            
+SMB0CN0_ACK     BIT SMB0CN0.1 ; SMBus Acknowledge               
+SMB0CN0_ARBLOST BIT SMB0CN0.2 ; SMBus Arbitration Lost Indicator
+SMB0CN0_ACKRQ   BIT SMB0CN0.3 ; SMBus Acknowledge Request       
+SMB0CN0_STO     BIT SMB0CN0.4 ; SMBus Stop Flag                 
+SMB0CN0_STA     BIT SMB0CN0.5 ; SMBus Start Flag                
+SMB0CN0_TXMODE  BIT SMB0CN0.6 ; SMBus Transmit Mode Indicator   
+SMB0CN0_MASTER  BIT SMB0CN0.7 ; SMBus Master/Slave Indicator    
+
+; SPI0CN0 0xF8 (SPI0 Control)
+SPI0CN0_SPIEN  BIT SPI0CN0.0 ; SPI0 Enable            
+SPI0CN0_TXNF   BIT SPI0CN0.1 ; TX FIFO Not Full       
+SPI0CN0_NSSMD0 BIT SPI0CN0.2 ; Slave Select Mode Bit 0
+SPI0CN0_NSSMD1 BIT SPI0CN0.3 ; Slave Select Mode Bit 1
+SPI0CN0_RXOVRN BIT SPI0CN0.4 ; Receive Overrun Flag   
+SPI0CN0_MODF   BIT SPI0CN0.5 ; Mode Fault Flag        
+SPI0CN0_WCOL   BIT SPI0CN0.6 ; Write Collision Flag   
+SPI0CN0_SPIF   BIT SPI0CN0.7 ; SPI0 Interrupt Flag    
+
+; TCON 0x88 (Timer 0/1 Control)
+TCON_IT0 BIT TCON.0 ; Interrupt 0 Type Select
+TCON_IE0 BIT TCON.1 ; External Interrupt 0   
+TCON_IT1 BIT TCON.2 ; Interrupt 1 Type Select
+TCON_IE1 BIT TCON.3 ; External Interrupt 1   
+TCON_TR0 BIT TCON.4 ; Timer 0 Run Control    
+TCON_TF0 BIT TCON.5 ; Timer 0 Overflow Flag  
+TCON_TR1 BIT TCON.6 ; Timer 1 Run Control    
+TCON_TF1 BIT TCON.7 ; Timer 1 Overflow Flag  
+
+; TMR2CN0 0xC8 (Timer 2 Control 0)
+TMR2CN0_T2XCLK0 BIT TMR2CN0.0 ; Timer 2 External Clock Select Bit 0
+TMR2CN0_T2XCLK1 BIT TMR2CN0.1 ; Timer 2 External Clock Select Bit 1
+TMR2CN0_TR2     BIT TMR2CN0.2 ; Timer 2 Run Control                
+TMR2CN0_T2SPLIT BIT TMR2CN0.3 ; Timer 2 Split Mode Enable          
+TMR2CN0_TF2CEN  BIT TMR2CN0.4 ; Timer 2 Capture Enable             
+TMR2CN0_TF2LEN  BIT TMR2CN0.5 ; Timer 2 Low Byte Interrupt Enable  
+TMR2CN0_TF2L    BIT TMR2CN0.6 ; Timer 2 Low Byte Overflow Flag     
+TMR2CN0_TF2H    BIT TMR2CN0.7 ; Timer 2 High Byte Overflow Flag    
+
+; TMR4CN0 0x98 (Timer 4 Control 0)
+TMR4CN0_T4XCLK0 BIT TMR4CN0.0 ; Timer 4 External Clock Select Bit 0
+TMR4CN0_T4XCLK1 BIT TMR4CN0.1 ; Timer 4 External Clock Select Bit 1
+TMR4CN0_TR4     BIT TMR4CN0.2 ; Timer 4 Run Control                
+TMR4CN0_T4SPLIT BIT TMR4CN0.3 ; Timer 4 Split Mode Enable          
+TMR4CN0_TF4CEN  BIT TMR4CN0.4 ; Timer 4 Capture Enable             
+TMR4CN0_TF4LEN  BIT TMR4CN0.5 ; Timer 4 Low Byte Interrupt Enable  
+TMR4CN0_TF4L    BIT TMR4CN0.6 ; Timer 4 Low Byte Overflow Flag     
+TMR4CN0_TF4H    BIT TMR4CN0.7 ; Timer 4 High Byte Overflow Flag    
+
+; UART1FCN1 0xD8 (UART1 FIFO Control 1)
+UART1FCN1_RIE    BIT UART1FCN1.0 ; Receive Interrupt Enable 
+UART1FCN1_RXTO0  BIT UART1FCN1.1 ; Receive Timeout Bit 0    
+UART1FCN1_RXTO1  BIT UART1FCN1.2 ; Receive Timeout Bit 1    
+UART1FCN1_RFRQ   BIT UART1FCN1.3 ; Receive FIFO Request     
+UART1FCN1_TIE    BIT UART1FCN1.4 ; Transmit Interrupt Enable
+UART1FCN1_TXHOLD BIT UART1FCN1.5 ; Transmit Hold            
+UART1FCN1_TXNF   BIT UART1FCN1.6 ; TX FIFO Not Full         
+UART1FCN1_TFRQ   BIT UART1FCN1.7 ; Transmit FIFO Request    
+
+;------------------------------------------------------------------------------
+; Interrupt Definitions
+;------------------------------------------------------------------------------
+INT0_IRQn    EQU 0  ; External Interrupt 0      
+TIMER0_IRQn  EQU 1  ; Timer 0 Overflow          
+INT1_IRQn    EQU 2  ; External Interrupt 1      
+TIMER1_IRQn  EQU 3  ; Timer 1 Overflow          
+UART0_IRQn   EQU 4  ; UART0                     
+TIMER2_IRQn  EQU 5  ; Timer 2 Overflow / Capture
+SPI0_IRQn    EQU 6  ; SPI0                      
+SMBUS0_IRQn  EQU 7  ; SMBus 0                   
+PMATCH_IRQn  EQU 8  ; Port Match                
+ADC0WC_IRQn  EQU 9  ; ADC0 Window Compare       
+ADC0EOC_IRQn EQU 10 ; ADC0 End of Conversion    
+PCA0_IRQn    EQU 11 ; PCA0                      
+CMP0_IRQn    EQU 12 ; Comparator 0              
+CMP1_IRQn    EQU 13 ; Comparator 1              
+TIMER3_IRQn  EQU 14 ; Timer 3 Overflow / Capture
+UART1_IRQn   EQU 17 ; UART1                     
+I2C0_IRQn    EQU 18 ; I2C0 Slave                
+TIMER4_IRQn  EQU 19 ; Timer 4 Overflow / Capture
+
+;------------------------------------------------------------------------------
+; SFR Page Definitions
+;------------------------------------------------------------------------------
+CRC0_PAGE       EQU 000H ; CRC0 Page       
+LEGACY_PAGE     EQU 000H ; Legacy SFR Page 
+PCA0_PAGE       EQU 000H ; PCA0 Page       
+PG2_PAGE        EQU 010H ; Page2           
+TIMER2_PAGE     EQU 010H ; Timer 2 Page    
+TIMER3_PAGE     EQU 010H ; Timer 3 Page    
+TIMER4_PAGE     EQU 010H ; Timer 4 Page    
+I2CSLAVE0_PAGE  EQU 020H ; I2C Slave 0 Page
+PG3_PAGE        EQU 020H ; Page3           
+SMB0_PAGE       EQU 020H ; SMBus 0 Page    
+SPI0_PAGE       EQU 020H ; SPI0 Page       
+UART0_PAGE      EQU 020H ; UART0 Page      
+UART1_PAGE      EQU 020H ; UART1 Page      

SI_EFM8LB1_Defs.inc

@@ -0,0 +1,558 @@
+;------------------------------------------------------------------------------
+; Copyright 2014 Silicon Laboratories, Inc.
+; All rights reserved. This program and the accompanying materials
+; are made available under the terms of the Silicon Laboratories End User
+; License Agreement which accompanies this distribution, and is available at
+; http://developer.silabs.com/legal/version/v11/Silicon_Labs_Software_License_Agreement.txt
+; Original content and implementation provided by Silicon Laboratories.
+;------------------------------------------------------------------------------
+;Supported Devices:
+;  EFM8LB10F16E_QFN24
+;  EFM8LB10F16E_QFN32
+;  EFM8LB10F16E_QFP32
+;  EFM8LB10F16E_QSOP24
+;  EFM8LB10F16ES0_QFN24
+;  EFM8LB10F16ES0_QFN32
+;  EFM8LB11F16E_QFN24
+;  EFM8LB11F16E_QFN32
+;  EFM8LB11F16E_QFP32
+;  EFM8LB11F16E_QSOP24
+;  EFM8LB11F16ES0_QFN24
+;  EFM8LB11F16ES0_QFN32
+;  EFM8LB11F32E_QFN24
+;  EFM8LB11F32E_QFN32
+;  EFM8LB11F32E_QFP32
+;  EFM8LB11F32E_QSOP24
+;  EFM8LB11F32ES0_QFN24
+;  EFM8LB11F32ES0_QFN32
+;  EFM8LB12F32E_QFN24
+;  EFM8LB12F32E_QFN32
+;  EFM8LB12F32E_QFP32
+;  EFM8LB12F32E_QSOP24
+;  EFM8LB12F32ES0_QFN24
+;  EFM8LB12F32ES0_QFN32
+;  EFM8LB12F64E_QFN24
+;  EFM8LB12F64E_QFN32
+;  EFM8LB12F64E_QFP32
+;  EFM8LB12F64E_QSOP24
+;  EFM8LB12F64ES0_QFN24
+;  EFM8LB12F64ES0_QFN32
+
+;-----------------------------------------------------------------------------
+; Register Definitions
+;-----------------------------------------------------------------------------
+ACC       DATA 0E0H; Accumulator                              
+ADC0ASAH  DATA 0B6H; ADC0 Autoscan Start Address High Byte    
+ADC0ASAL  DATA 0B5H; ADC0 Autoscan Start Address Low Byte     
+ADC0ASCF  DATA 0A1H; ADC0 Autoscan Configuration              
+ADC0ASCT  DATA 0C7H; ADC0 Autoscan Output Count               
+ADC0CF0   DATA 0BCH; ADC0 Configuration                       
+ADC0CF1   DATA 0B9H; ADC0 Configuration                       
+ADC0CF2   DATA 0DFH; ADC0 Power Control                       
+ADC0CN0   DATA 0E8H; ADC0 Control 0                           
+ADC0CN1   DATA 0B2H; ADC0 Control 1                           
+ADC0CN2   DATA 0B3H; ADC0 Control 2                           
+ADC0GTH   DATA 0C4H; ADC0 Greater-Than High Byte              
+ADC0GTL   DATA 0C3H; ADC0 Greater-Than Low Byte               
+ADC0H     DATA 0BEH; ADC0 Data Word High Byte                 
+ADC0L     DATA 0BDH; ADC0 Data Word Low Byte                  
+ADC0LTH   DATA 0C6H; ADC0 Less-Than High Byte                 
+ADC0LTL   DATA 0C5H; ADC0 Less-Than Low Byte                  
+ADC0MX    DATA 0BBH; ADC0 Multiplexer Selection               
+B         DATA 0F0H; B Register                               
+CKCON0    DATA 08EH; Clock Control 0                          
+CKCON1    DATA 0A6H; Clock Control 1                          
+CLEN0     DATA 0C6H; Configurable Logic Enable 0              
+CLIE0     DATA 0C7H; Configurable Logic Interrupt Enable 0    
+CLIF0     DATA 0E8H; Configurable Logic Interrupt Flag 0      
+CLKSEL    DATA 0A9H; Clock Select                             
+CLOUT0    DATA 0D1H; Configurable Logic Output 0              
+CLU0CF    DATA 0B1H; Configurable Logic Unit 0 Configuration  
+CLU0FN    DATA 0AFH; Configurable Logic Unit 0 Function Select
+CLU0MX    DATA 084H; Configurable Logic Unit 0 Multiplexer    
+CLU1CF    DATA 0B3H; Configurable Logic Unit 1 Configuration  
+CLU1FN    DATA 0B2H; Configurable Logic Unit 1 Function Select
+CLU1MX    DATA 085H; Configurable Logic Unit 1 Multiplexer    
+CLU2CF    DATA 0B6H; Configurable Logic Unit 2 Configuration  
+CLU2FN    DATA 0B5H; Configurable Logic Unit 2 Function Select
+CLU2MX    DATA 091H; Configurable Logic Unit 2 Multiplexer    
+CLU3CF    DATA 0BFH; Configurable Logic Unit 3 Configuration  
+CLU3FN    DATA 0BEH; Configurable Logic Unit 3 Function Select
+CLU3MX    DATA 0AEH; Configurable Logic Unit 3 Multiplexer    
+CMP0CN0   DATA 09BH; Comparator 0 Control 0                   
+CMP0CN1   DATA 099H; Comparator 0 Control 1                   
+CMP0MD    DATA 09DH; Comparator 0 Mode                        
+CMP0MX    DATA 09FH; Comparator 0 Multiplexer Selection       
+CMP1CN0   DATA 0BFH; Comparator 1 Control 0                   
+CMP1CN1   DATA 0ACH; Comparator 1 Control 1                   
+CMP1MD    DATA 0ABH; Comparator 1 Mode                        
+CMP1MX    DATA 0AAH; Comparator 1 Multiplexer Selection       
+CRC0CN0   DATA 0CEH; CRC0 Control 0                           
+CRC0CN1   DATA 086H; CRC0 Control 1                           
+CRC0CNT   DATA 0D3H; CRC0 Automatic Flash Sector Count        
+CRC0DAT   DATA 0CBH; CRC0 Data Output                         
+CRC0FLIP  DATA 0CFH; CRC0 Bit Flip                            
+CRC0IN    DATA 0CAH; CRC0 Data Input                          
+CRC0ST    DATA 0D2H; CRC0 Automatic Flash Sector Start        
+DAC0CF0   DATA 091H; DAC0 Configuration 0                     
+DAC0CF1   DATA 092H; DAC0 Configuration 1                     
+DAC0H     DATA 085H; DAC0 Data Word High Byte                 
+DAC0L     DATA 084H; DAC0 Data Word Low Byte                  
+DAC1CF0   DATA 093H; DAC1 Configuration 0                     
+DAC1CF1   DATA 094H; DAC1 Configuration 1                     
+DAC1H     DATA 08AH; DAC1 Data Word High Byte                 
+DAC1L     DATA 089H; DAC1 Data Word Low Byte                  
+DAC2CF0   DATA 095H; DAC2 Configuration 0                     
+DAC2CF1   DATA 096H; DAC2 Configuration 1                     
+DAC2H     DATA 08CH; DAC2 Data Word High Byte                 
+DAC2L     DATA 08BH; DAC2 Data Word Low Byte                  
+DAC3CF0   DATA 09AH; DAC3 Configuration 0                     
+DAC3CF1   DATA 09CH; DAC3 Configuration 1                     
+DAC3H     DATA 08EH; DAC3 Data Word High Byte                 
+DAC3L     DATA 08DH; DAC3 Data Word Low Byte                  
+DACGCF0   DATA 088H; DAC Global Configuration 0               
+DACGCF1   DATA 098H; DAC Global Configuration 1               
+DACGCF2   DATA 0A2H; DAC Global Configuration 2               
+DERIVID   DATA 0ADH; Derivative Identification                
+DEVICEID  DATA 0B5H; Device Identification                    
+DPH       DATA 083H; Data Pointer High                        
+DPL       DATA 082H; Data Pointer Low                         
+EIE1      DATA 0E6H; Extended Interrupt Enable 1              
+EIE2      DATA 0F3H; Extended Interrupt Enable 2              
+EIP1      DATA 0BBH; Extended Interrupt Priority 1 Low        
+EIP1H     DATA 0EEH; Extended Interrupt Priority 1 High       
+EIP2      DATA 0EDH; Extended Interrupt Priority 2            
+EIP2H     DATA 0F6H; Extended Interrupt Priority 2 High       
+EMI0CN    DATA 0E7H; External Memory Interface Control        
+FLKEY     DATA 0B7H; Flash Lock and Key                       
+HFO0CAL   DATA 0C7H; High Frequency Oscillator 0 Calibration  
+HFO1CAL   DATA 0D6H; High Frequency Oscillator 1 Calibration  
+HFOCN     DATA 0EFH; High Frequency Oscillator Control        
+I2C0ADM   DATA 0FFH; I2C0 Slave Address Mask                  
+I2C0CN0   DATA 0BAH; I2C0 Control                             
+I2C0DIN   DATA 0BCH; I2C0 Received Data                       
+I2C0DOUT  DATA 0BBH; I2C0 Transmit Data                       
+I2C0FCN0  DATA 0ADH; I2C0 FIFO Control 0                      
+I2C0FCN1  DATA 0ABH; I2C0 FIFO Control 1                      
+I2C0FCT   DATA 0F5H; I2C0 FIFO Count                          
+I2C0SLAD  DATA 0BDH; I2C0 Slave Address                       
+I2C0STAT  DATA 0B9H; I2C0 Status                              
+IE        DATA 0A8H; Interrupt Enable                         
+IP        DATA 0B8H; Interrupt Priority                       
+IPH       DATA 0F2H; Interrupt Priority High                  
+IT01CF    DATA 0E4H; INT0/INT1 Configuration                  
+LFO0CN    DATA 0B1H; Low Frequency Oscillator Control         
+P0        DATA 080H; Port 0 Pin Latch                         
+P0MASK    DATA 0FEH; Port 0 Mask                              
+P0MAT     DATA 0FDH; Port 0 Match                             
+P0MDIN    DATA 0F1H; Port 0 Input Mode                        
+P0MDOUT   DATA 0A4H; Port 0 Output Mode                       
+P0SKIP    DATA 0D4H; Port 0 Skip                              
+P1        DATA 090H; Port 1 Pin Latch                         
+P1MASK    DATA 0EEH; Port 1 Mask                              
+P1MAT     DATA 0EDH; Port 1 Match                             
+P1MDIN    DATA 0F2H; Port 1 Input Mode                        
+P1MDOUT   DATA 0A5H; Port 1 Output Mode                       
+P1SKIP    DATA 0D5H; Port 1 Skip                              
+P2        DATA 0A0H; Port 2 Pin Latch                         
+P2MASK    DATA 0FCH; Port 2 Mask                              
+P2MAT     DATA 0FBH; Port 2 Match                             
+P2MDIN    DATA 0F3H; Port 2 Input Mode                        
+P2MDOUT   DATA 0A6H; Port 2 Output Mode                       
+P2SKIP    DATA 0CCH; Port 2 Skip                              
+P3        DATA 0B0H; Port 3 Pin Latch                         
+P3MDIN    DATA 0F4H; Port 3 Input Mode                        
+P3MDOUT   DATA 09CH; Port 3 Output Mode                       
+PCA0CENT  DATA 09EH; PCA Center Alignment Enable              
+PCA0CLR   DATA 09CH; PCA Comparator Clear Control             
+PCA0CN0   DATA 0D8H; PCA Control                              
+PCA0CPH0  DATA 0FCH; PCA Channel 0 Capture Module High Byte   
+PCA0CPH1  DATA 0EAH; PCA Channel 1 Capture Module High Byte   
+PCA0CPH2  DATA 0ECH; PCA Channel 2 Capture Module High Byte   
+PCA0CPH3  DATA 0F5H; PCA Channel 3 Capture Module High Byte   
+PCA0CPH4  DATA 085H; PCA Channel 4 Capture Module High Byte   
+PCA0CPH5  DATA 0DEH; PCA Channel 5 Capture Module High Byte   
+PCA0CPL0  DATA 0FBH; PCA Channel 0 Capture Module Low Byte    
+PCA0CPL1  DATA 0E9H; PCA Channel 1 Capture Module Low Byte    
+PCA0CPL2  DATA 0EBH; PCA Channel 2 Capture Module Low Byte    
+PCA0CPL3  DATA 0F4H; PCA Channel 3 Capture Module Low Byte    
+PCA0CPL4  DATA 084H; PCA Channel 4 Capture Module Low Byte    
+PCA0CPL5  DATA 0DDH; PCA Channel 5 Capture Module Low Byte    
+PCA0CPM0  DATA 0DAH; PCA Channel 0 Capture/Compare Mode       
+PCA0CPM1  DATA 0DBH; PCA Channel 1 Capture/Compare Mode       
+PCA0CPM2  DATA 0DCH; PCA Channel 2 Capture/Compare Mode       
+PCA0CPM3  DATA 0AEH; PCA Channel 3 Capture/Compare Mode       
+PCA0CPM4  DATA 0AFH; PCA Channel 4 Capture/Compare Mode       
+PCA0CPM5  DATA 0CCH; PCA Channel 5 Capture/Compare Mode       
+PCA0H     DATA 0FAH; PCA Counter/Timer High Byte              
+PCA0L     DATA 0F9H; PCA Counter/Timer Low Byte               
+PCA0MD    DATA 0D9H; PCA Mode                                 
+PCA0POL   DATA 096H; PCA Output Polarity                      
+PCA0PWM   DATA 0F7H; PCA PWM Configuration                    
+PCON0     DATA 087H; Power Control                            
+PCON1     DATA 0CDH; Power Control 1                          
+PFE0CN    DATA 0C1H; Prefetch Engine Control                  
+PRTDRV    DATA 0F6H; Port Drive Strength                      
+PSCTL     DATA 08FH; Program Store Control                    
+PSTAT0    DATA 0AAH; PMU Status 0                             
+PSW       DATA 0D0H; Program Status Word                      
+REF0CN    DATA 0D1H; Voltage Reference Control                
+REG0CN    DATA 0C9H; Voltage Regulator 0 Control              
+REVID     DATA 0B6H; Revision Identifcation                   
+RSTSRC    DATA 0EFH; Reset Source                             
+SBCON1    DATA 094H; UART1 Baud Rate Generator Control        
+SBRLH1    DATA 096H; UART1 Baud Rate Generator High Byte      
+SBRLL1    DATA 095H; UART1 Baud Rate Generator Low Byte       
+SBUF0     DATA 099H; UART0 Serial Port Data Buffer            
+SBUF1     DATA 092H; UART1 Serial Port Data Buffer            
+SCON0     DATA 098H; UART0 Serial Port Control                
+SCON1     DATA 0C8H; UART1 Serial Port Control                
+SFRPAGE   DATA 0A7H; SFR Page                                 
+SFRPGCN   DATA 0BCH; SFR Page Control                         
+SFRSTACK  DATA 0D7H; SFR Page Stack                           
+SMB0ADM   DATA 0D6H; SMBus 0 Slave Address Mask               
+SMB0ADR   DATA 0D7H; SMBus 0 Slave Address                    
+SMB0CF    DATA 0C1H; SMBus 0 Configuration                    
+SMB0CN0   DATA 0C0H; SMBus 0 Control                          
+SMB0DAT   DATA 0C2H; SMBus 0 Data                             
+SMB0FCN0  DATA 0C3H; SMBus 0 FIFO Control 0                   
+SMB0FCN1  DATA 0C4H; SMBus 0 FIFO Control 1                   
+SMB0FCT   DATA 0EFH; SMBus 0 FIFO Count                       
+SMB0RXLN  DATA 0C5H; SMBus 0 Receive Length Counter           
+SMB0TC    DATA 0ACH; SMBus 0 Timing and Pin Control           
+SMOD1     DATA 093H; UART1 Mode                               
+SP        DATA 081H; Stack Pointer                            
+SPI0CFG   DATA 0A1H; SPI0 Configuration                       
+SPI0CKR   DATA 0A2H; SPI0 Clock Rate                          
+SPI0CN0   DATA 0F8H; SPI0 Control                             
+SPI0DAT   DATA 0A3H; SPI0 Data                                
+SPI0FCN0  DATA 09AH; SPI0 FIFO Control 0                      
+SPI0FCN1  DATA 09BH; SPI0 FIFO Control 1                      
+SPI0FCT   DATA 0F7H; SPI0 FIFO Count                          
+SPI0PCF   DATA 0DFH; SPI0 Pin Configuration                   
+TCON      DATA 088H; Timer 0/1 Control                        
+TH0       DATA 08CH; Timer 0 High Byte                        
+TH1       DATA 08DH; Timer 1 High Byte                        
+TL0       DATA 08AH; Timer 0 Low Byte                         
+TL1       DATA 08BH; Timer 1 Low Byte                         
+TMOD      DATA 089H; Timer 0/1 Mode                           
+TMR2CN0   DATA 0C8H; Timer 2 Control 0                        
+TMR2CN1   DATA 0FDH; Timer 2 Control 1                        
+TMR2H     DATA 0CFH; Timer 2 High Byte                        
+TMR2L     DATA 0CEH; Timer 2 Low Byte                         
+TMR2RLH   DATA 0CBH; Timer 2 Reload High Byte                 
+TMR2RLL   DATA 0CAH; Timer 2 Reload Low Byte                  
+TMR3CN0   DATA 091H; Timer 3 Control 0                        
+TMR3CN1   DATA 0FEH; Timer 3 Control 1                        
+TMR3H     DATA 095H; Timer 3 High Byte                        
+TMR3L     DATA 094H; Timer 3 Low Byte                         
+TMR3RLH   DATA 093H; Timer 3 Reload High Byte                 
+TMR3RLL   DATA 092H; Timer 3 Reload Low Byte                  
+TMR4CN0   DATA 098H; Timer 4 Control 0                        
+TMR4CN1   DATA 0FFH; Timer 4 Control 1                        
+TMR4H     DATA 0A5H; Timer 4 High Byte                        
+TMR4L     DATA 0A4H; Timer 4 Low Byte                         
+TMR4RLH   DATA 0A3H; Timer 4 Reload High Byte                 
+TMR4RLL   DATA 0A2H; Timer 4 Reload Low Byte                  
+TMR5CN0   DATA 0C0H; Timer 5 Control 0                        
+TMR5CN1   DATA 0F1H; Timer 5 Control 1                        
+TMR5H     DATA 0D5H; Timer 5 High Byte                        
+TMR5L     DATA 0D4H; Timer 5 Low Byte                         
+TMR5RLH   DATA 0D3H; Timer 5 Reload High Byte                 
+TMR5RLL   DATA 0D2H; Timer 5 Reload Low Byte                  
+UART0PCF  DATA 0D9H; UART0 Pin Configuration                  
+UART1FCN0 DATA 09DH; UART1 FIFO Control 0                     
+UART1FCN1 DATA 0D8H; UART1 FIFO Control 1                     
+UART1FCT  DATA 0FAH; UART1 FIFO Count                         
+UART1LIN  DATA 09EH; UART1 LIN Configuration                  
+UART1PCF  DATA 0DAH; UART1 Pin Configuration                  
+VDM0CN    DATA 0FFH; Supply Monitor Control                   
+WDTCN     DATA 097H; Watchdog Timer Control                   
+XBR0      DATA 0E1H; Port I/O Crossbar 0                      
+XBR1      DATA 0E2H; Port I/O Crossbar 1                      
+XBR2      DATA 0E3H; Port I/O Crossbar 2                      
+XOSC0CN   DATA 086H; External Oscillator Control              
+
+;------------------------------------------------------------------------------
+; 16-bit Register Definitions (may not work on all compilers)
+;------------------------------------------------------------------------------
+ADC0ASA DATA 0B5H ; ADC0 Autoscan Start Address Low Byte 
+ADC0GT  DATA 0C3H ; ADC0 Greater-Than Low Byte           
+ADC0    DATA 0BDH ; ADC0 Data Word Low Byte              
+ADC0LT  DATA 0C5H ; ADC0 Less-Than Low Byte              
+DP      DATA 082H ; Data Pointer Low                     
+PCA0CP0 DATA 0FBH ; PCA Channel 0 Capture Module Low Byte
+PCA0CP1 DATA 0E9H ; PCA Channel 1 Capture Module Low Byte
+PCA0CP2 DATA 0EBH ; PCA Channel 2 Capture Module Low Byte
+PCA0CP3 DATA 0F4H ; PCA Channel 3 Capture Module Low Byte
+PCA0CP4 DATA 084H ; PCA Channel 4 Capture Module Low Byte
+PCA0CP5 DATA 0DDH ; PCA Channel 5 Capture Module Low Byte
+PCA0    DATA 0F9H ; PCA Counter/Timer Low Byte           
+TMR2    DATA 0CEH ; Timer 2 Low Byte                     
+TMR2RL  DATA 0CAH ; Timer 2 Reload Low Byte              
+TMR3    DATA 094H ; Timer 3 Low Byte                     
+TMR3RL  DATA 092H ; Timer 3 Reload Low Byte              
+TMR4    DATA 0A4H ; Timer 4 Low Byte                     
+TMR4RL  DATA 0A2H ; Timer 4 Reload Low Byte              
+TMR5    DATA 0D4H ; Timer 5 Low Byte                     
+TMR5RL  DATA 0D2H ; Timer 5 Reload Low Byte              
+
+;------------------------------------------------------------------------------
+; Indirect Register Definitions
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+; Bit Definitions
+;------------------------------------------------------------------------------
+
+; ACC 0xE0 (Accumulator)
+ACC_ACC0 BIT ACC.0 ; Accumulator Bit 0
+ACC_ACC1 BIT ACC.1 ; Accumulator Bit 1
+ACC_ACC2 BIT ACC.2 ; Accumulator Bit 2
+ACC_ACC3 BIT ACC.3 ; Accumulator Bit 3
+ACC_ACC4 BIT ACC.4 ; Accumulator Bit 4
+ACC_ACC5 BIT ACC.5 ; Accumulator Bit 5
+ACC_ACC6 BIT ACC.6 ; Accumulator Bit 6
+ACC_ACC7 BIT ACC.7 ; Accumulator Bit 7
+
+; ADC0CN0 0xE8 (ADC0 Control 0)
+ADC0CN0_TEMPE  BIT ADC0CN0.0 ; Temperature Sensor Enable         
+ADC0CN0_ADGN0  BIT ADC0CN0.1 ; Gain Control Bit 0                
+ADC0CN0_ADGN1  BIT ADC0CN0.2 ; Gain Control Bit 1                
+ADC0CN0_ADWINT BIT ADC0CN0.3 ; Window Compare Interrupt Flag     
+ADC0CN0_ADBUSY BIT ADC0CN0.4 ; ADC Busy                          
+ADC0CN0_ADINT  BIT ADC0CN0.5 ; Conversion Complete Interrupt Flag
+ADC0CN0_IPOEN  BIT ADC0CN0.6 ; Idle Powered-off Enable           
+ADC0CN0_ADEN   BIT ADC0CN0.7 ; ADC Enable                        
+
+; B 0xF0 (B Register)
+B_B0 BIT B.0 ; B Register Bit 0
+B_B1 BIT B.1 ; B Register Bit 1
+B_B2 BIT B.2 ; B Register Bit 2
+B_B3 BIT B.3 ; B Register Bit 3
+B_B4 BIT B.4 ; B Register Bit 4
+B_B5 BIT B.5 ; B Register Bit 5
+B_B6 BIT B.6 ; B Register Bit 6
+B_B7 BIT B.7 ; B Register Bit 7
+
+; CLIF0 0xE8 (Configurable Logic Interrupt Flag 0)
+CLIF0_C0FIF BIT CLIF0.0 ; CLU0 Falling Edge Interrupt Flag
+CLIF0_C0RIF BIT CLIF0.1 ; CLU0 Rising Edge Interrupt Flag 
+CLIF0_C1FIF BIT CLIF0.2 ; CLU1 Falling Edge Interrupt Flag
+CLIF0_C1RIF BIT CLIF0.3 ; CLU1 Rising Edge Interrupt Flag 
+CLIF0_C2FIF BIT CLIF0.4 ; CLU2 Falling Edge Interrupt Flag
+CLIF0_C2RIF BIT CLIF0.5 ; CLU2 Rising Edge Interrupt Flag 
+CLIF0_C3FIF BIT CLIF0.6 ; CLU3 Falling Edge Interrupt Flag
+CLIF0_C3RIF BIT CLIF0.7 ; CLU3 Rising Edge Interrupt Flag 
+
+; DACGCF0 0x88 (DAC Global Configuration 0)
+DACGCF0_D1SRC0   BIT DACGCF0.0 ; DAC1 Data Source Bit 0                
+DACGCF0_D1SRC1   BIT DACGCF0.1 ; DAC1 Data Source Bit 1                
+DACGCF0_D1AMEN   BIT DACGCF0.2 ; DAC1 Alternating Mode Enable          
+DACGCF0_D01REFSL BIT DACGCF0.3 ; DAC0 and DAC1 Reference Voltage Select
+DACGCF0_D3SRC0   BIT DACGCF0.4 ; DAC3 Data Source Bit 0                
+DACGCF0_D3SRC1   BIT DACGCF0.5 ; DAC3 Data Source Bit 1                
+DACGCF0_D3AMEN   BIT DACGCF0.6 ; DAC3 Alternating Mode Enable          
+DACGCF0_D23REFSL BIT DACGCF0.7 ; DAC2 and DAC3 Reference Voltage Select
+
+; DACGCF1 0x98 (DAC Global Configuration 1)
+DACGCF1_D0UDIS BIT DACGCF1.0 ; DAC0 Update Disable
+DACGCF1_D1UDIS BIT DACGCF1.1 ; DAC1 Update Disable
+DACGCF1_D2UDIS BIT DACGCF1.2 ; DAC2 Update Disable
+DACGCF1_D3UDIS BIT DACGCF1.3 ; DAC3 Update Disable
+
+; IE 0xA8 (Interrupt Enable)
+IE_EX0   BIT IE.0 ; External Interrupt 0 Enable
+IE_ET0   BIT IE.1 ; Timer 0 Interrupt Enable   
+IE_EX1   BIT IE.2 ; External Interrupt 1 Enable
+IE_ET1   BIT IE.3 ; Timer 1 Interrupt Enable   
+IE_ES0   BIT IE.4 ; UART0 Interrupt Enable     
+IE_ET2   BIT IE.5 ; Timer 2 Interrupt Enable   
+IE_ESPI0 BIT IE.6 ; SPI0 Interrupt Enable      
+IE_EA    BIT IE.7 ; All Interrupts Enable      
+
+; IP 0xB8 (Interrupt Priority)
+IP_PX0   BIT IP.0 ; External Interrupt 0 Priority Control LSB                        
+IP_PT0   BIT IP.1 ; Timer 0 Interrupt Priority Control LSB                           
+IP_PX1   BIT IP.2 ; External Interrupt 1 Priority Control LSB                        
+IP_PT1   BIT IP.3 ; Timer 1 Interrupt Priority Control LSB                           
+IP_PS0   BIT IP.4 ; UART0 Interrupt Priority Control LSB                             
+IP_PT2   BIT IP.5 ; Timer 2 Interrupt Priority Control LSB                           
+IP_PSPI0 BIT IP.6 ; Serial Peripheral Interface (SPI0) Interrupt Priority Control LSB
+
+; P0 0x80 (Port 0 Pin Latch)
+P0_B0 BIT P0.0 ; Port 0 Bit 0 Latch
+P0_B1 BIT P0.1 ; Port 0 Bit 1 Latch
+P0_B2 BIT P0.2 ; Port 0 Bit 2 Latch
+P0_B3 BIT P0.3 ; Port 0 Bit 3 Latch
+P0_B4 BIT P0.4 ; Port 0 Bit 4 Latch
+P0_B5 BIT P0.5 ; Port 0 Bit 5 Latch
+P0_B6 BIT P0.6 ; Port 0 Bit 6 Latch
+P0_B7 BIT P0.7 ; Port 0 Bit 7 Latch
+
+; P1 0x90 (Port 1 Pin Latch)
+P1_B0 BIT P1.0 ; Port 1 Bit 0 Latch
+P1_B1 BIT P1.1 ; Port 1 Bit 1 Latch
+P1_B2 BIT P1.2 ; Port 1 Bit 2 Latch
+P1_B3 BIT P1.3 ; Port 1 Bit 3 Latch
+P1_B4 BIT P1.4 ; Port 1 Bit 4 Latch
+P1_B5 BIT P1.5 ; Port 1 Bit 5 Latch
+P1_B6 BIT P1.6 ; Port 1 Bit 6 Latch
+P1_B7 BIT P1.7 ; Port 1 Bit 7 Latch
+
+; P2 0xA0 (Port 2 Pin Latch)
+P2_B0 BIT P2.0 ; Port 2 Bit 0 Latch
+P2_B1 BIT P2.1 ; Port 2 Bit 1 Latch
+P2_B2 BIT P2.2 ; Port 2 Bit 2 Latch
+P2_B3 BIT P2.3 ; Port 2 Bit 3 Latch
+P2_B4 BIT P2.4 ; Port 2 Bit 4 Latch
+P2_B5 BIT P2.5 ; Port 2 Bit 5 Latch
+P2_B6 BIT P2.6 ; Port 2 Bit 6 Latch
+
+; P3 0xB0 (Port 3 Pin Latch)
+P3_B0 BIT P3.0 ; Port 3 Bit 0 Latch
+P3_B1 BIT P3.1 ; Port 3 Bit 1 Latch
+P3_B2 BIT P3.2 ; Port 3 Bit 2 Latch
+P3_B3 BIT P3.3 ; Port 3 Bit 3 Latch
+P3_B4 BIT P3.4 ; Port 3 Bit 4 Latch
+P3_B7 BIT P3.7 ; Port 3 Bit 7 Latch
+
+; PCA0CN0 0xD8 (PCA Control)
+PCA0CN0_CCF0 BIT PCA0CN0.0 ; PCA Module 0 Capture/Compare Flag
+PCA0CN0_CCF1 BIT PCA0CN0.1 ; PCA Module 1 Capture/Compare Flag
+PCA0CN0_CCF2 BIT PCA0CN0.2 ; PCA Module 2 Capture/Compare Flag
+PCA0CN0_CCF3 BIT PCA0CN0.3 ; PCA Module 3 Capture/Compare Flag
+PCA0CN0_CCF4 BIT PCA0CN0.4 ; PCA Module 4 Capture/Compare Flag
+PCA0CN0_CCF5 BIT PCA0CN0.5 ; PCA Module 5 Capture/Compare Flag
+PCA0CN0_CR   BIT PCA0CN0.6 ; PCA Counter/Timer Run Control    
+PCA0CN0_CF   BIT PCA0CN0.7 ; PCA Counter/Timer Overflow Flag  
+
+; PSW 0xD0 (Program Status Word)
+PSW_PARITY BIT PSW.0 ; Parity Flag               
+PSW_F1     BIT PSW.1 ; User Flag 1               
+PSW_OV     BIT PSW.2 ; Overflow Flag             
+PSW_RS0    BIT PSW.3 ; Register Bank Select Bit 0
+PSW_RS1    BIT PSW.4 ; Register Bank Select Bit 1
+PSW_F0     BIT PSW.5 ; User Flag 0               
+PSW_AC     BIT PSW.6 ; Auxiliary Carry Flag      
+PSW_CY     BIT PSW.7 ; Carry Flag                
+
+; SCON0 0x98 (UART0 Serial Port Control)
+SCON0_RI    BIT SCON0.0 ; Receive Interrupt Flag             
+SCON0_TI    BIT SCON0.1 ; Transmit Interrupt Flag            
+SCON0_RB8   BIT SCON0.2 ; Ninth Receive Bit                  
+SCON0_TB8   BIT SCON0.3 ; Ninth Transmission Bit             
+SCON0_REN   BIT SCON0.4 ; Receive Enable                     
+SCON0_MCE   BIT SCON0.5 ; Multiprocessor Communication Enable
+SCON0_SMODE BIT SCON0.7 ; Serial Port 0 Operation Mode       
+
+; SCON1 0xC8 (UART1 Serial Port Control)
+SCON1_RI   BIT SCON1.0 ; Receive Interrupt Flag   
+SCON1_TI   BIT SCON1.1 ; Transmit Interrupt Flag  
+SCON1_RBX  BIT SCON1.2 ; Extra Receive Bit        
+SCON1_TBX  BIT SCON1.3 ; Extra Transmission Bit   
+SCON1_REN  BIT SCON1.4 ; Receive Enable           
+SCON1_PERR BIT SCON1.6 ; Parity Error Flag        
+SCON1_OVR  BIT SCON1.7 ; Receive FIFO Overrun Flag
+
+; SMB0CN0 0xC0 (SMBus 0 Control)
+SMB0CN0_SI      BIT SMB0CN0.0 ; SMBus Interrupt Flag            
+SMB0CN0_ACK     BIT SMB0CN0.1 ; SMBus Acknowledge               
+SMB0CN0_ARBLOST BIT SMB0CN0.2 ; SMBus Arbitration Lost Indicator
+SMB0CN0_ACKRQ   BIT SMB0CN0.3 ; SMBus Acknowledge Request       
+SMB0CN0_STO     BIT SMB0CN0.4 ; SMBus Stop Flag                 
+SMB0CN0_STA     BIT SMB0CN0.5 ; SMBus Start Flag                
+SMB0CN0_TXMODE  BIT SMB0CN0.6 ; SMBus Transmit Mode Indicator   
+SMB0CN0_MASTER  BIT SMB0CN0.7 ; SMBus Master/Slave Indicator    
+
+; SPI0CN0 0xF8 (SPI0 Control)
+SPI0CN0_SPIEN  BIT SPI0CN0.0 ; SPI0 Enable            
+SPI0CN0_TXNF   BIT SPI0CN0.1 ; TX FIFO Not Full       
+SPI0CN0_NSSMD0 BIT SPI0CN0.2 ; Slave Select Mode Bit 0
+SPI0CN0_NSSMD1 BIT SPI0CN0.3 ; Slave Select Mode Bit 1
+SPI0CN0_RXOVRN BIT SPI0CN0.4 ; Receive Overrun Flag   
+SPI0CN0_MODF   BIT SPI0CN0.5 ; Mode Fault Flag        
+SPI0CN0_WCOL   BIT SPI0CN0.6 ; Write Collision Flag   
+SPI0CN0_SPIF   BIT SPI0CN0.7 ; SPI0 Interrupt Flag    
+
+; TCON 0x88 (Timer 0/1 Control)
+TCON_IT0 BIT TCON.0 ; Interrupt 0 Type Select
+TCON_IE0 BIT TCON.1 ; External Interrupt 0   
+TCON_IT1 BIT TCON.2 ; Interrupt 1 Type Select
+TCON_IE1 BIT TCON.3 ; External Interrupt 1   
+TCON_TR0 BIT TCON.4 ; Timer 0 Run Control    
+TCON_TF0 BIT TCON.5 ; Timer 0 Overflow Flag  
+TCON_TR1 BIT TCON.6 ; Timer 1 Run Control    
+TCON_TF1 BIT TCON.7 ; Timer 1 Overflow Flag  
+
+; TMR2CN0 0xC8 (Timer 2 Control 0)
+TMR2CN0_T2XCLK0 BIT TMR2CN0.0 ; Timer 2 External Clock Select Bit 0
+TMR2CN0_T2XCLK1 BIT TMR2CN0.1 ; Timer 2 External Clock Select Bit 1
+TMR2CN0_TR2     BIT TMR2CN0.2 ; Timer 2 Run Control                
+TMR2CN0_T2SPLIT BIT TMR2CN0.3 ; Timer 2 Split Mode Enable          
+TMR2CN0_TF2CEN  BIT TMR2CN0.4 ; Timer 2 Capture Enable             
+TMR2CN0_TF2LEN  BIT TMR2CN0.5 ; Timer 2 Low Byte Interrupt Enable  
+TMR2CN0_TF2L    BIT TMR2CN0.6 ; Timer 2 Low Byte Overflow Flag     
+TMR2CN0_TF2H    BIT TMR2CN0.7 ; Timer 2 High Byte Overflow Flag    
+
+; TMR4CN0 0x98 (Timer 4 Control 0)
+TMR4CN0_T4XCLK0 BIT TMR4CN0.0 ; Timer 4 External Clock Select Bit 0
+TMR4CN0_T4XCLK1 BIT TMR4CN0.1 ; Timer 4 External Clock Select Bit 1
+TMR4CN0_TR4     BIT TMR4CN0.2 ; Timer 4 Run Control                
+TMR4CN0_T4SPLIT BIT TMR4CN0.3 ; Timer 4 Split Mode Enable          
+TMR4CN0_TF4CEN  BIT TMR4CN0.4 ; Timer 4 Capture Enable             
+TMR4CN0_TF4LEN  BIT TMR4CN0.5 ; Timer 4 Low Byte Interrupt Enable  
+TMR4CN0_TF4L    BIT TMR4CN0.6 ; Timer 4 Low Byte Overflow Flag     
+TMR4CN0_TF4H    BIT TMR4CN0.7 ; Timer 4 High Byte Overflow Flag    
+
+; TMR5CN0 0xC0 (Timer 5 Control 0)
+TMR5CN0_T5XCLK0 BIT TMR5CN0.0 ; Timer 5 External Clock Select Bit 0
+TMR5CN0_T5XCLK1 BIT TMR5CN0.1 ; Timer 5 External Clock Select Bit 1
+TMR5CN0_TR5     BIT TMR5CN0.2 ; Timer 5 Run Control                
+TMR5CN0_T5SPLIT BIT TMR5CN0.3 ; Timer 5 Split Mode Enable          
+TMR5CN0_TF5CEN  BIT TMR5CN0.4 ; Timer 5 Capture Enable             
+TMR5CN0_TF5LEN  BIT TMR5CN0.5 ; Timer 5 Low Byte Interrupt Enable  
+TMR5CN0_TF5L    BIT TMR5CN0.6 ; Timer 5 Low Byte Overflow Flag     
+TMR5CN0_TF5H    BIT TMR5CN0.7 ; Timer 5 High Byte Overflow Flag    
+
+; UART1FCN1 0xD8 (UART1 FIFO Control 1)
+UART1FCN1_RIE    BIT UART1FCN1.0 ; Receive Interrupt Enable 
+UART1FCN1_RXTO0  BIT UART1FCN1.1 ; Receive Timeout Bit 0    
+UART1FCN1_RXTO1  BIT UART1FCN1.2 ; Receive Timeout Bit 1    
+UART1FCN1_RFRQ   BIT UART1FCN1.3 ; Receive FIFO Request     
+UART1FCN1_TIE    BIT UART1FCN1.4 ; Transmit Interrupt Enable
+UART1FCN1_TXHOLD BIT UART1FCN1.5 ; Transmit Hold            
+UART1FCN1_TXNF   BIT UART1FCN1.6 ; TX FIFO Not Full         
+UART1FCN1_TFRQ   BIT UART1FCN1.7 ; Transmit FIFO Request    
+
+;------------------------------------------------------------------------------
+; Interrupt Definitions
+;------------------------------------------------------------------------------
+INT0_IRQn    EQU 0  ; External Interrupt 0      
+TIMER0_IRQn  EQU 1  ; Timer 0 Overflow          
+INT1_IRQn    EQU 2  ; External Interrupt 1      
+TIMER1_IRQn  EQU 3  ; Timer 1 Overflow          
+UART0_IRQn   EQU 4  ; UART0                     
+TIMER2_IRQn  EQU 5  ; Timer 2 Overflow / Capture
+SPI0_IRQn    EQU 6  ; SPI0                      
+SMBUS0_IRQn  EQU 7  ; SMBus 0                   
+PMATCH_IRQn  EQU 8  ; Port Match                
+ADC0WC_IRQn  EQU 9  ; ADC0 Window Compare       
+ADC0EOC_IRQn EQU 10 ; ADC0 End of Conversion    
+PCA0_IRQn    EQU 11 ; PCA0                      
+CMP0_IRQn    EQU 12 ; Comparator 0              
+CMP1_IRQn    EQU 13 ; Comparator 1              
+TIMER3_IRQn  EQU 14 ; Timer 3 Overflow / Capture
+UART1_IRQn   EQU 15 ; UART1                     
+I2C0_IRQn    EQU 16 ; I2C0 Slave                
+TIMER4_IRQn  EQU 17 ; Timer 4 Overflow / Capture
+TIMER5_IRQn  EQU 18 ; Timer 5 Overflow / Capture
+CL0_IRQn     EQU 19 ; Configurable Logic        
+
+;------------------------------------------------------------------------------
+; SFR Page Definitions
+;------------------------------------------------------------------------------
+LEGACY_PAGE  EQU 000H ; Legacy SFR Page
+PG2_PAGE     EQU 010H ; Page2          
+PG3_PAGE     EQU 020H ; Page3          
+PG4_PAGE     EQU 030H ; Page4          

T.inc

@@ -0,0 +1,558 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "T".
+; RC X  MA X  MB CC MC X     X  X  Cp Bp Ap Ac Bc Cc
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#T_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#T_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#T_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#T_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#T_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#T_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#T_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#T_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#T_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#T_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#T_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#T_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#T_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#T_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#T_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#T_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#T_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#T_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#T_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#T_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#T_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#T_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	7		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Rcp_In		EQU	7	;i
+;			EQU	6	;i
+Mux_A		EQU	5	;i
+;			EQU	4	;i 
+Mux_B		EQU	3	;i
+Comp_Com		EQU	2	;i
+Mux_C		EQU	1	;i
+;			EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+;			EQU	6	;i
+CpwmFET		EQU	5	;o
+BpwmFET		EQU	4	;o
+ApwmFET		EQU	3	;o
+AcomFET		EQU	2	;o 
+BcomFET		EQU	1	;o
+CcomFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	3Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #37h
+ELSE
+	mov	P1SKIP, #33h
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #2Fh
+ELSE
+	mov	P1SKIP, #2Dh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #1Fh
+ELSE
+	mov	P1SKIP, #1Eh
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #3Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #52h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #32h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #12h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

U.inc

@@ -0,0 +1,562 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "U".
+; MA MC CC MB RC L0 L1 L2     X  Cc Bc Ac Cp Bp Ap X     
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#U_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#U_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#U_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#U_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#U_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#U_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#U_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#U_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#U_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#U_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#U_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#U_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#U_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#U_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#U_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#U_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#U_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#U_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#U_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#U_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#U_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#U_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	3		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Mux_A		EQU	7	;i
+Mux_C		EQU	6	;i
+Comp_Com  	EQU	5	;i
+Mux_B		EQU	4	;i
+Rcp_In		EQU	3	;i
+LED_0		EQU	2	;i
+LED_1		EQU	1	;i
+LED_2		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	(1 SHL LED_0)+(1 SHL LED_1)+(1 SHL LED_2)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+	mov	PCA0POL, #02h				; Damping inverted, pwm noninverted
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+CcomFET		EQU	6	;o
+BcomFET		EQU	5	;o
+AcomFET		EQU	4	;o
+CpwmFET		EQU	3	;i
+BpwmFET		EQU	2	;o 
+ApwmFET		EQU	1	;o
+;			EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
+P1_SKIP		EQU	7Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb	P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P1.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P1.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P1.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P1SKIP, #7Dh
+ELSE
+	mov	P1SKIP, #6Dh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P1SKIP, #7Bh
+ELSE
+	mov	P1SKIP, #5Bh
+ENDIF
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P1.CcomFET
+	mov	P1SKIP, #77h
+ELSE
+	mov	P1SKIP, #37h
+ENDIF
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #75h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #45h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #65h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+	clr	P0.LED_0
+ENDM
+Clear_LED_0 MACRO
+	setb	P0.LED_0
+ENDM
+Set_LED_1 MACRO
+	clr	P0.LED_1
+ENDM
+Clear_LED_1 MACRO
+	setb	P0.LED_1
+ENDM
+Set_LED_2 MACRO
+	clr	P0.LED_2
+ENDM
+Clear_LED_2 MACRO
+	setb	P0.LED_2
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM
+

V.inc

@@ -0,0 +1,564 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "V"
+; Cc X  RC X  MC CC MB MA    X  Ap Ac Bp X  X  Bc Cp
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#V_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#V_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#V_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#V_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#V_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#V_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#V_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#V_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#V_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#V_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#V_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#V_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#V_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#V_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#V_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#V_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#V_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#V_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#V_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#V_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#V_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#V_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	5		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+CcomFET		EQU	7	;o
+;			EQU	6	;i
+Rcp_In		EQU	5	;i
+;			EQU	4	;i 
+Mux_C		EQU	3	;i
+Comp_Com	EQU	2	;i
+Mux_B		EQU	1	;i
+Mux_A		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	NOT(1 SHL CcomFET)
+P0_PUSHPULL	EQU	(1 SHL CcomFET)
+P0_SKIP		EQU	0FFh
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+	ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;			EQU	7	;i
+ApwmFET		EQU	6	;i
+AcomFET		EQU	5	;i
+BpwmFET		EQU	4	;o
+;    		EQU	3	;o
+;    		EQU	2	;o
+BcomFET		EQU	1	;o
+CpwmFET		EQU	0	;o
+
+P1_DIGITAL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)
+P1_INIT		EQU 	00h		
+P1_PUSHPULL	EQU	(1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)
+P1_SKIP		EQU	7Fh
+
+ApwmFET_on MACRO
+	setb	P1.ApwmFET
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+ENDIF
+ENDM
+ApwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+ELSE
+	clr	P1.AcomFET
+ENDIF
+ENDM
+BpwmFET_on MACRO
+	setb	P1.BpwmFET
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+ENDIF
+ENDM
+BpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.BpwmFET
+ELSE
+	clr	P1.BcomFET
+ENDIF
+ENDM
+CpwmFET_on MACRO
+	setb	P1.CpwmFET
+IF FETON_DELAY == 0
+	setb	P0.CcomFET
+ENDIF
+ENDM
+CpwmFET_off MACRO
+IF FETON_DELAY != 0
+	clr	P1.CpwmFET
+ELSE
+	clr	P0.CcomFET
+ENDIF
+ENDM
+All_pwmFETs_Off MACRO
+IF FETON_DELAY != 0
+	clr	P1.ApwmFET
+	clr	P1.BpwmFET
+	clr	P1.CpwmFET
+ELSE
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P0.CcomFET
+ENDIF
+ENDM
+
+AcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.ApwmFET
+ENDIF
+	setb P1.AcomFET
+ENDM
+AcomFET_off MACRO
+	clr	P1.AcomFET
+ENDM
+BcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.BpwmFET
+ENDIF
+	setb	P1.BcomFET
+ENDM
+BcomFET_off MACRO
+	clr	P1.BcomFET
+ENDM
+CcomFET_on MACRO
+IF FETON_DELAY == 0
+	clr	P1.CpwmFET
+ENDIF
+	setb	P0.CcomFET
+ENDM
+CcomFET_off MACRO
+	clr	P0.CcomFET
+ENDM
+All_comFETs_Off MACRO
+	clr	P1.AcomFET
+	clr	P1.BcomFET
+	clr	P0.CcomFET
+ENDM
+
+Set_Pwm_A MACRO
+IF FETON_DELAY == 0
+	setb	P1.AcomFET
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #3Fh
+ELSE
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #1Fh
+ENDIF
+ENDM
+Set_Pwm_B MACRO
+IF FETON_DELAY == 0
+	setb	P1.BcomFET
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #6Fh
+ELSE
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #6Dh
+endif
+ENDM
+Set_Pwm_C MACRO
+IF FETON_DELAY == 0
+	setb	P0.CcomFET
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #7Fh
+ELSE
+	mov	P0SKIP, #7Fh
+	mov	P1SKIP, #7Eh
+endif
+ENDM
+Set_Pwms_Off MACRO
+	mov	P0SKIP, #0FFh
+	mov	P1SKIP, #7Fh
+ENDM
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #02h	; Set comparator multiplexer to phase A
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #12h	; Set comparator multiplexer to phase B
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #32h	; Set comparator multiplexer to phase C
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM

W.inc

@@ -0,0 +1,518 @@
+;**** **** **** **** ****
+;
+; BLHeli program for controlling brushless motors in helicopters and multirotors
+;
+; Copyright 2011, 2012 Steffen Skaug
+; This program is distributed under the terms of the GNU General Public License
+;
+; This file is part of BLHeli.
+;
+; BLHeli is free software: you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation, either version 3 of the License, or
+; (at your option) any later version.
+;
+; BLHeli is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with BLHeli.  If not, see <http://www.gnu.org/licenses/>.
+;
+;**** **** **** **** ****
+;
+; Hardware definition file "W". This is for tristate input style FET driver chips
+; RC MC MB X CC MA X X     X  Ap Bp Cp X X X X
+;
+;**** **** **** **** ****
+
+
+
+;*********************
+; Device SiLabs EFM8BB1x/2x
+;*********************
+IF MCU_48MHZ == 0
+$include (SI_EFM8BB1_Defs.inc)
+ELSE
+$include (SI_EFM8BB2_Defs.inc)
+ENDIF
+
+
+;**** **** **** **** ****
+; Uses internal calibrated oscillator set to 24/48Mhz
+;**** **** **** **** ****
+
+;**** **** **** **** ****
+; Constant definitions
+;**** **** **** **** ****
+IF MCU_48MHZ == 0
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#W_L_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#W_L_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#W_L_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#W_L_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#W_L_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#W_L_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#W_L_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#W_L_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#W_L_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#W_L_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#W_L_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B10#"	; Project and MCU tag (16 Bytes)
+
+ELSE
+
+CSEG AT 1A40h
+IF FETON_DELAY == 0
+Eep_ESC_Layout:		DB	"#W_H_00#        "	; ESC layout tag
+ELSEIF FETON_DELAY == 5
+Eep_ESC_Layout:		DB	"#W_H_05#        "
+ELSEIF FETON_DELAY == 10
+Eep_ESC_Layout:		DB	"#W_H_10#        "
+ELSEIF FETON_DELAY == 15
+Eep_ESC_Layout:		DB	"#W_H_15#        "
+ELSEIF FETON_DELAY == 20
+Eep_ESC_Layout:		DB	"#W_H_20#        "
+ELSEIF FETON_DELAY == 25
+Eep_ESC_Layout:		DB	"#W_H_25#        "
+ELSEIF FETON_DELAY == 30
+Eep_ESC_Layout:		DB	"#W_H_30#        "
+ELSEIF FETON_DELAY == 40
+Eep_ESC_Layout:		DB	"#W_H_40#        "
+ELSEIF FETON_DELAY == 50
+Eep_ESC_Layout:		DB	"#W_H_50#        "
+ELSEIF FETON_DELAY == 70
+Eep_ESC_Layout:		DB	"#W_H_70#        "
+ELSEIF FETON_DELAY == 90
+Eep_ESC_Layout:		DB	"#W_H_90#        "
+ENDIF
+CSEG AT 1A50h
+Eep_ESC_MCU:			DB	"#BLHELI$EFM8B21#"	; Project and MCU tag (16 Bytes)
+ENDIF
+
+TEMP_LIMIT			EQU 	49	; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
+TEMP_LIMIT_STEP		EQU	9	; Temperature measurement ADC value increment for another 10degC
+
+;**** **** **** **** ****
+; Bootloader definitions
+;**** **** **** **** ****
+RTX_PORT		  		EQU 	P0		; Receive/Transmit port
+RTX_MDOUT				EQU	P0MDOUT	; Set to 1 for PUSHPULL				
+RTX_MDIN				EQU	P0MDIN	; Set to 1 for DIGITAL				
+RTX_SKIP				EQU	P0SKIP	; Set to 1 for SKIP				
+RTX_PIN				EQU 	7		; RTX pin
+
+SIGNATURE_001			EQU	0E8h		; Device signature
+IF MCU_48MHZ == 0
+SIGNATURE_002			EQU	0B1h
+ELSE
+SIGNATURE_002			EQU	0B2h
+ENDIF
+
+
+;*********************
+; PORT 0 definitions *
+;*********************  
+Rcp_In		EQU	7	;i
+Mux_C		EQU	6	;i
+Mux_B		EQU	5	;i
+;		EQU	4	;i
+Comp_Com	EQU	3	;i
+Mux_A		EQU	2	;i
+;		EQU	1	;i
+;		EQU	0	;i
+
+P0_DIGITAL	EQU	NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
+P0_INIT		EQU	0FFh
+P0_PUSHPULL	EQU	0
+P0_SKIP		EQU	0FFh
+
+
+Get_Rcp_Capture_Values MACRO
+	anl	TCON, #0EFh				; Disable timer0
+	mov	Temp1, TL0				; Get timer0 values
+	mov	Temp2, TH0
+IF MCU_48MHZ == 1
+	mov	Temp3, Timer0_X
+	jnb	TCON_TF0, ($+4)			; Check if interrupt is pending
+	inc	Temp3					; If it is pending, then timer has already wrapped
+ENDIF
+	mov	TL0, #0					; Reset timer0
+	mov	TH0, #0
+IF MCU_48MHZ == 1
+	mov	Timer0_X, #0
+ENDIF
+	orl	TCON, #10h				; Enable timer0 again
+IF MCU_48MHZ == 1
+	mov	A, Clock_Set_At_48MHz
+	jnz	Get_Rcp_End
+	clr	C
+	mov	A, Temp1
+	rlc	A
+	mov	Temp1, A
+	mov	A, Temp2
+	rlc	A
+	mov	Temp2, A
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+Get_Rcp_End:
+ENDIF
+ENDM
+Decode_Dshot_2Msb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp4					; Shift bit into data byte
+	rlc	A
+	mov	Temp4, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_msb_fail
+
+	subb	A, Temp1
+	mov	A, Temp4
+	rlc	A
+	mov	Temp4, A
+	inc	DPL
+ENDM
+Decode_Dshot_2Lsb MACRO
+	movx	A, @DPTR
+	mov	Temp6, A
+	clr	C
+	subb	A, Temp5					; Subtract previous timestamp
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail			; Check that bit is longer than minimum
+
+	subb	A, Temp1					; Check if bit is zero or one
+	mov	A, Temp3					; Shift bit into data byte
+	rlc	A
+	mov	Temp3, A
+	inc	DPL						; Next bit
+	movx	A, @DPTR
+	mov	Temp5, A
+	clr	C
+	subb	A, Temp6
+	clr	C
+	subb	A, Temp1
+	jc	t1_int_lsb_fail
+
+	subb	A, Temp1
+	mov	A, Temp3
+	rlc	A
+	mov	Temp3, A
+	inc	DPL
+ENDM
+Initialize_PCA MACRO
+	mov	PCA0CN0, #40h				; PCA enabled
+	mov	PCA0MD, #08h				; PCA clock is system clock
+IF FETON_DELAY == 0
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ELSE
+	mov	PCA0PWM, #83h				; PCA ARSEL set and 11bits pwm
+ENDIF
+	mov	PCA0CENT, #00h				; Edge aligned pwm
+ELSE
+IF MCU_48MHZ == 0
+	mov	PCA0PWM, #81h				; PCA ARSEL set and 9bits pwm
+ELSE
+	mov	PCA0PWM, #82h				; PCA ARSEL set and 10bits pwm
+ENDIF
+	mov	PCA0CENT, #03h				; Center aligned pwm
+ENDIF
+ENDM
+Set_Pwm_Polarity MACRO
+IF FETON_DELAY == 0
+	mov	PCA0POL, #00h				; Pwm noninverted
+ELSE
+	mov	PCA0POL, #01h				; Damping inverted, pwm noninverted
+ENDIF
+ENDM
+Enable_Power_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM0, #4Ah				; Enable comparator of module, enable match, set pwm mode
+ELSE
+	mov	PCA0CPM1, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Enable_Damp_Pwm_Module MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPM1, #00h				; Disable
+ELSE
+	mov	PCA0CPM0, #42h				; Enable comparator of module, set pwm mode
+ENDIF
+ENDM
+Set_Power_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL0, Power_Pwm_Reg_L
+	mov	PCA0CPH0, Power_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Power_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Power_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL1, A
+	mov	PCA0CPH1, Temp1
+ENDIF
+ENDM		
+Set_Damp_Pwm_Regs MACRO
+IF FETON_DELAY == 0
+	mov	PCA0CPL1, Damp_Pwm_Reg_L
+	mov	PCA0CPH1, Damp_Pwm_Reg_H
+ELSE
+	clr	C
+	mov	A, Damp_Pwm_Reg_H
+	rrc	A
+	mov	Temp1, A
+	mov	A, Damp_Pwm_Reg_L
+	rrc	A
+	mov	PCA0CPL0, A
+	mov	PCA0CPH0, Temp1
+ENDIF
+ENDM		
+Clear_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0DFh
+ENDM
+Clear_CCF_Interrupt MACRO	; CCF interrupt is only used for FETON_DELAY == 0
+	anl	PCA0CN0, #0FEh
+ENDM
+Enable_COVF_Interrupt MACRO
+	orl	PCA0PWM, #40h
+ENDM
+Enable_CCF_Interrupt MACRO
+	orl	PCA0CPM0,#01h
+ENDM
+Disable_COVF_Interrupt MACRO
+	anl	PCA0PWM, #0BFh
+ENDM
+Disable_CCF_Interrupt MACRO
+	anl	PCA0CPM0,#0FEh
+ENDM
+
+
+;*********************
+; PORT 1 definitions *
+;*********************
+;		EQU	7	;i
+ApwmFET		EQU	6	;o
+BpwmFET		EQU	5	;o
+CpwmFET		EQU	4	;o
+;		EQU	3	;i
+;		EQU	2	;i
+;		EQU	1	;i
+;		EQU	0	;i
+; pwm outputs start as analog in -> floating
+; this ensures all mosfet drivers start with floating outputs
+P1_DIGITAL	EQU	NOT((1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET))
+P1_INIT		EQU 	00h
+P1_PUSHPULL	EQU	((1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET))
+;
+P1_SKIP		EQU     0FFh
+
+
+ApwmFET_on MACRO
+	setb     P1.ApwmFET		; set pin to high
+	orl P1MDIN, #(1 SHL ApwmFET)	; enable pin driver
+ENDM
+ApwmFET_off MACRO
+	anl P1MDIN, #(NOT(1 SHL ApwmFET))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+BpwmFET_on MACRO
+	setb P1.BpwmFET		; set pin to high
+	orl P1MDIN, #(1 SHL BpwmFET)	; enable pin driver
+ENDM
+BpwmFET_off MACRO
+	anl P1MDIN, #(NOT(1 SHL BpwmFET))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+CpwmFET_on MACRO
+	setb     P1.CpwmFET		; set pin to high
+	orl P1MDIN, #(1 SHL CpwmFET)	; enable pin driver
+ENDM
+CpwmFET_off MACRO
+	anl P1MDIN, #(NOT(1 SHL CpwmFET))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+All_pwmFETs_Off MACRO
+	anl P1MDIN, #(NOT((1 SHL ApwmFET) + (1 SHL BpwmFET) + (1 SHL CpwmFET)))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+
+AcomFET_on MACRO
+	clr P1.ApwmFET			; set pin to low
+	orl P1MDIN, #(1 SHL ApwmFET)	; enable pin driver
+ENDM
+AcomFET_off MACRO
+	anl P1MDIN, #(NOT(1 SHL ApwmFET))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+BcomFET_on MACRO
+	clr P1.BpwmFET			; set pin to low
+	orl P1MDIN, #(1 SHL BpwmFET)	; enable pin driver
+ENDM
+BcomFET_off MACRO
+	anl P1MDIN, #(NOT(1 SHL BpwmFET))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+CcomFET_on MACRO
+	clr P1.CpwmFET			; set pin to low
+	orl P1MDIN, #(1 SHL CpwmFET)	; enable pin driver
+ENDM
+CcomFET_off MACRO
+	anl P1MDIN, #(NOT(1 SHL CpwmFET))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+All_comFETs_Off MACRO
+	anl P1MDIN, #(NOT((1 SHL ApwmFET) + (1 SHL BpwmFET) + (1 SHL CpwmFET)))	; analog in -> pullup, driver and digital in is disable = floating
+ENDM
+Set_Pwm_A MACRO
+	mov	P1SKIP, #(NOT(1 SHL ApwmFET));
+	orl	P1MDIN, #(1 SHL ApwmFET)	; enable pin driver
+ENDM
+Set_Pwm_B MACRO
+	mov	P1SKIP, #(NOT(1 SHL BpwmFET));
+	orl	P1MDIN, #(1 SHL BpwmFET)	; enable pin driver
+ENDM
+Set_Pwm_C MACRO
+	mov	P1SKIP, #(NOT(1 SHL CpwmFET));
+	orl	P1MDIN, #(1 SHL CpwmFET)	; enable pin driver
+ENDM
+Set_Pwms_Off MACRO
+	mov	P1SKIP, #P1_SKIP;
+ENDM
+
+
+
+Set_Comp_Phase_A MACRO
+	mov	CMP0MX, #((Mux_A) SHL 4)+((Comp_Com) SHL 0);
+ENDM
+Set_Comp_Phase_B MACRO
+	mov	CMP0MX, #((Mux_B) SHL 4)+((Comp_Com) SHL 0);
+ENDM
+Set_Comp_Phase_C MACRO
+	mov	CMP0MX, #((Mux_C) SHL 4)+((Comp_Com) SHL 0);
+ENDM
+Read_Comp_Out MACRO
+	mov	A, CMP0CN0	; Read comparator output
+ENDM
+
+
+
+;*********************
+; PORT 2 definitions *
+;*********************
+DebugPin		EQU	0	;o
+
+P2_PUSHPULL	EQU	(1 SHL DebugPin)
+
+
+;**********************
+; MCU specific macros *
+;**********************
+Interrupt_Table_Definition MACRO
+CSEG AT 0				; Code segment start
+	jmp reset
+CSEG AT 03h			; Int0 interrupt	
+	jmp	int0_int	
+IF MCU_48MHZ == 1
+CSEG AT 0Bh			; Timer0 overflow interrupt
+	jmp	t0_int
+ENDIF
+CSEG AT 13h			; Int1 interrupt
+	jmp	int1_int
+CSEG AT 1Bh			; Timer1 overflow interrupt
+	jmp	t1_int
+CSEG AT 2Bh			; Timer2 overflow interrupt
+	jmp	t2_int	
+CSEG AT 5Bh			; Pca interrupt
+	jmp	pca_int
+CSEG AT 73h			; Timer3 overflow/compare interrupt
+	jmp	t3_int	
+ENDM
+
+Initialize_Xbar MACRO
+	mov	XBR2, #40h	; Xbar enabled			
+	mov	XBR1, #02h	; CEX0 and CEX1 routed to pins		
+ENDM
+
+Initialize_Comparator MACRO
+	mov	CMP0CN0, #80h	; Comparator enabled, no hysteresis
+	mov	CMP0MD, #00h	; Comparator response time 100ns
+ENDM
+Initialize_Adc MACRO
+	mov	REF0CN, #0Ch	; Set vdd (3.3V) as reference. Enable temp sensor and bias
+IF MCU_48MHZ == 0
+	mov	ADC0CF, #59h	; ADC clock 2MHz, PGA gain 1
+ELSE
+	mov	ADC0CF, #0B9h	; ADC clock 2MHz, PGA gain 1
+ENDIF
+	mov	ADC0MX, #10h	; Select temp sensor input
+	mov	ADC0CN0, #80h	; ADC enabled 
+	mov	ADC0CN1, #01h	; Common mode buffer enabled
+ENDM
+Start_Adc MACRO
+	mov	ADC0CN0, #90h	; ADC start
+ENDM
+Read_Adc_Result MACRO
+	mov	Temp1, ADC0L
+	mov	Temp2, ADC0H
+ENDM
+Stop_Adc MACRO
+ENDM
+Set_RPM_Out MACRO
+ENDM
+Clear_RPM_Out MACRO
+ENDM
+Set_MCU_Clk_24MHz MACRO
+	mov	CLKSEL, #13h		; Set clock to 24MHz
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #00h		; Set flash timing for 24MHz
+	mov	SFRPAGE, #00h
+	mov	Clock_Set_At_48MHz, #0
+ENDM
+Set_MCU_Clk_48MHz MACRO
+	mov	SFRPAGE, #10h
+	mov	PFE0CN, #30h		; Set flash timing for 48MHz
+	mov	SFRPAGE, #00h
+	mov	CLKSEL, #03h		; Set clock to 48MHz
+	mov	Clock_Set_At_48MHz, #1
+ENDM
+Set_LED_0 MACRO
+ENDM
+Clear_LED_0 MACRO
+ENDM
+Set_LED_1 MACRO
+ENDM
+Clear_LED_1 MACRO
+ENDM
+Set_LED_2 MACRO
+ENDM
+Clear_LED_2 MACRO
+ENDM
+Set_LED_3 MACRO
+ENDM
+Clear_LED_3 MACRO
+ENDM