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@ -133,7 +133,8 @@ Temp8 EQU R7 |
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;**** **** **** **** **** |
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;**** **** **** **** **** |
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; RAM definitions |
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; RAM definitions |
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DSEG AT 20h ; Ram data segment, bit-addressable |
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; Bit-addressable data segment |
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DSEG AT 20h |
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Bit_Access: DS 1 ; MUST BE AT THIS ADDRESS. Variable at bit accessible address (for non interrupt routines) |
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Bit_Access: DS 1 ; MUST BE AT THIS ADDRESS. Variable at bit accessible address (for non interrupt routines) |
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Bit_Access_Int: DS 1 ; Variable at bit accessible address (for interrupts) |
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Bit_Access_Int: DS 1 ; Variable at bit accessible address (for interrupts) |
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@ -169,7 +170,9 @@ Tlm_Data_L: DS 1 ; DShot telemetry data low byte |
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Tlm_Data_H: DS 1 ; DShot telemetry data high byte |
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Tlm_Data_H: DS 1 ; DShot telemetry data high byte |
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Tmp_B: DS 1 |
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Tmp_B: DS 1 |
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DSEG AT 30h ; Ram data segment, direct addressing |
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;**** **** **** **** **** |
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; Direct addressing data segment |
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DSEG AT 30h |
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Power_On_Wait_Cnt_L: DS 1 ; Power on wait counter (lo byte) |
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Power_On_Wait_Cnt_L: DS 1 ; Power on wait counter (lo byte) |
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Power_On_Wait_Cnt_H: DS 1 ; Power on wait counter (hi byte) |
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Power_On_Wait_Cnt_H: DS 1 ; Power on wait counter (hi byte) |
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@ -242,8 +245,9 @@ DShot_GCR_Pulse_Time_3_Tmp: DS 1 |
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DShot_GCR_Start_Delay: DS 1 |
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DShot_GCR_Start_Delay: DS 1 |
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; Indirect addressing data segment. The variables below must be in this sequence |
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ISEG AT 080h |
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;**** **** **** **** **** |
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; Indirect addressing data segments |
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ISEG AT 080h ; The variables below must be in this sequence |
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_Pgm_Gov_P_Gain: DS 1 ; Governor P gain |
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_Pgm_Gov_P_Gain: DS 1 ; Governor P gain |
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_Pgm_Gov_I_Gain: DS 1 ; Governor I gain |
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_Pgm_Gov_I_Gain: DS 1 ; Governor I gain |
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_Pgm_Gov_Mode: DS 1 ; Governor mode |
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_Pgm_Gov_Mode: DS 1 ; Governor mode |
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@ -286,7 +290,6 @@ Pgm_LED_Control: DS 1 ; LED control |
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; The sequence of the variables below is no longer of importance |
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; The sequence of the variables below is no longer of importance |
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Pgm_Startup_Pwr_Decoded: DS 1 ; Programmed startup power decoded |
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Pgm_Startup_Pwr_Decoded: DS 1 ; Programmed startup power decoded |
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; Indirect addressing data segments |
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ISEG AT 0B0h |
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ISEG AT 0B0h |
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Stack: DS 16 ; Reserved stack space |
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Stack: DS 16 ; Reserved stack space |
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@ -297,7 +300,8 @@ ISEG AT 0D0h |
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Temp_Storage: DS 48 ; Temporary storage |
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Temp_Storage: DS 48 ; Temporary storage |
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;**** **** **** **** **** |
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;**** **** **** **** **** |
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CSEG AT 1A00h ; "Eeprom" segment |
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; "EEPROM" code segments |
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CSEG AT 1A00h |
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EEPROM_FW_MAIN_REVISION EQU 0 ; Main revision of the firmware |
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EEPROM_FW_MAIN_REVISION EQU 0 ; Main revision of the firmware |
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EEPROM_FW_SUB_REVISION EQU 40 ; Sub revision of the firmware |
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EEPROM_FW_SUB_REVISION EQU 40 ; Sub revision of the firmware |
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EEPROM_LAYOUT_REVISION EQU 33 ; Revision of the EEPROM layout |
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EEPROM_LAYOUT_REVISION EQU 33 ; Revision of the EEPROM layout |
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