Fork from bluejay at github and modified for my custom ESC. I need to modify it because some mistake design on my ESC hardware.
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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hardware definition file "W". This is for tristate input style FET driver chips
  26. ; RC MC MB X CC MA X X X Ap Bp Cp X X X X
  27. ;
  28. ;**** **** **** **** ****
  29. ;*********************
  30. ; Device SiLabs EFM8BB1x/2x
  31. ;*********************
  32. IF MCU_48MHZ == 0
  33. $include (SI_EFM8BB1_Defs.inc)
  34. ELSE
  35. $include (SI_EFM8BB2_Defs.inc)
  36. ENDIF
  37. ;**** **** **** **** ****
  38. ; Uses internal calibrated oscillator set to 24/48Mhz
  39. ;**** **** **** **** ****
  40. ;**** **** **** **** ****
  41. ; Constant definitions
  42. ;**** **** **** **** ****
  43. IF MCU_48MHZ == 0
  44. CSEG AT 1A40h
  45. IF FETON_DELAY == 0
  46. Eep_ESC_Layout: DB "#W_L_00# " ; ESC layout tag
  47. ELSEIF FETON_DELAY == 5
  48. Eep_ESC_Layout: DB "#W_L_05# "
  49. ELSEIF FETON_DELAY == 10
  50. Eep_ESC_Layout: DB "#W_L_10# "
  51. ELSEIF FETON_DELAY == 15
  52. Eep_ESC_Layout: DB "#W_L_15# "
  53. ELSEIF FETON_DELAY == 20
  54. Eep_ESC_Layout: DB "#W_L_20# "
  55. ELSEIF FETON_DELAY == 25
  56. Eep_ESC_Layout: DB "#W_L_25# "
  57. ELSEIF FETON_DELAY == 30
  58. Eep_ESC_Layout: DB "#W_L_30# "
  59. ELSEIF FETON_DELAY == 40
  60. Eep_ESC_Layout: DB "#W_L_40# "
  61. ELSEIF FETON_DELAY == 50
  62. Eep_ESC_Layout: DB "#W_L_50# "
  63. ELSEIF FETON_DELAY == 70
  64. Eep_ESC_Layout: DB "#W_L_70# "
  65. ELSEIF FETON_DELAY == 90
  66. Eep_ESC_Layout: DB "#W_L_90# "
  67. ENDIF
  68. CSEG AT 1A50h
  69. Eep_ESC_MCU: DB "#BLHELI$EFM8B10#" ; Project and MCU tag (16 Bytes)
  70. ELSE
  71. CSEG AT 1A40h
  72. IF FETON_DELAY == 0
  73. Eep_ESC_Layout: DB "#W_H_00# " ; ESC layout tag
  74. ELSEIF FETON_DELAY == 5
  75. Eep_ESC_Layout: DB "#W_H_05# "
  76. ELSEIF FETON_DELAY == 10
  77. Eep_ESC_Layout: DB "#W_H_10# "
  78. ELSEIF FETON_DELAY == 15
  79. Eep_ESC_Layout: DB "#W_H_15# "
  80. ELSEIF FETON_DELAY == 20
  81. Eep_ESC_Layout: DB "#W_H_20# "
  82. ELSEIF FETON_DELAY == 25
  83. Eep_ESC_Layout: DB "#W_H_25# "
  84. ELSEIF FETON_DELAY == 30
  85. Eep_ESC_Layout: DB "#W_H_30# "
  86. ELSEIF FETON_DELAY == 40
  87. Eep_ESC_Layout: DB "#W_H_40# "
  88. ELSEIF FETON_DELAY == 50
  89. Eep_ESC_Layout: DB "#W_H_50# "
  90. ELSEIF FETON_DELAY == 70
  91. Eep_ESC_Layout: DB "#W_H_70# "
  92. ELSEIF FETON_DELAY == 90
  93. Eep_ESC_Layout: DB "#W_H_90# "
  94. ENDIF
  95. CSEG AT 1A50h
  96. Eep_ESC_MCU: DB "#BLHELI$EFM8B21#" ; Project and MCU tag (16 Bytes)
  97. ENDIF
  98. TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
  99. TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC
  100. ;**** **** **** **** ****
  101. ; Bootloader definitions
  102. ;**** **** **** **** ****
  103. RTX_PORT EQU P0 ; Receive/Transmit port
  104. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  105. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  106. RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP
  107. RTX_PIN EQU 7 ; RTX pin
  108. SIGNATURE_001 EQU 0E8h ; Device signature
  109. IF MCU_48MHZ == 0
  110. SIGNATURE_002 EQU 0B1h
  111. ELSE
  112. SIGNATURE_002 EQU 0B2h
  113. ENDIF
  114. ;*********************
  115. ; PORT 0 definitions *
  116. ;*********************
  117. Rcp_In EQU 7 ;i
  118. Mux_C EQU 6 ;i
  119. Mux_B EQU 5 ;i
  120. ; EQU 4 ;i
  121. Comp_Com EQU 3 ;i
  122. Mux_A EQU 2 ;i
  123. ; EQU 1 ;i
  124. ; EQU 0 ;i
  125. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  126. P0_INIT EQU 0FFh
  127. P0_PUSHPULL EQU 0
  128. P0_SKIP EQU 0FFh
  129. Get_Rcp_Capture_Values MACRO
  130. anl TCON, #0EFh ; Disable timer0
  131. mov Temp1, TL0 ; Get timer0 values
  132. mov Temp2, TH0
  133. IF MCU_48MHZ == 1
  134. mov Temp3, Timer0_X
  135. jnb TCON_TF0, ($+4) ; Check if interrupt is pending
  136. inc Temp3 ; If it is pending, then timer has already wrapped
  137. ENDIF
  138. mov TL0, #0 ; Reset timer0
  139. mov TH0, #0
  140. IF MCU_48MHZ == 1
  141. mov Timer0_X, #0
  142. ENDIF
  143. orl TCON, #10h ; Enable timer0 again
  144. IF MCU_48MHZ == 1
  145. mov A, Clock_Set_At_48MHz
  146. jnz Get_Rcp_End
  147. clr C
  148. mov A, Temp1
  149. rlc A
  150. mov Temp1, A
  151. mov A, Temp2
  152. rlc A
  153. mov Temp2, A
  154. mov A, Temp3
  155. rlc A
  156. mov Temp3, A
  157. Get_Rcp_End:
  158. ENDIF
  159. ENDM
  160. Decode_Dshot_2Msb MACRO
  161. movx A, @DPTR
  162. mov Temp6, A
  163. clr C
  164. subb A, Temp5 ; Subtract previous timestamp
  165. clr C
  166. subb A, Temp1
  167. jc t1_int_msb_fail ; Check that bit is longer than minimum
  168. subb A, Temp1 ; Check if bit is zero or one
  169. mov A, Temp4 ; Shift bit into data byte
  170. rlc A
  171. mov Temp4, A
  172. inc DPL ; Next bit
  173. movx A, @DPTR
  174. mov Temp5, A
  175. clr C
  176. subb A, Temp6
  177. clr C
  178. subb A, Temp1
  179. jc t1_int_msb_fail
  180. subb A, Temp1
  181. mov A, Temp4
  182. rlc A
  183. mov Temp4, A
  184. inc DPL
  185. ENDM
  186. Decode_Dshot_2Lsb MACRO
  187. movx A, @DPTR
  188. mov Temp6, A
  189. clr C
  190. subb A, Temp5 ; Subtract previous timestamp
  191. clr C
  192. subb A, Temp1
  193. jc t1_int_lsb_fail ; Check that bit is longer than minimum
  194. subb A, Temp1 ; Check if bit is zero or one
  195. mov A, Temp3 ; Shift bit into data byte
  196. rlc A
  197. mov Temp3, A
  198. inc DPL ; Next bit
  199. movx A, @DPTR
  200. mov Temp5, A
  201. clr C
  202. subb A, Temp6
  203. clr C
  204. subb A, Temp1
  205. jc t1_int_lsb_fail
  206. subb A, Temp1
  207. mov A, Temp3
  208. rlc A
  209. mov Temp3, A
  210. inc DPL
  211. ENDM
  212. Initialize_PCA MACRO
  213. mov PCA0CN0, #40h ; PCA enabled
  214. mov PCA0MD, #08h ; PCA clock is system clock
  215. IF FETON_DELAY == 0
  216. IF MCU_48MHZ == 0
  217. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  218. ELSE
  219. mov PCA0PWM, #83h ; PCA ARSEL set and 11bits pwm
  220. ENDIF
  221. mov PCA0CENT, #00h ; Edge aligned pwm
  222. ELSE
  223. IF MCU_48MHZ == 0
  224. mov PCA0PWM, #81h ; PCA ARSEL set and 9bits pwm
  225. ELSE
  226. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  227. ENDIF
  228. mov PCA0CENT, #03h ; Center aligned pwm
  229. ENDIF
  230. ENDM
  231. Set_Pwm_Polarity MACRO
  232. IF FETON_DELAY == 0
  233. mov PCA0POL, #00h ; Pwm noninverted
  234. ELSE
  235. mov PCA0POL, #01h ; Damping inverted, pwm noninverted
  236. ENDIF
  237. ENDM
  238. Enable_Power_Pwm_Module MACRO
  239. IF FETON_DELAY == 0
  240. mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode
  241. ELSE
  242. mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode
  243. ENDIF
  244. ENDM
  245. Enable_Damp_Pwm_Module MACRO
  246. IF FETON_DELAY == 0
  247. mov PCA0CPM1, #00h ; Disable
  248. ELSE
  249. mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode
  250. ENDIF
  251. ENDM
  252. Set_Power_Pwm_Regs MACRO
  253. IF FETON_DELAY == 0
  254. mov PCA0CPL0, Power_Pwm_Reg_L
  255. mov PCA0CPH0, Power_Pwm_Reg_H
  256. ELSE
  257. clr C
  258. mov A, Power_Pwm_Reg_H
  259. rrc A
  260. mov Temp1, A
  261. mov A, Power_Pwm_Reg_L
  262. rrc A
  263. mov PCA0CPL1, A
  264. mov PCA0CPH1, Temp1
  265. ENDIF
  266. ENDM
  267. Set_Damp_Pwm_Regs MACRO
  268. IF FETON_DELAY == 0
  269. mov PCA0CPL1, Damp_Pwm_Reg_L
  270. mov PCA0CPH1, Damp_Pwm_Reg_H
  271. ELSE
  272. clr C
  273. mov A, Damp_Pwm_Reg_H
  274. rrc A
  275. mov Temp1, A
  276. mov A, Damp_Pwm_Reg_L
  277. rrc A
  278. mov PCA0CPL0, A
  279. mov PCA0CPH0, Temp1
  280. ENDIF
  281. ENDM
  282. Clear_COVF_Interrupt MACRO
  283. anl PCA0PWM, #0DFh
  284. ENDM
  285. Clear_CCF_Interrupt MACRO ; CCF interrupt is only used for FETON_DELAY == 0
  286. anl PCA0CN0, #0FEh
  287. ENDM
  288. Enable_COVF_Interrupt MACRO
  289. orl PCA0PWM, #40h
  290. ENDM
  291. Enable_CCF_Interrupt MACRO
  292. orl PCA0CPM0,#01h
  293. ENDM
  294. Disable_COVF_Interrupt MACRO
  295. anl PCA0PWM, #0BFh
  296. ENDM
  297. Disable_CCF_Interrupt MACRO
  298. anl PCA0CPM0,#0FEh
  299. ENDM
  300. ;*********************
  301. ; PORT 1 definitions *
  302. ;*********************
  303. ; EQU 7 ;i
  304. ApwmFET EQU 6 ;o
  305. BpwmFET EQU 5 ;o
  306. CpwmFET EQU 4 ;o
  307. ; EQU 3 ;i
  308. ; EQU 2 ;i
  309. ; EQU 1 ;i
  310. ; EQU 0 ;i
  311. ; pwm outputs start as analog in -> floating
  312. ; this ensures all mosfet drivers start with floating outputs
  313. P1_DIGITAL EQU NOT((1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET))
  314. P1_INIT EQU 00h
  315. P1_PUSHPULL EQU ((1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET))
  316. ;
  317. P1_SKIP EQU 0FFh
  318. ApwmFET_on MACRO
  319. setb P1.ApwmFET ; set pin to high
  320. orl P1MDIN, #(1 SHL ApwmFET) ; enable pin driver
  321. ENDM
  322. ApwmFET_off MACRO
  323. anl P1MDIN, #(NOT(1 SHL ApwmFET)) ; analog in -> pullup, driver and digital in is disable = floating
  324. ENDM
  325. BpwmFET_on MACRO
  326. setb P1.BpwmFET ; set pin to high
  327. orl P1MDIN, #(1 SHL BpwmFET) ; enable pin driver
  328. ENDM
  329. BpwmFET_off MACRO
  330. anl P1MDIN, #(NOT(1 SHL BpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating
  331. ENDM
  332. CpwmFET_on MACRO
  333. setb P1.CpwmFET ; set pin to high
  334. orl P1MDIN, #(1 SHL CpwmFET) ; enable pin driver
  335. ENDM
  336. CpwmFET_off MACRO
  337. anl P1MDIN, #(NOT(1 SHL CpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating
  338. ENDM
  339. All_pwmFETs_Off MACRO
  340. anl P1MDIN, #(NOT((1 SHL ApwmFET) + (1 SHL BpwmFET) + (1 SHL CpwmFET))) ; analog in -> pullup, driver and digital in is disable = floating
  341. ENDM
  342. AcomFET_on MACRO
  343. clr P1.ApwmFET ; set pin to low
  344. orl P1MDIN, #(1 SHL ApwmFET) ; enable pin driver
  345. ENDM
  346. AcomFET_off MACRO
  347. anl P1MDIN, #(NOT(1 SHL ApwmFET)) ; analog in -> pullup, driver and digital in is disable = floating
  348. ENDM
  349. BcomFET_on MACRO
  350. clr P1.BpwmFET ; set pin to low
  351. orl P1MDIN, #(1 SHL BpwmFET) ; enable pin driver
  352. ENDM
  353. BcomFET_off MACRO
  354. anl P1MDIN, #(NOT(1 SHL BpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating
  355. ENDM
  356. CcomFET_on MACRO
  357. clr P1.CpwmFET ; set pin to low
  358. orl P1MDIN, #(1 SHL CpwmFET) ; enable pin driver
  359. ENDM
  360. CcomFET_off MACRO
  361. anl P1MDIN, #(NOT(1 SHL CpwmFET)) ; analog in -> pullup, driver and digital in is disable = floating
  362. ENDM
  363. All_comFETs_Off MACRO
  364. anl P1MDIN, #(NOT((1 SHL ApwmFET) + (1 SHL BpwmFET) + (1 SHL CpwmFET))) ; analog in -> pullup, driver and digital in is disable = floating
  365. ENDM
  366. Set_Pwm_A MACRO
  367. mov P1SKIP, #(NOT(1 SHL ApwmFET));
  368. orl P1MDIN, #(1 SHL ApwmFET) ; enable pin driver
  369. ENDM
  370. Set_Pwm_B MACRO
  371. mov P1SKIP, #(NOT(1 SHL BpwmFET));
  372. orl P1MDIN, #(1 SHL BpwmFET) ; enable pin driver
  373. ENDM
  374. Set_Pwm_C MACRO
  375. mov P1SKIP, #(NOT(1 SHL CpwmFET));
  376. orl P1MDIN, #(1 SHL CpwmFET) ; enable pin driver
  377. ENDM
  378. Set_Pwms_Off MACRO
  379. mov P1SKIP, #P1_SKIP;
  380. ENDM
  381. Set_Comp_Phase_A MACRO
  382. mov CMP0MX, #((Mux_A) SHL 4)+((Comp_Com) SHL 0);
  383. ENDM
  384. Set_Comp_Phase_B MACRO
  385. mov CMP0MX, #((Mux_B) SHL 4)+((Comp_Com) SHL 0);
  386. ENDM
  387. Set_Comp_Phase_C MACRO
  388. mov CMP0MX, #((Mux_C) SHL 4)+((Comp_Com) SHL 0);
  389. ENDM
  390. Read_Comp_Out MACRO
  391. mov A, CMP0CN0 ; Read comparator output
  392. ENDM
  393. ;*********************
  394. ; PORT 2 definitions *
  395. ;*********************
  396. DebugPin EQU 0 ;o
  397. P2_PUSHPULL EQU (1 SHL DebugPin)
  398. ;**********************
  399. ; MCU specific macros *
  400. ;**********************
  401. Interrupt_Table_Definition MACRO
  402. CSEG AT 0 ; Code segment start
  403. jmp reset
  404. CSEG AT 03h ; Int0 interrupt
  405. jmp int0_int
  406. IF MCU_48MHZ == 1
  407. CSEG AT 0Bh ; Timer0 overflow interrupt
  408. jmp t0_int
  409. ENDIF
  410. CSEG AT 13h ; Int1 interrupt
  411. jmp int1_int
  412. CSEG AT 1Bh ; Timer1 overflow interrupt
  413. jmp t1_int
  414. CSEG AT 2Bh ; Timer2 overflow interrupt
  415. jmp t2_int
  416. CSEG AT 5Bh ; Pca interrupt
  417. jmp pca_int
  418. CSEG AT 73h ; Timer3 overflow/compare interrupt
  419. jmp t3_int
  420. ENDM
  421. Initialize_Xbar MACRO
  422. mov XBR2, #40h ; Xbar enabled
  423. mov XBR1, #02h ; CEX0 and CEX1 routed to pins
  424. ENDM
  425. Initialize_Comparator MACRO
  426. mov CMP0CN0, #80h ; Comparator enabled, no hysteresis
  427. mov CMP0MD, #00h ; Comparator response time 100ns
  428. ENDM
  429. Initialize_Adc MACRO
  430. mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  431. IF MCU_48MHZ == 0
  432. mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1
  433. ELSE
  434. mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1
  435. ENDIF
  436. mov ADC0MX, #10h ; Select temp sensor input
  437. mov ADC0CN0, #80h ; ADC enabled
  438. mov ADC0CN1, #01h ; Common mode buffer enabled
  439. ENDM
  440. Start_Adc MACRO
  441. mov ADC0CN0, #90h ; ADC start
  442. ENDM
  443. Read_Adc_Result MACRO
  444. mov Temp1, ADC0L
  445. mov Temp2, ADC0H
  446. ENDM
  447. Stop_Adc MACRO
  448. ENDM
  449. Set_RPM_Out MACRO
  450. ENDM
  451. Clear_RPM_Out MACRO
  452. ENDM
  453. Set_MCU_Clk_24MHz MACRO
  454. mov CLKSEL, #13h ; Set clock to 24MHz
  455. mov SFRPAGE, #10h
  456. mov PFE0CN, #00h ; Set flash timing for 24MHz
  457. mov SFRPAGE, #00h
  458. mov Clock_Set_At_48MHz, #0
  459. ENDM
  460. Set_MCU_Clk_48MHz MACRO
  461. mov SFRPAGE, #10h
  462. mov PFE0CN, #30h ; Set flash timing for 48MHz
  463. mov SFRPAGE, #00h
  464. mov CLKSEL, #03h ; Set clock to 48MHz
  465. mov Clock_Set_At_48MHz, #1
  466. ENDM
  467. Set_LED_0 MACRO
  468. ENDM
  469. Clear_LED_0 MACRO
  470. ENDM
  471. Set_LED_1 MACRO
  472. ENDM
  473. Clear_LED_1 MACRO
  474. ENDM
  475. Set_LED_2 MACRO
  476. ENDM
  477. Clear_LED_2 MACRO
  478. ENDM
  479. Set_LED_3 MACRO
  480. ENDM
  481. Clear_LED_3 MACRO
  482. ENDM