Fork from bluejay at github and modified for my custom ESC. I need to modify it because some mistake design on my ESC hardware.
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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hardware definition file "I"
  26. ; X X RC X MC MB MA CC X X Ac Bc Cc Ap Bp Cp
  27. ;
  28. ;**** **** **** **** ****
  29. ;*********************
  30. ; Device SiLabs EFM8BB1x/2x
  31. ;*********************
  32. IF MCU_48MHZ == 0
  33. $include (SI_EFM8BB1_Defs.inc)
  34. ELSE
  35. $include (SI_EFM8BB2_Defs.inc)
  36. ENDIF
  37. ;**** **** **** **** ****
  38. ; Uses internal calibrated oscillator set to 24/48Mhz
  39. ;**** **** **** **** ****
  40. ;**** **** **** **** ****
  41. ; Constant definitions
  42. ;**** **** **** **** ****
  43. IF MCU_48MHZ == 0
  44. CSEG AT 1A40h
  45. IF FETON_DELAY == 0
  46. Eep_ESC_Layout: DB "#I_L_00# " ; ESC layout tag
  47. ELSEIF FETON_DELAY == 5
  48. Eep_ESC_Layout: DB "#I_L_05# "
  49. ELSEIF FETON_DELAY == 10
  50. Eep_ESC_Layout: DB "#I_L_10# "
  51. ELSEIF FETON_DELAY == 15
  52. Eep_ESC_Layout: DB "#I_L_15# "
  53. ELSEIF FETON_DELAY == 20
  54. Eep_ESC_Layout: DB "#I_L_20# "
  55. ELSEIF FETON_DELAY == 25
  56. Eep_ESC_Layout: DB "#I_L_25# "
  57. ELSEIF FETON_DELAY == 30
  58. Eep_ESC_Layout: DB "#I_L_30# "
  59. ELSEIF FETON_DELAY == 40
  60. Eep_ESC_Layout: DB "#I_L_40# "
  61. ELSEIF FETON_DELAY == 50
  62. Eep_ESC_Layout: DB "#I_L_50# "
  63. ELSEIF FETON_DELAY == 70
  64. Eep_ESC_Layout: DB "#I_L_70# "
  65. ELSEIF FETON_DELAY == 90
  66. Eep_ESC_Layout: DB "#I_L_90# "
  67. ENDIF
  68. CSEG AT 1A50h
  69. Eep_ESC_MCU: DB "#BLHELI$EFM8B10#" ; Project and MCU tag (16 Bytes)
  70. ELSE
  71. CSEG AT 1A40h
  72. IF FETON_DELAY == 0
  73. Eep_ESC_Layout: DB "#I_H_00# " ; ESC layout tag
  74. ELSEIF FETON_DELAY == 5
  75. Eep_ESC_Layout: DB "#I_H_05# "
  76. ELSEIF FETON_DELAY == 10
  77. Eep_ESC_Layout: DB "#I_H_10# "
  78. ELSEIF FETON_DELAY == 15
  79. Eep_ESC_Layout: DB "#I_H_15# "
  80. ELSEIF FETON_DELAY == 20
  81. Eep_ESC_Layout: DB "#I_H_20# "
  82. ELSEIF FETON_DELAY == 25
  83. Eep_ESC_Layout: DB "#I_H_25# "
  84. ELSEIF FETON_DELAY == 30
  85. Eep_ESC_Layout: DB "#I_H_30# "
  86. ELSEIF FETON_DELAY == 40
  87. Eep_ESC_Layout: DB "#I_H_40# "
  88. ELSEIF FETON_DELAY == 50
  89. Eep_ESC_Layout: DB "#I_H_50# "
  90. ELSEIF FETON_DELAY == 70
  91. Eep_ESC_Layout: DB "#I_H_70# "
  92. ELSEIF FETON_DELAY == 90
  93. Eep_ESC_Layout: DB "#I_H_90# "
  94. ENDIF
  95. CSEG AT 1A50h
  96. Eep_ESC_MCU: DB "#BLHELI$EFM8B21#" ; Project and MCU tag (16 Bytes)
  97. ENDIF
  98. TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
  99. TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC
  100. ;**** **** **** **** ****
  101. ; Bootloader definitions
  102. ;**** **** **** **** ****
  103. RTX_PORT EQU P0 ; Receive/Transmit port
  104. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  105. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  106. RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP
  107. RTX_PIN EQU 5 ; RTX pin
  108. SIGNATURE_001 EQU 0E8h ; Device signature
  109. IF MCU_48MHZ == 0
  110. SIGNATURE_002 EQU 0B1h
  111. ELSE
  112. SIGNATURE_002 EQU 0B2h
  113. ENDIF
  114. ;*********************
  115. ; PORT 0 definitions *
  116. ;*********************
  117. ; EQU 7 ;i
  118. ; EQU 6 ;i
  119. Rcp_In EQU 5 ;i
  120. ; EQU 4 ;i
  121. Mux_C EQU 3 ;i
  122. Mux_B EQU 2 ;i
  123. Mux_A EQU 1 ;i
  124. Comp_Com EQU 0 ;i
  125. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  126. P0_INIT EQU 0FFh
  127. P0_PUSHPULL EQU 0
  128. P0_SKIP EQU 0FFh
  129. Get_Rcp_Capture_Values MACRO
  130. anl TCON, #0EFh ; Disable timer0
  131. mov Temp1, TL0 ; Get timer0 values
  132. mov Temp2, TH0
  133. IF MCU_48MHZ == 1
  134. mov Temp3, Timer0_X
  135. jnb TCON_TF0, ($+4) ; Check if interrupt is pending
  136. inc Temp3 ; If it is pending, then timer has already wrapped
  137. ENDIF
  138. mov TL0, #0 ; Reset timer0
  139. mov TH0, #0
  140. IF MCU_48MHZ == 1
  141. mov Timer0_X, #0
  142. ENDIF
  143. orl TCON, #10h ; Enable timer0 again
  144. IF MCU_48MHZ == 1
  145. mov A, Clock_Set_At_48MHz
  146. jnz Get_Rcp_End
  147. clr C
  148. mov A, Temp1
  149. rlc A
  150. mov Temp1, A
  151. mov A, Temp2
  152. rlc A
  153. mov Temp2, A
  154. mov A, Temp3
  155. rlc A
  156. mov Temp3, A
  157. Get_Rcp_End:
  158. ENDIF
  159. ENDM
  160. Decode_Dshot_2Msb MACRO
  161. movx A, @DPTR
  162. mov Temp6, A
  163. clr C
  164. subb A, Temp5 ; Subtract previous timestamp
  165. clr C
  166. subb A, Temp1
  167. jc t1_int_msb_fail ; Check that bit is longer than minimum
  168. subb A, Temp1 ; Check if bit is zero or one
  169. mov A, Temp4 ; Shift bit into data byte
  170. rlc A
  171. mov Temp4, A
  172. inc DPL ; Next bit
  173. movx A, @DPTR
  174. mov Temp5, A
  175. clr C
  176. subb A, Temp6
  177. clr C
  178. subb A, Temp1
  179. jc t1_int_msb_fail
  180. subb A, Temp1
  181. mov A, Temp4
  182. rlc A
  183. mov Temp4, A
  184. inc DPL
  185. ENDM
  186. Decode_Dshot_2Lsb MACRO
  187. movx A, @DPTR
  188. mov Temp6, A
  189. clr C
  190. subb A, Temp5 ; Subtract previous timestamp
  191. clr C
  192. subb A, Temp1
  193. jc t1_int_lsb_fail ; Check that bit is longer than minimum
  194. subb A, Temp1 ; Check if bit is zero or one
  195. mov A, Temp3 ; Shift bit into data byte
  196. rlc A
  197. mov Temp3, A
  198. inc DPL ; Next bit
  199. movx A, @DPTR
  200. mov Temp5, A
  201. clr C
  202. subb A, Temp6
  203. clr C
  204. subb A, Temp1
  205. jc t1_int_lsb_fail
  206. subb A, Temp1
  207. mov A, Temp3
  208. rlc A
  209. mov Temp3, A
  210. inc DPL
  211. ENDM
  212. Initialize_PCA MACRO
  213. mov PCA0CN0, #40h ; PCA enabled
  214. mov PCA0MD, #08h ; PCA clock is system clock
  215. IF FETON_DELAY == 0
  216. IF MCU_48MHZ == 0
  217. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  218. ELSE
  219. mov PCA0PWM, #83h ; PCA ARSEL set and 11bits pwm
  220. ENDIF
  221. mov PCA0CENT, #00h ; Edge aligned pwm
  222. ELSE
  223. IF MCU_48MHZ == 0
  224. mov PCA0PWM, #81h ; PCA ARSEL set and 9bits pwm
  225. ELSE
  226. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  227. ENDIF
  228. mov PCA0CENT, #03h ; Center aligned pwm
  229. ENDIF
  230. ENDM
  231. Set_Pwm_Polarity MACRO
  232. mov PCA0POL, #02h ; Damping inverted, pwm noninverted
  233. ENDM
  234. Enable_Power_Pwm_Module MACRO
  235. IF FETON_DELAY == 0
  236. mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode
  237. ELSE
  238. mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode
  239. ENDIF
  240. ENDM
  241. Enable_Damp_Pwm_Module MACRO
  242. IF FETON_DELAY == 0
  243. mov PCA0CPM1, #00h ; Disable
  244. ELSE
  245. mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode
  246. ENDIF
  247. ENDM
  248. Set_Power_Pwm_Regs MACRO
  249. IF FETON_DELAY == 0
  250. mov PCA0CPL0, Power_Pwm_Reg_L
  251. mov PCA0CPH0, Power_Pwm_Reg_H
  252. ELSE
  253. clr C
  254. mov A, Power_Pwm_Reg_H
  255. rrc A
  256. mov Temp1, A
  257. mov A, Power_Pwm_Reg_L
  258. rrc A
  259. mov PCA0CPL0, A
  260. mov PCA0CPH0, Temp1
  261. ENDIF
  262. ENDM
  263. Set_Damp_Pwm_Regs MACRO
  264. IF FETON_DELAY == 0
  265. mov PCA0CPL1, Damp_Pwm_Reg_L
  266. mov PCA0CPH1, Damp_Pwm_Reg_H
  267. ELSE
  268. clr C
  269. mov A, Damp_Pwm_Reg_H
  270. rrc A
  271. mov Temp1, A
  272. mov A, Damp_Pwm_Reg_L
  273. rrc A
  274. mov PCA0CPL1, A
  275. mov PCA0CPH1, Temp1
  276. ENDIF
  277. ENDM
  278. Clear_COVF_Interrupt MACRO
  279. anl PCA0PWM, #0DFh
  280. ENDM
  281. Clear_CCF_Interrupt MACRO
  282. anl PCA0CN0, #0FEh
  283. ENDM
  284. Enable_COVF_Interrupt MACRO
  285. orl PCA0PWM, #40h
  286. ENDM
  287. Enable_CCF_Interrupt MACRO
  288. orl PCA0CPM0,#01h
  289. ENDM
  290. Disable_COVF_Interrupt MACRO
  291. anl PCA0PWM, #0BFh
  292. ENDM
  293. Disable_CCF_Interrupt MACRO
  294. anl PCA0CPM0,#0FEh
  295. ENDM
  296. ;*********************
  297. ; PORT 1 definitions *
  298. ;*********************
  299. ; EQU 7 ;i
  300. ; EQU 6 ;i
  301. AcomFET EQU 5 ;o
  302. BcomFET EQU 4 ;o
  303. CcomFET EQU 3 ;o
  304. ApwmFET EQU 2 ;o
  305. BpwmFET EQU 1 ;o
  306. CpwmFET EQU 0 ;o
  307. P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
  308. P1_INIT EQU 00h
  309. P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
  310. P1_SKIP EQU 3Fh
  311. ApwmFET_on MACRO
  312. setb P1.ApwmFET
  313. IF FETON_DELAY == 0
  314. setb P1.AcomFET
  315. ENDIF
  316. ENDM
  317. ApwmFET_off MACRO
  318. IF FETON_DELAY != 0
  319. clr P1.ApwmFET
  320. ELSE
  321. clr P1.AcomFET
  322. ENDIF
  323. ENDM
  324. BpwmFET_on MACRO
  325. setb P1.BpwmFET
  326. IF FETON_DELAY == 0
  327. setb P1.BcomFET
  328. ENDIF
  329. ENDM
  330. BpwmFET_off MACRO
  331. IF FETON_DELAY != 0
  332. clr P1.BpwmFET
  333. ELSE
  334. clr P1.BcomFET
  335. ENDIF
  336. ENDM
  337. CpwmFET_on MACRO
  338. setb P1.CpwmFET
  339. IF FETON_DELAY == 0
  340. setb P1.CcomFET
  341. ENDIF
  342. ENDM
  343. CpwmFET_off MACRO
  344. IF FETON_DELAY != 0
  345. clr P1.CpwmFET
  346. ELSE
  347. clr P1.CcomFET
  348. ENDIF
  349. ENDM
  350. All_pwmFETs_Off MACRO
  351. IF FETON_DELAY != 0
  352. clr P1.ApwmFET
  353. clr P1.BpwmFET
  354. clr P1.CpwmFET
  355. ELSE
  356. clr P1.AcomFET
  357. clr P1.BcomFET
  358. clr P1.CcomFET
  359. ENDIF
  360. ENDM
  361. AcomFET_on MACRO
  362. IF FETON_DELAY == 0
  363. clr P1.ApwmFET
  364. ENDIF
  365. setb P1.AcomFET
  366. ENDM
  367. AcomFET_off MACRO
  368. clr P1.AcomFET
  369. ENDM
  370. BcomFET_on MACRO
  371. IF FETON_DELAY == 0
  372. clr P1.BpwmFET
  373. ENDIF
  374. setb P1.BcomFET
  375. ENDM
  376. BcomFET_off MACRO
  377. clr P1.BcomFET
  378. ENDM
  379. CcomFET_on MACRO
  380. IF FETON_DELAY == 0
  381. clr P1.CpwmFET
  382. ENDIF
  383. setb P1.CcomFET
  384. ENDM
  385. CcomFET_off MACRO
  386. clr P1.CcomFET
  387. ENDM
  388. All_comFETs_Off MACRO
  389. clr P1.AcomFET
  390. clr P1.BcomFET
  391. clr P1.CcomFET
  392. ENDM
  393. Set_Pwm_A MACRO
  394. IF FETON_DELAY == 0
  395. setb P1.AcomFET
  396. mov P1SKIP, #3Bh
  397. ELSE
  398. mov P1SKIP, #1Bh
  399. ENDIF
  400. ENDM
  401. Set_Pwm_B MACRO
  402. IF FETON_DELAY == 0
  403. setb P1.BcomFET
  404. mov P1SKIP, #3Dh
  405. ELSE
  406. mov P1SKIP, #2Dh
  407. ENDIF
  408. ENDM
  409. Set_Pwm_C MACRO
  410. IF FETON_DELAY == 0
  411. setb P1.CcomFET
  412. mov P1SKIP, #3Eh
  413. ELSE
  414. mov P1SKIP, #36h
  415. ENDIF
  416. ENDM
  417. Set_Pwms_Off MACRO
  418. mov P1SKIP, #7Fh
  419. ENDM
  420. Set_Comp_Phase_A MACRO
  421. mov CMP0MX, #10h ; Set comparator multiplexer to phase A
  422. ENDM
  423. Set_Comp_Phase_B MACRO
  424. mov CMP0MX, #20h ; Set comparator multiplexer to phase B
  425. ENDM
  426. Set_Comp_Phase_C MACRO
  427. mov CMP0MX, #30h ; Set comparator multiplexer to phase C
  428. ENDM
  429. Read_Comp_Out MACRO
  430. mov A, CMP0CN0 ; Read comparator output
  431. ENDM
  432. ;*********************
  433. ; PORT 2 definitions *
  434. ;*********************
  435. DebugPin EQU 0 ;o
  436. P2_PUSHPULL EQU (1 SHL DebugPin)
  437. ;**********************
  438. ; MCU specific macros *
  439. ;**********************
  440. Interrupt_Table_Definition MACRO
  441. CSEG AT 0 ; Code segment start
  442. jmp reset
  443. CSEG AT 03h ; Int0 interrupt
  444. jmp int0_int
  445. IF MCU_48MHZ == 1
  446. CSEG AT 0Bh ; Timer0 overflow interrupt
  447. jmp t0_int
  448. ENDIF
  449. CSEG AT 13h ; Int1 interrupt
  450. jmp int1_int
  451. CSEG AT 1Bh ; Timer1 overflow interrupt
  452. jmp t1_int
  453. CSEG AT 2Bh ; Timer2 overflow interrupt
  454. jmp t2_int
  455. CSEG AT 5Bh ; Pca interrupt
  456. jmp pca_int
  457. CSEG AT 73h ; Timer3 overflow/compare interrupt
  458. jmp t3_int
  459. ENDM
  460. Initialize_Xbar MACRO
  461. mov XBR2, #40h ; Xbar enabled
  462. mov XBR1, #02h ; CEX0 and CEX1 routed to pins
  463. ENDM
  464. Initialize_Comparator MACRO
  465. mov CMP0CN0, #80h ; Comparator enabled, no hysteresis
  466. mov CMP0MD, #00h ; Comparator response time 100ns
  467. ENDM
  468. Initialize_Adc MACRO
  469. mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  470. IF MCU_48MHZ == 0
  471. mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1
  472. ELSE
  473. mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1
  474. ENDIF
  475. mov ADC0MX, #10h ; Select temp sensor input
  476. mov ADC0CN0, #80h ; ADC enabled
  477. mov ADC0CN1, #01h ; Common mode buffer enabled
  478. ENDM
  479. Start_Adc MACRO
  480. mov ADC0CN0, #90h ; ADC start
  481. ENDM
  482. Read_Adc_Result MACRO
  483. mov Temp1, ADC0L
  484. mov Temp2, ADC0H
  485. ENDM
  486. Stop_Adc MACRO
  487. ENDM
  488. Set_RPM_Out MACRO
  489. ENDM
  490. Clear_RPM_Out MACRO
  491. ENDM
  492. Set_MCU_Clk_24MHz MACRO
  493. mov CLKSEL, #13h ; Set clock to 24MHz
  494. mov SFRPAGE, #10h
  495. mov PFE0CN, #00h ; Set flash timing for 24MHz
  496. mov SFRPAGE, #00h
  497. mov Clock_Set_At_48MHz, #0
  498. ENDM
  499. Set_MCU_Clk_48MHz MACRO
  500. mov SFRPAGE, #10h
  501. mov PFE0CN, #30h ; Set flash timing for 48MHz
  502. mov SFRPAGE, #00h
  503. mov CLKSEL, #03h ; Set clock to 48MHz
  504. mov Clock_Set_At_48MHz, #1
  505. ENDM
  506. Set_LED_0 MACRO
  507. ENDM
  508. Clear_LED_0 MACRO
  509. ENDM
  510. Set_LED_1 MACRO
  511. ENDM
  512. Clear_LED_1 MACRO
  513. ENDM
  514. Set_LED_2 MACRO
  515. ENDM
  516. Clear_LED_2 MACRO
  517. ENDM
  518. Set_LED_3 MACRO
  519. ENDM
  520. Clear_LED_3 MACRO
  521. ENDM