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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hardware definition file "G"
  26. ; X X RC X CC MA MC MB X X Cc Cp Bc Bp Ac Ap
  27. ;
  28. ;**** **** **** **** ****
  29. ;*********************
  30. ; Device SiLabs EFM8BB1x/2x
  31. ;*********************
  32. IF MCU_48MHZ == 0
  33. $include (SI_EFM8BB1_Defs.inc)
  34. ELSE
  35. $include (SI_EFM8BB2_Defs.inc)
  36. ENDIF
  37. ;**** **** **** **** ****
  38. ; Uses internal calibrated oscillator set to 24/48Mhz
  39. ;**** **** **** **** ****
  40. ;**** **** **** **** ****
  41. ; Constant definitions
  42. ;**** **** **** **** ****
  43. IF MCU_48MHZ == 0
  44. CSEG AT 1A40h
  45. IF FETON_DELAY == 0
  46. Eep_ESC_Layout: DB "#G_L_00# " ; ESC layout tag
  47. ELSEIF FETON_DELAY == 5
  48. Eep_ESC_Layout: DB "#G_L_05# "
  49. ELSEIF FETON_DELAY == 10
  50. Eep_ESC_Layout: DB "#G_L_10# "
  51. ELSEIF FETON_DELAY == 15
  52. Eep_ESC_Layout: DB "#G_L_15# "
  53. ELSEIF FETON_DELAY == 20
  54. Eep_ESC_Layout: DB "#G_L_20# "
  55. ELSEIF FETON_DELAY == 25
  56. Eep_ESC_Layout: DB "#G_L_25# "
  57. ELSEIF FETON_DELAY == 30
  58. Eep_ESC_Layout: DB "#G_L_30# "
  59. ELSEIF FETON_DELAY == 40
  60. Eep_ESC_Layout: DB "#G_L_40# "
  61. ELSEIF FETON_DELAY == 50
  62. Eep_ESC_Layout: DB "#G_L_50# "
  63. ELSEIF FETON_DELAY == 70
  64. Eep_ESC_Layout: DB "#G_L_70# "
  65. ELSEIF FETON_DELAY == 90
  66. Eep_ESC_Layout: DB "#G_L_90# "
  67. ENDIF
  68. CSEG AT 1A50h
  69. Eep_ESC_MCU: DB "#BLHELI$EFM8B10#" ; Project and MCU tag (16 Bytes)
  70. ELSE
  71. CSEG AT 1A40h
  72. IF FETON_DELAY == 0
  73. Eep_ESC_Layout: DB "#G_H_00# " ; ESC layout tag
  74. ELSEIF FETON_DELAY == 5
  75. Eep_ESC_Layout: DB "#G_H_05# "
  76. ELSEIF FETON_DELAY == 10
  77. Eep_ESC_Layout: DB "#G_H_10# "
  78. ELSEIF FETON_DELAY == 15
  79. Eep_ESC_Layout: DB "#G_H_15# "
  80. ELSEIF FETON_DELAY == 20
  81. Eep_ESC_Layout: DB "#G_H_20# "
  82. ELSEIF FETON_DELAY == 25
  83. Eep_ESC_Layout: DB "#G_H_25# "
  84. ELSEIF FETON_DELAY == 30
  85. Eep_ESC_Layout: DB "#G_H_30# "
  86. ELSEIF FETON_DELAY == 40
  87. Eep_ESC_Layout: DB "#G_H_40# "
  88. ELSEIF FETON_DELAY == 50
  89. Eep_ESC_Layout: DB "#G_H_50# "
  90. ELSEIF FETON_DELAY == 70
  91. Eep_ESC_Layout: DB "#G_H_70# "
  92. ELSEIF FETON_DELAY == 90
  93. Eep_ESC_Layout: DB "#G_H_90# "
  94. ENDIF
  95. CSEG AT 1A50h
  96. Eep_ESC_MCU: DB "#BLHELI$EFM8B21#" ; Project and MCU tag (16 Bytes)
  97. ENDIF
  98. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  99. LOCK_BYTE_ADDRESS_16K EQU 3FFFh ; Address of lock byte if 16k flash size
  100. LOCK_BYTE_ADDRESS_8K EQU 1DFFh ; Address of lock byte if 8k flash size
  101. TEMP_LIMIT EQU 246 ; Temperature measurement ADC value for which main motor power is limited (low byte, assuming high byte is 1)
  102. TEMP_LIMIT_STEP EQU 6 ; Temperature measurement ADC value increment for which main motor power is further limited
  103. ;**** **** **** **** ****
  104. ; Bootloader definitions
  105. ;**** **** **** **** ****
  106. RTX_PORT EQU P0 ; Receive/Transmit port
  107. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  108. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  109. RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP
  110. RTX_PIN EQU 5 ; RTX pin
  111. SIGNATURE_001 EQU 0E8h ; Device signature
  112. IF MCU_48MHZ == 0
  113. SIGNATURE_002 EQU 0B1h
  114. ELSE
  115. SIGNATURE_002 EQU 0B2h
  116. ENDIF
  117. ;*********************
  118. ; PORT 0 definitions *
  119. ;*********************
  120. ; EQU 7 ;i
  121. ; EQU 6 ;i
  122. Rcp_In EQU 5 ;i
  123. ; EQU 4 ;i
  124. Mux_C EQU 3 ;i
  125. Mux_B EQU 2 ;i
  126. Mux_A EQU 1 ;i
  127. Comp_Com EQU 0 ;i
  128. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  129. P0_INIT EQU 0FFh
  130. P0_PUSHPULL EQU 0
  131. P0_SKIP EQU 0FFh
  132. Get_Rcp_Capture_Values MACRO
  133. anl TCON, #0EFh ; Disable timer0
  134. mov Temp1, TL0 ; Get timer0 values
  135. mov Temp2, TH0
  136. IF MCU_48MHZ == 1
  137. mov Temp3, Timer0_X
  138. jnb TCON_TF0, ($+4) ; Check if interrupt is pending
  139. inc Temp3 ; If it is pending, then timer has already wrapped
  140. ENDIF
  141. mov TL0, #0 ; Reset timer0
  142. mov TH0, #0
  143. IF MCU_48MHZ == 1
  144. mov Timer0_X, #0
  145. ENDIF
  146. orl TCON, #10h ; Enable timer0 again
  147. IF MCU_48MHZ == 1
  148. mov A, Clock_Set_At_48MHz
  149. jnz Get_Rcp_End
  150. clr C
  151. mov A, Temp1
  152. rlc A
  153. mov Temp1, A
  154. mov A, Temp2
  155. rlc A
  156. mov Temp2, A
  157. mov A, Temp3
  158. rlc A
  159. mov Temp3, A
  160. Get_Rcp_End:
  161. ENDIF
  162. ENDM
  163. Initialize_PCA MACRO
  164. mov PCA0CN0, #40h ; PCA enabled
  165. mov PCA0MD, #08h ; PCA clock is system clock
  166. IF FETON_DELAY == 0
  167. IF MCU_48MHZ == 0
  168. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  169. ELSE
  170. mov PCA0PWM, #83h ; PCA ARSEL set and 11bits pwm
  171. ENDIF
  172. mov PCA0CENT, #00h ; Edge aligned pwm
  173. ELSE
  174. IF MCU_48MHZ == 0
  175. mov PCA0PWM, #81h ; PCA ARSEL set and 9bits pwm
  176. ELSE
  177. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  178. ENDIF
  179. mov PCA0CENT, #03h ; Center aligned pwm
  180. ENDIF
  181. ENDM
  182. Set_Pwm_Polarity MACRO
  183. mov PCA0POL, #02h ; Damping inverted, pwm noninverted
  184. ENDM
  185. Enable_Power_Pwm_Module MACRO
  186. IF FETON_DELAY == 0
  187. mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode
  188. ELSE
  189. mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode
  190. ENDIF
  191. ENDM
  192. Enable_Damp_Pwm_Module MACRO
  193. IF FETON_DELAY == 0
  194. mov PCA0CPM1, #00h ; Disable
  195. ELSE
  196. mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode
  197. ENDIF
  198. ENDM
  199. Set_Power_Pwm_Regs MACRO
  200. IF FETON_DELAY == 0
  201. mov PCA0CPL0, Power_Pwm_Reg_L
  202. mov PCA0CPH0, Power_Pwm_Reg_H
  203. ELSE
  204. clr C
  205. mov A, Power_Pwm_Reg_H
  206. rrc A
  207. mov Temp1, A
  208. mov A, Power_Pwm_Reg_L
  209. rrc A
  210. mov PCA0CPL0, A
  211. mov PCA0CPH0, Temp1
  212. ENDIF
  213. ENDM
  214. Set_Damp_Pwm_Regs MACRO
  215. IF FETON_DELAY == 0
  216. mov PCA0CPL1, Damp_Pwm_Reg_L
  217. mov PCA0CPH1, Damp_Pwm_Reg_H
  218. ELSE
  219. clr C
  220. mov A, Damp_Pwm_Reg_H
  221. rrc A
  222. mov Temp1, A
  223. mov A, Damp_Pwm_Reg_L
  224. rrc A
  225. mov PCA0CPL1, A
  226. mov PCA0CPH1, Temp1
  227. ENDIF
  228. ENDM
  229. Clear_COVF_Interrupt MACRO
  230. anl PCA0PWM, #0DFh
  231. ENDM
  232. Clear_CCF_Interrupt MACRO
  233. anl PCA0CN0, #0FEh
  234. ENDM
  235. Enable_COVF_Interrupt MACRO
  236. orl PCA0PWM, #40h
  237. ENDM
  238. Enable_CCF_Interrupt MACRO
  239. orl PCA0CPM0,#01h
  240. ENDM
  241. Disable_COVF_Interrupt MACRO
  242. anl PCA0PWM, #0BFh
  243. ENDM
  244. Disable_CCF_Interrupt MACRO
  245. anl PCA0CPM0,#0FEh
  246. ENDM
  247. ;*********************
  248. ; PORT 1 definitions *
  249. ;*********************
  250. ; EQU 7 ;i
  251. ; EQU 6 ;i
  252. CcomFET EQU 5 ;o
  253. CpwmFET EQU 4 ;o
  254. BcomFET EQU 3 ;o
  255. BpwmFET EQU 2 ;o
  256. AcomFET EQU 1 ;o
  257. ApwmFET EQU 0 ;o
  258. P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
  259. P1_INIT EQU 00h
  260. P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
  261. P1_SKIP EQU 3Fh
  262. ApwmFET_on MACRO
  263. setb P1.ApwmFET
  264. IF FETON_DELAY == 0
  265. setb P1.AcomFET
  266. ENDIF
  267. ENDM
  268. ApwmFET_off MACRO
  269. IF FETON_DELAY != 0
  270. clr P1.ApwmFET
  271. ELSE
  272. clr P1.AcomFET
  273. ENDIF
  274. ENDM
  275. BpwmFET_on MACRO
  276. setb P1.BpwmFET
  277. IF FETON_DELAY == 0
  278. setb P1.BcomFET
  279. ENDIF
  280. ENDM
  281. BpwmFET_off MACRO
  282. IF FETON_DELAY != 0
  283. clr P1.BpwmFET
  284. ELSE
  285. clr P1.BcomFET
  286. ENDIF
  287. ENDM
  288. CpwmFET_on MACRO
  289. setb P1.CpwmFET
  290. IF FETON_DELAY == 0
  291. setb P1.CcomFET
  292. ENDIF
  293. ENDM
  294. CpwmFET_off MACRO
  295. IF FETON_DELAY != 0
  296. clr P1.CpwmFET
  297. ELSE
  298. clr P1.CcomFET
  299. ENDIF
  300. ENDM
  301. All_pwmFETs_Off MACRO
  302. IF FETON_DELAY != 0
  303. clr P1.ApwmFET
  304. clr P1.BpwmFET
  305. clr P1.CpwmFET
  306. ELSE
  307. clr P1.AcomFET
  308. clr P1.BcomFET
  309. clr P1.CcomFET
  310. ENDIF
  311. ENDM
  312. AcomFET_on MACRO
  313. IF FETON_DELAY == 0
  314. clr P1.ApwmFET
  315. ENDIF
  316. setb P1.AcomFET
  317. ENDM
  318. AcomFET_off MACRO
  319. clr P1.AcomFET
  320. ENDM
  321. BcomFET_on MACRO
  322. IF FETON_DELAY == 0
  323. clr P1.BpwmFET
  324. ENDIF
  325. setb P1.BcomFET
  326. ENDM
  327. BcomFET_off MACRO
  328. clr P1.BcomFET
  329. ENDM
  330. CcomFET_on MACRO
  331. IF FETON_DELAY == 0
  332. clr P1.CpwmFET
  333. ENDIF
  334. setb P1.CcomFET
  335. ENDM
  336. CcomFET_off MACRO
  337. clr P1.CcomFET
  338. ENDM
  339. All_comFETs_Off MACRO
  340. clr P1.AcomFET
  341. clr P1.BcomFET
  342. clr P1.CcomFET
  343. ENDM
  344. Set_Pwm_A MACRO
  345. IF FETON_DELAY == 0
  346. setb P1.AcomFET
  347. mov P1SKIP, #3Eh
  348. ELSE
  349. mov P1SKIP, #3Ch
  350. ENDIF
  351. ENDM
  352. Set_Pwm_B MACRO
  353. IF FETON_DELAY == 0
  354. setb P1.BcomFET
  355. mov P1SKIP, #3Bh
  356. ELSE
  357. mov P1SKIP, #33h
  358. ENDIF
  359. ENDM
  360. Set_Pwm_C MACRO
  361. IF FETON_DELAY == 0
  362. setb P1.CcomFET
  363. mov P1SKIP, #2Fh
  364. ELSE
  365. mov P1SKIP, #0Fh
  366. ENDIF
  367. ENDM
  368. Set_Pwms_Off MACRO
  369. mov P1SKIP, #3Fh
  370. ENDM
  371. Set_Comp_Phase_A MACRO
  372. mov CMP0MX, #23h ; Set comparator multiplexer to phase A
  373. ENDM
  374. Set_Comp_Phase_B MACRO
  375. mov CMP0MX, #03h ; Set comparator multiplexer to phase B
  376. ENDM
  377. Set_Comp_Phase_C MACRO
  378. mov CMP0MX, #13h ; Set comparator multiplexer to phase C
  379. ENDM
  380. Read_Comp_Out MACRO
  381. mov A, CMP0CN0 ; Read comparator output
  382. ENDM
  383. ;*********************
  384. ; PORT 2 definitions *
  385. ;*********************
  386. DebugPin EQU 0 ;o
  387. P2_PUSHPULL EQU (1 SHL DebugPin)
  388. ;**********************
  389. ; MCU specific macros *
  390. ;**********************
  391. Interrupt_Table_Definition MACRO
  392. CSEG AT 0 ; Code segment start
  393. jmp reset
  394. CSEG AT 03h ; Int0 interrupt
  395. jmp int0_int
  396. IF MCU_48MHZ == 1
  397. CSEG AT 0Bh ; Timer0 overflow interrupt
  398. jmp t0_int
  399. ENDIF
  400. CSEG AT 2Bh ; Timer2 overflow interrupt
  401. jmp t2_int
  402. CSEG AT 5Bh ; Pca interrupt
  403. jmp pca_int
  404. CSEG AT 73h ; Timer3 overflow/compare interrupt
  405. jmp t3_int
  406. ENDM
  407. Initialize_Xbar MACRO
  408. mov XBR2, #40h ; Xbar enabled
  409. mov XBR1, #02h ; CEX0 and CEX1 routed to pins
  410. ENDM
  411. Initialize_Adc MACRO
  412. mov REF0CN, #2Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  413. IF MCU_48MHZ == 0
  414. mov ADC0CF, #58h ; ADC clock 2MHz
  415. ELSE
  416. mov ADC0CF, #0C0h ; ADC clock 2MHz
  417. ENDIF
  418. mov ADC0MX, #10h ; Select temp sensor input
  419. mov ADC0CN0, #80h ; ADC enabled
  420. mov ADC0CN1, #01h ; Common mode buffer enabled
  421. ENDM
  422. Start_Adc MACRO
  423. mov ADC0CN0, #90h ; ADC start
  424. ENDM
  425. Get_Adc_Status MACRO
  426. mov A, ADC0CN0
  427. ENDM
  428. Read_Adc_Result MACRO
  429. mov Temp1, ADC0L
  430. mov Temp2, ADC0H
  431. ENDM
  432. Stop_Adc MACRO
  433. ENDM
  434. Set_RPM_Out MACRO
  435. ENDM
  436. Clear_RPM_Out MACRO
  437. ENDM
  438. Set_MCU_Clk_24MHz MACRO
  439. mov CLKSEL, #13h ; Set clock to 24MHz
  440. mov SFRPAGE, #10h
  441. mov PFE0CN, #00h ; Set flash timing for 24MHz
  442. mov SFRPAGE, #00h
  443. mov Clock_Set_At_48MHz, #0
  444. ENDM
  445. Set_MCU_Clk_48MHz MACRO
  446. mov SFRPAGE, #10h
  447. mov PFE0CN, #30h ; Set flash timing for 48MHz
  448. mov SFRPAGE, #00h
  449. mov CLKSEL, #03h ; Set clock to 48MHz
  450. mov Clock_Set_At_48MHz, #1
  451. ENDM
  452. Set_LED_0 MACRO
  453. ENDM
  454. Clear_LED_0 MACRO
  455. ENDM
  456. Set_LED_1 MACRO
  457. ENDM
  458. Clear_LED_1 MACRO
  459. ENDM
  460. Set_LED_2 MACRO
  461. ENDM
  462. Clear_LED_2 MACRO
  463. ENDM
  464. Set_LED_3 MACRO
  465. ENDM
  466. Clear_LED_3 MACRO
  467. ENDM