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371 lines
7.7 KiB
371 lines
7.7 KiB
; BLHeli bootloader for SiLabs MCUs. Based upon AVRootloader (copyright HR)
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XTAL EQU 25000000
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BOOT_START EQU 1C00h ; Bootloader segment address
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BOOT_DELAY EQU XTAL/4 ; About 250ms (don't set to fast to avoid connection problems)
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BOOT_BAUDRATE EQU 19200 ; Only used if no baudrate detection activated, XTAL is than important
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BOOT_VERSION EQU 6 ; Version 6 (must be not changed)
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BOOT_PAGES EQU 1 ; Number of flash segments for bootloader
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UART_LOOP EQU 26 ; Depends upon timing of putc, getc
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BAUDTIME EQU ((XTAL/BOOT_BAUDRATE)/3)-UART_LOOP
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SUCCESS EQU 030h
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ERRORVERIFY EQU 0C0h
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ERRORCOMMAND EQU 0C1h
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ERRORCRC EQU 0C2h
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ERRORPROG EQU 0C5h
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POLYNOM EQU 0A001h ; CRC Polynom
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Xl EQU R0 ; Temporary X
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Xh EQU R1
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Paral EQU R2 ; Params for UART
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Parah EQU R3
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Cmdl EQU R4 ; Commands
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Cmdh EQU R5
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Cntl EQU R6 ; Baudtime
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Cnth EQU R7
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DSEG AT 20h
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Bit_Reg: DS 1 ; Bit storage register
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Byte_Reg: DS 1 ; Byte storage register
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Crcl: DS 1 ; CRC 16Bit
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Crch: DS 1
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Baudl: DS 1 ; Baudtime
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Baudh: DS 1
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Bit_Cnt: DS 1 ; Counter in UART loops
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Byte_Cntl: DS 1 ; Generic counter
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Byte_Cnth: DS 1
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CSEG AT BOOT_START ; Bootloader start
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init:clr IE_EA
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; Select register bank 0 for main program routines
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clr PSW.3 ; Select register bank 0 for main program routines
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; Disable the WDT.
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mov WDTCN, #0DEh ; Disable watchdog
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mov WDTCN, #0ADh
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; Initialize stack
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mov SP, #0c0h ; Stack = 64 upper bytes of RAM
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; Initialize clock
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mov CLKSEL, #00h ; Set clock divider to 1
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; Initialize VDD monitor
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orl VDM0CN, #080h ; Enable the VDD monitor
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mov Baudl, #38h ; Wait 100us
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mov Baudh, #03h
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acall waitf
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mov RSTSRC, #02h ; Set VDD monitor as a reset source (PORSF)
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; Initialize ports
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orl RTX_MDIN, #(1 SHL RTX_PIN) ; Set digital
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anl RTX_MDOUT, #NOT(1 SHL RTX_PIN) ; Disable pushpull
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setb RTX_PORT.RTX_PIN ; Set data high
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mov RTX_SKIP, #0FFh
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mov XBR2, #40h; ; Enable crossbar
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; Set number of connect attempts before exiting bootloader
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mov Cmdh, #250
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; Identifier scanning
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abd: mov Xl, #(low(BOOT_DELAY / 6)+1)
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mov Xh, #(high(BOOT_DELAY / 6)+1)
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mov Cmdl, #(high((BOOT_DELAY / 6) SHR 8)+1)
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mov Crcl, #0
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mov Crch, #0
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mov DPTR, #BOOT_SIGN
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mov Parah, #(BOOT_MSG - BOOT_SIGN)
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mov Baudl, #low(BAUDTIME)
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mov Baudh, #high(BAUDTIME)
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wait_for_low:
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jnb RTX_PORT.RTX_PIN, ($+5)
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ajmp wait_for_low
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; Identifier (BOOT_SIGN) scanning with timeout and checksum
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id1: jb RTX_PORT.RTX_PIN, id3 ; Look for high
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djnz Xl, id1 ; Subtract 1 from X (BOOT_DELAY)
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djnz Xh, id1
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djnz Cmdl, id1
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ajmp exit
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id3: jnb RTX_PORT.RTX_PIN, id4 ; Look for low
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djnz Xl, id3 ; Subtract 1 from X (BOOT_DELAY)
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djnz Xh, id3
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djnz Cmdl, id3
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ajmp exit
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id4: acall getx ; Read character
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clr A
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movc A, @A+DPTR ; Load BOOT_SIGN character
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inc DPTR
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clr C
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subb A, Paral ; Compare with read character
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jz id5
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djnz Cmdh, abd ; Retry if not last connect attempt
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ajmp exit
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id5:
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djnz Parah, id1
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acall getw ; Read CRC
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jz ($+4) ; Check CRC
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ajmp abd
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; Send info about chip/bootloader (BOOT_MSG + BOOT_INFO)
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mov Parah, #((BOOT_INFO - BOOT_MSG) + 4)
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in1: clr A
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movc A, @A+DPTR ; Load character
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mov Paral, A
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inc DPTR
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acall putc
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djnz Parah, in1
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; Main commandloop
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; 0=Run/restart
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; 1=Program flash, 2=Erase flash, 3=Read flash
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; 0xFF=Set address, 0xFE=Set buffer, 0xFD=Keep alive
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main:mov Paral, #SUCCESS
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mai1:acall putc
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mov Crcl, #0 ; Reset CRC
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mov Crch, #0
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acall getw ; Get command
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mov A, Paral
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mov Cmdl, A
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mov A, Parah
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mov Cmdh, A
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clr C
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mov A, Cmdh
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subb A, #0FEh
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jc mai2 ; Jump if not set address or set buffer
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acall getw ; Address or number of bytes
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mov Byte_Cntl, Paral ; Store number of bytes for set buffer
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mov Byte_Cnth, Parah
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mov A, Cmdh
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jnb ACC.0, mai2 ; Jump if set buffer
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mov DPL, Paral ; Store flash address (for set address)
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mov DPH, Parah
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mai2:acall getw ; Get CRC
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mov Paral, #ERRORCRC
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jnz mai1
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clr C
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mov A, Cmdh
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subb A, #0FEh
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jz setbuf ; If command is set buffer, receive data
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jnc main
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cjne Cmdh, #0, mai4 ; Jump if command != 0 (and not set buffer)
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; Run application/restart bootloader
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mov A, Cmdl
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jz rst
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exit:mov Bit_Access, #0 ; Clear variable used by flash lock detect
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mov Bit_Access_Int, #0FFh ; Set variable to indicate that program execution came from bootloader
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ljmp 0000h
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rst: ajmp init
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; Set buffer
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setbuf:mov Xl, Byte_Cntl ; Set number of bytes
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mov Xh, Byte_Cnth
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inc Xl
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inc Xh
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set4:djnz Xl, set5
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djnz Xh, set5
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ajmp set6
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set5:acall getc ; Receive data
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mov A, Paral
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movx @Xl, A ; Store data in XRAM
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ajmp set4
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set6:inc Cmdh
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ajmp mai2
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mai4:clr C
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mov A, Cmdh
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subb A, #3
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jnc mai5 ; Jump if command >= 3
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; Program/erase
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mov A, Cmdh
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mov C, ACC.0
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mov Bit_Reg.0, C
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mov Paral, #ERRORPROG
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clr C
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mov A, DPL
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subb A, #low(BOOT_START)
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mov A, DPH
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subb A, #high(BOOT_START)
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jnc mai1 ; Jump if in bootloader segment
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jb Bit_Reg.0, pro3 ; Jump if program command
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; Erase flash
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orl PSCTL, #02h ; Set the PSEE bit
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orl PSCTL, #01h ; Set the PSWE bit
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mov FLKEY, #0A5h ; First key code
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mov FLKEY, #0F1h ; Second key code
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movx @DPTR, A
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jnb Bit_Reg.0, pro6 ; Jump if erase command
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; Program flash
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pro3:mov Xl, Byte_Cntl ; Set number of bytes
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mov Xh, Byte_Cnth
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inc Xl
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inc Xh
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orl PSCTL, #01h ; Set the PSWE bit
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anl PSCTL, #0FDh ; Clear the PSEE bit
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pro4:djnz Xl, pro5
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djnz Xh, pro5
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ajmp pro6
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pro5:
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movx A, @Xl ; Read from XRAM
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mov FLKEY, #0A5h ; First key code
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mov FLKEY, #0F1h ; Second key code
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movx @DPTR, A ; Write to flash
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inc DPTR ; Increment flash address
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ajmp pro4
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pro6:anl PSCTL, #0FCh ; Clear the PSEE and PSWE bits
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ajmp main ; Successfully done erase or program
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; Read flash
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mai5:mov Paral, #ERRORCOMMAND ; Illegal command
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cjne Cmdh, #3, mai6 ; Jump if not read flash command
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rd1: clr A
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movc A, @A+DPTR ; Read from flash
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inc DPTR ; Increment flash address
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mov Paral, A
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acall putp
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djnz Cmdl, rd1 ; Decrement bytes to read
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acall putw ; CRC
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ajmp main
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mai6:ajmp mai1
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; Send char with crc
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putw:mov Paral, Crcl
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mov Parah, Crch
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acall putc
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mov A, Parah
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mov Paral, A
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putp:mov A, Paral
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xrl Crcl, A
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mov Bit_Cnt, #8
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put1:clr C
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mov A, Crch
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rrc A
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mov Crch, A
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mov A, Crcl
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rrc A
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mov Crcl, A
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jnc put2
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xrl Crch, #high(POLYNOM)
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xrl Crcl, #low(POLYNOM)
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put2:djnz Bit_Cnt, put1
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; Send char
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putc:acall waitf
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acall waitf
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mov Bit_Cnt, #10
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mov A, Paral
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cpl A
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put3:jb Bit_Reg.1, ($+5)
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setb RTX_PORT.RTX_PIN ; Set pin high
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jnb Bit_Reg.1, ($+5)
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clr RTX_PORT.RTX_PIN ; Set pin low
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acall waitf
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clr C
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rrc A
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jc put4
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clr Bit_Reg.1
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put4:djnz Bit_Cnt, put3
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ret
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; Receive char/word
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getw:acall getc
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mov A, Paral
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mov Parah, A
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getc:jb RTX_PORT.RTX_PIN, ($+5) ; Wait for high
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ajmp getc
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get1:jnb RTX_PORT.RTX_PIN, ($+5) ; Wait for low
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ajmp get1
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getx:mov Bit_Cnt, #8
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mov Cntl, Baudl
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mov Cnth, Baudh
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clr C
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mov A, Cnth ; Wait half a baud
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rrc A
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mov Cnth, A
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mov A, Cntl
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rrc A
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mov Cntl, A
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acall waith
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get2:acall waitf ; Wait one baud
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clr C
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mov A, Paral
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rrc A
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jnb RTX_PORT.RTX_PIN, ($+5)
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orl A, #080h
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mov Paral, A
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jnb ACC.7, ($+6)
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xrl Crcl, #low(POLYNOM)
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clr C
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mov A, Crch
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rrc A
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mov Crch, A
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mov A, Crcl
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rrc A
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mov Crcl, A
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jnc get3
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xrl Crch, #high(POLYNOM)
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xrl Crcl, #low(POLYNOM)
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get3:djnz Bit_Cnt, get2
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mov A, Crcl
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xrl A, Crch
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xrl A, Crch
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mov Crcl, A
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ret
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; UART delays
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waitf:mov Cntl, Baudl
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mov Cnth, Baudh
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waith:inc Cntl
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inc Cnth
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wait1:djnz Cntl, wait1
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djnz Cnth, wait1
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setb Bit_Reg.1
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ret
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BOOT_SIGN: DB "BLHeli"
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BOOT_MSG: DB "471c" ; Interface-MCU_BootlaoderRevision
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BOOT_INFO: DB SIGNATURE_001, SIGNATURE_002, BOOT_VERSION, BOOT_PAGES
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