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226 lines
15 KiB
226 lines
15 KiB
;---------------------------------------------------------------------------
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;
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;
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;
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;
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; FILE NAME : C8051F310.INC
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; TARGET MCUs : C8051F310, 'F311
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; DESCRIPTION : Register/bit definitions for the C8051F31x product family.
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;
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; REVISION 1.3
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; -- added ESPI0 and PSPI0
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; REVISION 1.2
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; -- added VDM0CN (0xff)
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;
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; REVISION 1.1
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; -- changed TARGET MCUs to 'F310, 'F311
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; -- SPICFG --> SPI0CFG
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; -- SPICKR --> SPI0CKR
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; -- SPIDAT --> SPI0DAT
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; -- removed CLKMUL (0xb9)
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; -- AMUX0N --> AMX0N
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; -- AMUX0P --> AMX0P
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;
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;---------------------------------------------------------------------------
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; BYTE Registers
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P0 DATA 080H ; PORT 0
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SP DATA 081H ; STACK POINTER
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DPL DATA 082H ; DATA POINTER - LOW BYTE
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DPH DATA 083H ; DATA POINTER - HIGH BYTE
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PCON DATA 087H ; POWER CONTROL
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TCON DATA 088H ; TIMER CONTROL
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TMOD DATA 089H ; TIMER MODE
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TL0 DATA 08AH ; TIMER 0 - LOW BYTE
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TL1 DATA 08BH ; TIMER 1 - LOW BYTE
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TH0 DATA 08CH ; TIMER 0 - HIGH BYTE
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TH1 DATA 08DH ; TIMER 1 - HIGH BYTE
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CKCON DATA 08EH ; CLOCK CONTROL
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PSCTL DATA 08FH ; PROGRAM STORE R/W CONTROL
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P1 DATA 090H ; PORT 1
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TMR3CN DATA 091H ; TIMER 3 CONTROL
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TMR3RLL DATA 092H ; TIMER 3 RELOAD LOW
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TMR3RLH DATA 093H ; TIMER 3 RELOAD HIGH
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TMR3L DATA 094H ; TIMER 3 LOW BYTE
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TMR3H DATA 095H ; TIMER 3 HIGH BYTE
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SCON0 DATA 098H ; SERIAL PORT 0 CONTROL
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SBUF0 DATA 099H ; SERIAL PORT 0 BUFFER
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CPT1CN DATA 09AH ; COMPARATOR 1 CONTROL
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CPT0CN DATA 09BH ; COMPARATOR 0 CONTROL
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CPT1MD DATA 09CH ; COMPARATOR 1 MODE
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CPT0MD DATA 09DH ; COMPARATOR 0 MODE
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CPT1MX DATA 09EH ; COMPARATOR 1 MUX
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CPT0MX DATA 09FH ; COMPARATOR 0 MUX
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P2 DATA 0A0H ; PORT 2
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SPI0CFG DATA 0A1H ; SPI0 CONFIGURATION
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SPI0CKR DATA 0A2H ; SPI0 CLOCK CONFIGURATION
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SPI0DAT DATA 0A3H ; SPI0 DATA
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P0MDOUT DATA 0A4H ; PORT 0 OUTPUT MODE
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P1MDOUT DATA 0A5H ; PORT 1 OUTPUT MODE
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P2MDOUT DATA 0A6H ; PORT 2 OUTPUT MODE
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P3MDOUT DATA 0A7H ; PORT 3 OUTPUT MODE
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IE DATA 0A8H ; INTERRUPT ENABLE
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CLKSEL DATA 0A9H ; CLOCK SOURCE SELECT
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EMI0CN DATA 0AAH ; EXTERNAL MEMORY INTERFACE CONTROL
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P3 DATA 0B0H ; PORT 3
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OSCXCN DATA 0B1H ; EXTERNAL OSCILLATOR CONTROL
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OSCICN DATA 0B2H ; INTERNAL OSCILLATOR CONTROL
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OSCICL DATA 0B3H ; INTERNAL OSCILLATOR CALIBRATION
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FLACL DATA 0B5H ; FLASH ACCESS LIMIT
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FLSCL DATA 0B6H ; FLASH SCALE
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FLKEY DATA 0B7H ; FLASH LOCK & KEY
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IP DATA 0B8H ; INTERRUPT PRIORITY
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AMX0N DATA 0BAH ; ADC0 MUX NEGATIVE CHANNEL SELECTION
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AMX0P DATA 0BBH ; ADC0 MUX POSITIVE CHANNEL SELECTION
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ADC0CF DATA 0BCH ; ADC0 CONFIGURATION
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ADC0L DATA 0BDH ; ADC0 DATA LOW
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ADC0H DATA 0BEH ; ADC0 DATA HIGH
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SMB0CN DATA 0C0H ; SMBUS CONTROL
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SMB0CF DATA 0C1H ; SMBUS CONFIGURATION
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SMB0DAT DATA 0C2H ; SMBUS DATA
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ADC0GTL DATA 0C3H ; ADC0 GREATER-THAN LOW
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ADC0GTH DATA 0C4H ; ADC0 GREATER-THAN HIGH
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ADC0LTL DATA 0C5H ; ADC0 LESS-THAN LOW
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ADC0LTH DATA 0C6H ; ADC0 LESS-THAN HIGH
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TMR2CN DATA 0C8H ; TIMER 2 CONTROL
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TMR2RLL DATA 0CAH ; TIMER 2 RELOAD LOW
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TMR2RLH DATA 0CBH ; TIMER 2 RELOAD HIGH
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TMR2L DATA 0CCH ; TIMER 2 LOW BYTE
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TMR2H DATA 0CDH ; TIMER 2 HIGH BYTE
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PSW DATA 0D0H ; PROGRAM STATUS WORD
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REF0CN DATA 0D1H ; VOLTAGE REFERENCE 0 CONTROL
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P0SKIP DATA 0D4H ; PORT 0 CROSSBAR SKIP
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P1SKIP DATA 0D5H ; PORT 1 CROSSBAR SKIP
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P2SKIP DATA 0D6H ; PORT 2 CROSSBAR SKIP
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PCA0CN DATA 0D8H ; PCA0 CONTROL
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PCA0MD DATA 0D9H ; PCA0 MODE
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PCA0CPM0 DATA 0DAH ; PCA0 MODULE 0 MODE
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PCA0CPM1 DATA 0DBH ; PCA0 MODULE 1 MODE
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PCA0CPM2 DATA 0DCH ; PCA0 MODULE 2 MODE
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PCA0CPM3 DATA 0DDH ; PCA0 MODULE 3 MODE
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PCA0CPM4 DATA 0DEH ; PCA0 MODULE 4 MODE
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ACC DATA 0E0H ; ACCUMULATOR
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XBR0 DATA 0E1H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 0
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XBR1 DATA 0E2H ; DIGITAL CROSSBAR CONFIGURATION REGISTER 1
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IT01CF DATA 0E4H ; INT0/INT1 CONFIGURATION
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EIE1 DATA 0E6H ; EXTERNAL INTERRUPT ENABLE 1
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ADC0CN DATA 0E8H ; ADC 0 CONTROL
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PCA0CPL1 DATA 0E9H ; PCA0 MODULE 1 CAPTURE/COMPARE REGISTER LOW BYTE
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PCA0CPH1 DATA 0EAH ; PCA0 MODULE 1 CAPTURE/COMPARE REGISTER HIGH BYTE
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PCA0CPL2 DATA 0EBH ; PCA0 MODULE 2 CAPTURE/COMPARE REGISTER LOW BYTE
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PCA0CPH2 DATA 0ECH ; PCA0 MODULE 2 CAPTURE/COMPARE REGISTER HIGH BYTE
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PCA0CPL3 DATA 0EDH ; PCA0 MODULE 3 CAPTURE/COMPARE REGISTER LOW BYTE
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PCA0CPH3 DATA 0EEH ; PCA0 MODULE 3 CAPTURE/COMPARE REGISTER HIGH BYTE
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RSTSRC DATA 0EFH ; RESET SOURCE
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B DATA 0F0H ; B REGISTER
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P0MDIN DATA 0F1H ; PORT 0 INPUT MODE REGISTER
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P1MDIN DATA 0F2H ; PORT 1 INPUT MODE REGISTER
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P2MDIN DATA 0F3H ; PORT 2 INPUT MODE REGISTER
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P3MDIN DATA 0F4H ; PORT 3 INPUT MODE REGISTER
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EIP1 DATA 0F6H ; EXTERNAL INTERRUPT PRIORITY 1
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SPI0CN DATA 0F8H ; SPI0 CONTROL
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PCA0L DATA 0F9H ; PCA0 COUNTER REGISTER LOW BYTE
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PCA0H DATA 0FAH ; PCA0 COUNTER REGISTER HIGH BYTE
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PCA0CPL0 DATA 0FBH ; PCA MODULE 0 CAPTURE/COMPARE REGISTER LOW BYTE
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PCA0CPH0 DATA 0FCH ; PCA MODULE 0 CAPTURE/COMPARE REGISTER HIGH BYTE
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PCA0CPL4 DATA 0FDH ; PCA MODULE 4 CAPTURE/COMPARE REGISTER LOW BYTE
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PCA0CPH4 DATA 0FEH ; PCA MODULE 4 CAPTURE/COMPARE REGISTER HIGH BYTE
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VDM0CN DATA 0FFH ; VDD MONITOR CONTROL
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;------------------------------------------------------------------------------
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;BIT DEFINITIONS
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;
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; TCON 88H
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IT0 BIT TCON.0 ; EXT. INTERRUPT 0 TYPE
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IE0 BIT TCON.1 ; EXT. INTERRUPT 0 EDGE FLAG
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IT1 BIT TCON.2 ; EXT. INTERRUPT 1 TYPE
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IE1 BIT TCON.3 ; EXT. INTERRUPT 1 EDGE FLAG
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TR0 BIT TCON.4 ; TIMER 0 ON/OFF CONTROL
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TF0 BIT TCON.5 ; TIMER 0 OVERFLOW FLAG
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TR1 BIT TCON.6 ; TIMER 1 ON/OFF CONTROL
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TF1 BIT TCON.7 ; TIMER 1 OVERFLOW FLAG
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; SCON0 0x98
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RI0 BIT SCON0.0 ; RECEIVE INTERRUPT FLAG
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TI0 BIT SCON0.1 ; TRANSMIT INTERRUPT FLAG
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RB80 BIT SCON0.2 ; RECEIVE BIT 8
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TB80 BIT SCON0.3 ; TRANSMIT BIT 8
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REN0 BIT SCON0.4 ; RECEIVE ENABLE
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MCE0 BIT SCON0.5 ; MULTIPROCESSOR COMMUNICATION ENABLE
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S0MODE BIT SCON0.7 ; SERIAL MODE CONTROL BIT 0
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; IE 0xA8
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EX0 BIT IE.0 ; EXTERNAL INTERRUPT 0 ENABLE
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ET0 BIT IE.1 ; TIMER 0 INTERRUPT ENABLE
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EX1 BIT IE.2 ; EXTERNAL INTERRUPT 1 ENABLE
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ET1 BIT IE.3 ; TIMER 1 INTERRUPT ENABLE
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ES0 BIT IE.4 ; UART0 INTERRUPT ENABLE
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ET2 BIT IE.5 ; TIMER 2 INTERRUPT ENABLE
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ESPI0 BIT IE.6 ; SPI0 INTERRUPT ENABLE
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EA BIT IE.7 ; GLOBAL INTERRUPT ENABLE
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; IP 0xB8
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PX0 BIT IP.0 ; EXTERNAL INTERRUPT 0 PRIORITY
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PT0 BIT IP.1 ; TIMER 0 PRIORITY
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PX1 BIT IP.2 ; EXTERNAL INTERRUPT 1 PRIORITY
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PT1 BIT IP.3 ; TIMER 1 PRIORITY
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PS0 BIT IP.4 ; UART0 PRIORITY
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PT2 BIT IP.5 ; TIMER 2 PRIORITY
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PSPI0 BIT IP.6 ; SPI0 INTERRUPT PRIORITY
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; SMB0CN 0xC0
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SI BIT SMB0CN.0 ; SMBUS0 INTERRUPT FLAG
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ACK BIT SMB0CN.1 ; ACKNOWLEDGE FLAG
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ARBLOST BIT SMB0CN.2 ; ARBITRATION LOST INDICATOR
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ACKRQ BIT SMB0CN.3 ; ACKNOWLEDGE REQUEST
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STO BIT SMB0CN.4 ; STOP FLAG
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STA BIT SMB0CN.5 ; START FLAG
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TXMODE BIT SMB0CN.6 ; TRANSMIT MODE INDICATOR
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MASTER BIT SMB0CN.7 ; MASTER/SLAVE INDICATOR
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; TMR2CN 0xC8
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T2XCLK BIT TMR2CN.0 ; TIMER 2 EXTERNAL CLOCK SELECT
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TR2 BIT TMR2CN.2 ; TIMER 2 ON/OFF CONTROL
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T2SPLIT BIT TMR2CN.3 ; TIMER 2 SPLIT MODE ENABLE
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TF2LEN BIT TMR2CN.5 ; TIMER 2 LOW BYTE INTERRUPT ENABLE
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TF2L BIT TMR2CN.6 ; TIMER 2 LOW BYTE OVERFLOW FLAG
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TF2H BIT TMR2CN.7 ; TIMER 2 HIGH BYTE OVERFLOW FLAG
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; PSW 0xD0
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P BIT PSW.0 ; ACCUMULATOR PARITY FLAG
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F1 BIT PSW.1 ; USER FLAG 1
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OV BIT PSW.2 ; OVERFLOW FLAG
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RS0 BIT PSW.3 ; REGISTER BANK SELECT 0
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RS1 BIT PSW.4 ; REGISTER BANK SELECT 1
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F0 BIT PSW.5 ; USER FLAG 0
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AC BIT PSW.6 ; AUXILIARY CARRY FLAG
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CY BIT PSW.7 ; CARRY FLAG
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; PCA0CN 0xD8H
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CCF0 BIT PCA0CN.0 ; PCA0 MODULE 0 CAPTURE/COMPARE FLAG
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CCF1 BIT PCA0CN.1 ; PCA0 MODULE 1 CAPTURE/COMPARE FLAG
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CCF2 BIT PCA0CN.2 ; PCA0 MODULE 2 CAPTURE/COMPARE FLAG
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CCF3 BIT PCA0CN.3 ; PCA0 MODULE 3 CAPTURE/COMPARE FLAG
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CCF4 BIT PCA0CN.4 ; PCA0 MODULE 4 CAPTURE/COMPARE FLAG
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CR BIT PCA0CN.6 ; PCA0 COUNTER RUN CONTROL
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CF BIT PCA0CN.7 ; PCA0 COUNTER OVERFLOW FLAG
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; ADC0CN 0xE8H
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AD0CM0 BIT ADC0CN.0 ; ADC0 CONVERSION MODE SELECT 0
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AD0CM1 BIT ADC0CN.1 ; ADC0 CONVERSION MODE SELECT 1
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AD0CM2 BIT ADC0CN.2 ; ADC0 CONVERSION MODE SELECT 2
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AD0WINT BIT ADC0CN.3 ; ADC0 WINDOW COMPARE INTERRUPT FLAG
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AD0BUSY BIT ADC0CN.4 ; ADC0 BUSY FLAG
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AD0INT BIT ADC0CN.5 ; ADC0 CONVERISION COMPLETE INTERRUPT FLAG
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AD0TM BIT ADC0CN.6 ; ADC0 TRACK MODE
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AD0EN BIT ADC0CN.7 ; ADC0 ENABLE
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; SPI0CN 0xF8H
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SPIF BIT SPI0CN.7 ; SPI 0 INTERRUPT FLAG
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WCOL BIT SPI0CN.6 ; SPI 0 WRITE COLLISION FLAG
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MODF BIT SPI0CN.5 ; SPI 0 MODE FAULT FLAG
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RXOVRN BIT SPI0CN.4 ; SPI 0 RX OVERRUN FLAG
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NSSMD1 BIT SPI0CN.3 ; SPI 0 SLAVE SELECT MODE 1
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NSSMD0 BIT SPI0CN.2 ; SPI 0 SLAVE SELECT MODE 0
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TXBMT BIT SPI0CN.1 ; SPI 0 TRANSMIT BUFFER EMPTY
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SPIEN BIT SPI0CN.0 ; SPI 0 SPI ENABLE
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