You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

259 lines
14 KiB

9 years ago
  1. ;------------------------------------------------------------------------------
  2. ; C8051F410.INC
  3. ;------------------------------------------------------------------------------
  4. ; Copyright 2005 Silicon Laboratories, Inc.
  5. ; http://www.silabs.com
  6. ;
  7. ; Program Description:
  8. ;
  9. ; Register/bit definitions for the C8051F41x family.
  10. ;
  11. ;
  12. ; FID: 41X000004
  13. ; Target: C8051F410, F411, F412, F413
  14. ; Tool chain: Keil
  15. ; Command Line: None
  16. ;
  17. ;
  18. ; Release 1.0
  19. ; -Initial Revision (GP, PKC)
  20. ; -26 JAN 2006
  21. ;
  22. ;------------------------------------------------------------------------------
  23. ; Byte Registers
  24. ;------------------------------------------------------------------------------
  25. P0 DATA 080H ; Port 0 latch
  26. SP DATA 081H ; Stack pointer
  27. DPL DATA 082H ; Data pointer low
  28. DPH DATA 083H ; Data pointer high
  29. CRC0CN DATA 084H ; CRC0 control
  30. CRC0IN DATA 085H ; CRC0 input data
  31. CRC0DAT DATA 086H ; CRC0 output data
  32. PCON DATA 087H ; Power control
  33. TCON DATA 088H ; Timer/counter control
  34. TMOD DATA 089H ; Timer/counter mode
  35. TL0 DATA 08AH ; Timer/counter 0 low
  36. TL1 DATA 08BH ; Timer/counter 1 low
  37. TH0 DATA 08CH ; Timer/counter 0 high
  38. TH1 DATA 08DH ; Timer/counter 1 high
  39. CKCON DATA 08EH ; Clock control
  40. PSCTL DATA 08FH ; Program store R/W control
  41. P1 DATA 090H ; Port 1 latch
  42. TMR3CN DATA 091H ; Timer/counter 3 control
  43. TMR3RLL DATA 092H ; Timer/counter 3 reload low
  44. TMR3RLH DATA 093H ; Timer/counter 3 reload high
  45. TMR3L DATA 094H ; Timer/counter 3 low
  46. TMR3H DATA 095H ; Timer/counter 3 high
  47. IDA0L DATA 096H ; Current mode DAC0 low
  48. IDA0H DATA 097H ; Current mode DAC0 high
  49. SCON0 DATA 098H ; UART0 control
  50. SBUF0 DATA 099H ; UART0 data buffer
  51. CPT1CN DATA 09AH ; Comparator1 control
  52. CPT0CN DATA 09BH ; Comparator0 control
  53. CPT1MD DATA 09CH ; Comparator1 mode selection
  54. CPT0MD DATA 09DH ; Comparator0 mode selection
  55. CPT1MX DATA 09EH ; Comparator1 mux selection
  56. CPT0MX DATA 09FH ; Comparator0 mux selection
  57. P2 DATA 0A0H ; Port 2 latch
  58. SPI0CFG DATA 0A1H ; SPI0 configuration
  59. SPI0CKR DATA 0A2H ; SPI0 clock rate control
  60. SPI0DAT DATA 0A3H ; SPI0 data
  61. P0MDOUT DATA 0A4H ; Port 0 output mode configuration
  62. P1MDOUT DATA 0A5H ; Port 1 output mode configuration
  63. P2MDOUT DATA 0A6H ; Port 2 output mode configuration
  64. IE DATA 0A8H ; Interrupt enable
  65. CLKSEL DATA 0A9H ; Clock select
  66. EMI0CN DATA 0AAH ; External memory interface control
  67. CLKMUL DATA 0ABH ; Clock multiplier
  68. RTC0ADR DATA 0ACH ; RTC0 address
  69. RTC0DAT DATA 0ADH ; RTC0 data
  70. RTC0KEY DATA 0AEH ; RTC0 lock and key
  71. ONESHOT DATA 0AFH ; Flash oneshot timing
  72. P0ODEN DATA 0B0H ; Port0 Hi-Z overdrive mode enable
  73. OSCXCN DATA 0B1H ; External oscillator control
  74. OSCICN DATA 0B2H ; Internal oscillator control
  75. OSCICL DATA 0B3H ; Internal oscillator calibration
  76. IDA1CN DATA 0B5H ; Current mode DAC1 control
  77. FLSCL DATA 0B6H ; Flash scale
  78. FLKEY DATA 0B7H ; Flash lock and key
  79. IP DATA 0B8H ; Interrupt priority
  80. IDA0CN DATA 0B9H ; Current mode DAC0 control
  81. ADC0TK DATA 0BAH ; ADC0 tracking
  82. ADC0MX DATA 0BBH ; ADC0 mux
  83. ADC0CF DATA 0BCH ; ADC0 configuration
  84. ADC0L DATA 0BDH ; ADC0 data low
  85. ADC0H DATA 0BEH ; ADC0 data high
  86. P1MASK DATA 0BFH ; Port1 mask
  87. SMB0CN DATA 0C0H ; SMBus0 control
  88. SMB0CF DATA 0C1H ; SMBus0 configuration
  89. SMB0DAT DATA 0C2H ; SMBus0 data
  90. ADC0GTL DATA 0C3H ; ADC0 window greater than low byte
  91. ADC0GTH DATA 0C4H ; ADC0 window greater than high byte
  92. ADC0LTL DATA 0C5H ; ADC0 window less than low byte
  93. ADC0LTH DATA 0C6H ; ADC0 window less than high byte
  94. P0MASK DATA 0C7H ; Port0 mask
  95. TMR2CN DATA 0C8H ; Timer/counter 2 control
  96. REG0CN DATA 0C9H ; Voltage regulator control
  97. TMR2RLL DATA 0CAH ; Timer/counter 2 reload low
  98. TMR2RLH DATA 0CBH ; Timer/counter 2 reload high
  99. TMR2L DATA 0CCH ; Timer/counter 2 low
  100. TMR2H DATA 0CDH ; Timer/counter 2 high
  101. PCA0CPM5 DATA 0CEH ; PCA0 module 5 mode
  102. P1MAT DATA 0CFH ; Port1 match
  103. PSW DATA 0D0H ; Program status word
  104. REF0CN DATA 0D1H ; Voltage reference control
  105. PCA0CPL5 DATA 0D2H ; PCA0 module 5 low
  106. PCA0CPH5 DATA 0D3H ; PCA0 module 5 high
  107. P0SKIP DATA 0D4H ; Port 0 skip
  108. P1SKIP DATA 0D5H ; Port 1 skip
  109. P2SKIP DATA 0D6H ; Port 2 skip
  110. P0MAT DATA 0D7H ; Port 0 match
  111. PCA0CN DATA 0D8H ; PCA0 control
  112. PCA0MD DATA 0D9H ; PCA0 mode
  113. PCA0CPM0 DATA 0DAH ; PCA0 module 0 mode
  114. PCA0CPM1 DATA 0DBH ; PCA0 module 1 mode
  115. PCA0CPM2 DATA 0DCH ; PCA0 module 2 mode
  116. PCA0CPM3 DATA 0DDH ; PCA0 module 3 mode
  117. PCA0CPM4 DATA 0DEH ; PCA0 module 4 mode
  118. CRC0FLIP DATA 0DFH ; CRC0 bit flip
  119. ACC DATA 0E0H ; Accumulator
  120. XBR0 DATA 0E1H ; Port I/O crossbar control 0
  121. XBR1 DATA 0E2H ; Port I/O crossbar control 1
  122. PFE0CN DATA 0E3H ; Prefetch engine control
  123. IT01CF DATA 0E4H ; INT0/INT1 configuration
  124. EIE1 DATA 0E6H ; Extended interrupt enable 1
  125. EIE2 DATA 0E7H ; Extended interrupt enable 2
  126. ADC0CN DATA 0E8H ; ADC0 control
  127. PCA0CPL1 DATA 0E9H ; PCA0 module 1 capture low
  128. PCA0CPH1 DATA 0EAH ; PCA0 module 1 capture high
  129. PCA0CPL2 DATA 0EBH ; PCA0 module 2 capture low
  130. PCA0CPH2 DATA 0ECH ; PCA0 module 2 capture high
  131. PCA0CPL3 DATA 0EDH ; PCA0 module 3 capture low
  132. PCA0CPH3 DATA 0EEH ; PCA0 module 3 capture high
  133. RSTSRC DATA 0EFH ; Reset source configuration/status
  134. B DATA 0F0H ; B register
  135. P0MDIN DATA 0F1H ; Port 0 input mode configuration
  136. P1MDIN DATA 0F2H ; Port 1 input mode configuration
  137. P2MDIN DATA 0F3H ; Port 2 input mode configuration
  138. IDA1L DATA 0F4H ; Current mode DAC1 data low
  139. IDA1H DATA 0F5H ; Current mode DAC1 data high
  140. EIP1 DATA 0F6H ; Extended interrupt priority 1
  141. EIP2 DATA 0F7H ; Extended interrupt priority 2
  142. SPI0CN DATA 0F8H ; SPI0 control
  143. PCA0L DATA 0F9H ; PCA0 counter low
  144. PCA0H DATA 0FAH ; PCA0 counter high
  145. PCA0CPL0 DATA 0FBH ; PCA0 module 0 capture low
  146. PCA0CPH0 DATA 0FCH ; PCA0 module 0 capture high
  147. PCA0CPL4 DATA 0FDH ; PCA0 module 4 capture low
  148. PCA0CPH4 DATA 0FEH ; PCA0 module 4 capture high
  149. VDM0CN DATA 0FFH ; VDD monitor control
  150. ;------------------------------------------------------------------------------
  151. ; Bit Definitions
  152. ;------------------------------------------------------------------------------
  153. ; TCON 0x88
  154. TF1 BIT TCON.7 ; Timer 1 overflow flag
  155. TR1 BIT TCON.6 ; Timer 1 on/off control
  156. TF0 BIT TCON.5 ; Timer 0 overflow flag
  157. TR0 BIT TCON.4 ; Timer 0 on/off control
  158. IE1 BIT TCON.3 ; Ext. Interrupt 1 edge flag
  159. IT1 BIT TCON.2 ; Ext. Interrupt 1 type
  160. IE0 BIT TCON.1 ; Ext. Interrupt 0 edge flag
  161. IT0 BIT TCON.0 ; Ext. Interrupt 0 type
  162. ; SCON0 0x98
  163. S0MODE BIT SCON0.7 ; UART0 mode
  164. ; Bit 6 Unused
  165. MCE0 BIT SCON0.5 ; UART0 MCE
  166. REN0 BIT SCON0.4 ; UART0 RX enable
  167. TB80 BIT SCON0.3 ; UART0 TX bit 8
  168. RB80 BIT SCON0.2 ; UART0 RX bit 8
  169. TI0 BIT SCON0.1 ; UART0 TX interrupt flag
  170. RI0 BIT SCON0.0 ; UART0 RX interrupt flag
  171. ; IE 0xA8
  172. EA BIT IE.7 ; Global interrupt enable
  173. ESPI0 BIT IE.6 ; SPI0 interrupt enable
  174. ET2 BIT IE.5 ; Timer 2 interrupt enable
  175. ES0 BIT IE.4 ; UART0 interrupt enable
  176. ET1 BIT IE.3 ; Timer 1 interrupt enable
  177. EX1 BIT IE.2 ; External interrupt 1 enable
  178. ET0 BIT IE.1 ; Timer 0 interrupt enable
  179. EX0 BIT IE.0 ; External interrupt 0 enable
  180. ; IP 0xB8
  181. ; Bit 7 Unused
  182. PSPI0 BIT IP.6 ; SPI0 priority
  183. PT2 BIT IP.5 ; Timer 2 priority
  184. PS0 BIT IP.4 ; UART0 priority
  185. PT1 BIT IP.3 ; Timer 1 priority
  186. PX1 BIT IP.2 ; External interrupt 1 priority
  187. PT0 BIT IP.1 ; Timer 0 priority
  188. PX0 BIT IP.0 ; External interrupt 0 priority
  189. ; SMB0CN 0xC0
  190. MASTER BIT SMB0CN.7 ; SMBus0 master/slave
  191. TXMODE BIT SMB0CN.6 ; SMBus0 transmit mode
  192. STA BIT SMB0CN.5 ; SMBus0 start flag
  193. STO BIT SMB0CN.4 ; SMBus0 stop flag
  194. ACKRQ BIT SMB0CN.3 ; SMBus0 acknowledge request
  195. ARBLOST BIT SMB0CN.2 ; SMBus0 arbitration lost
  196. ACK BIT SMB0CN.1 ; SMBus0 acknowledge flag
  197. SI BIT SMB0CN.0 ; SMBus0 interrupt pending flag
  198. ; TMR2CN 0xC8
  199. TF2H BIT TMR2CN.7 ; Timer 2 high byte overflow flag
  200. TF2L BIT TMR2CN.6 ; Timer 2 low byte overflow flag
  201. TF2LEN BIT TMR2CN.5 ; Timer 2 low byte interrupt enable
  202. TF2CEN BIT TMR2CN.4 ; Timer 2 capture enable
  203. T2SPLIT BIT TMR2CN.3 ; Timer 2 split mode enable
  204. TR2 BIT TMR2CN.2 ; Timer 2 on/off control
  205. T2RCLK BIT TMR2CN.1 ; Timer 2 RTC capture mode select
  206. T2XCLK BIT TMR2CN.0 ; Timer 2 external clock select
  207. ; PSW 0xD0
  208. CY BIT PSW.7 ; Carry flag
  209. AC BIT PSW.6 ; Auxiliary carry flag
  210. F0 BIT PSW.5 ; User flag 0
  211. RS1 BIT PSW.4 ; Register bank select 1
  212. RS0 BIT PSW.3 ; Register bank select 0
  213. OV BIT PSW.2 ; Overflow flag
  214. F1 BIT PSW.1 ; User flag 1
  215. P BIT PSW.0 ; Accumulator parity flag
  216. ; PCA0CN 0xD8
  217. CF BIT PCA0CN.7 ; PCA0 counter overflow flag
  218. CR BIT PCA0CN.6 ; PCA0 counter run control bit
  219. CCF5 BIT PCA0CN.5 ; PCA0 module 5 interrupt flag
  220. CCF4 BIT PCA0CN.4 ; PCA0 module 4 interrupt flag
  221. CCF3 BIT PCA0CN.3 ; PCA0 module 3 interrupt flag
  222. CCF2 BIT PCA0CN.2 ; PCA0 module 2 interrupt flag
  223. CCF1 BIT PCA0CN.1 ; PCA0 module 1 interrupt flag
  224. CCF0 BIT PCA0CN.0 ; PCA0 module 0 interrupt flag
  225. ; ADC0CN 0xE8
  226. AD0EN BIT ADC0CN.7 ; ADC0 enable
  227. BURSTEN BIT ADC0CN.6 ; ADC0 burst mode enable
  228. AD0INT BIT ADC0CN.5 ; ADC0 conv. complete interrupt flag
  229. AD0BUSY BIT ADC0CN.4 ; ADC0 busy flag
  230. AD0WINT BIT ADC0CN.3 ; ADC0 window compare interrupt flag
  231. AD0LJST BIT ADC0CN.2 ; ADC0 left justify select
  232. AD0CM1 BIT ADC0CN.1 ; ADC0 conversion mode select 1
  233. AD0CM0 BIT ADC0CN.0 ; ADC0 conversion mode select 0
  234. ; SPI0CN 0xF8
  235. SPIF BIT SPI0CN.7 ; SPI0 interrupt flag
  236. WCOL BIT SPI0CN.6 ; SPI0 write collision flag
  237. MODF BIT SPI0CN.5 ; SPI0 mode fault flag
  238. RXOVRN BIT SPI0CN.4 ; SPI0 RX overrun flag
  239. NSSMD1 BIT SPI0CN.3 ; SPI0 slave select mode 1
  240. NSSMD0 BIT SPI0CN.2 ; SPI0 slave select mode 0
  241. TXBMT BIT SPI0CN.1 ; SPI0 TX buffer empty flag
  242. SPIEN BIT SPI0CN.0 ; SPI0 SPI0 enable
  243. ;------------------------------------------------------------------------------
  244. ; End Of File
  245. ;------------------------------------------------------------------------------