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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hardware definition file "L"
  26. ; X X RC X CC MA MB MC X X Ac Bc Cc Ap Bp Cp
  27. ;
  28. ;**** **** **** **** ****
  29. ;*********************
  30. ; Device SiLabs EFM8BB1x/2x
  31. ;*********************
  32. IF MCU_48MHZ == 0
  33. $include (SI_EFM8BB1_Defs.inc)
  34. ELSE
  35. $include (SI_EFM8BB2_Defs.inc)
  36. ENDIF
  37. ;**** **** **** **** ****
  38. ; Uses internal calibrated oscillator set to 24/48Mhz
  39. ;**** **** **** **** ****
  40. ;**** **** **** **** ****
  41. ; Constant definitions
  42. ;**** **** **** **** ****
  43. IF MCU_48MHZ == 0
  44. CSEG AT 1A40h
  45. IF FETON_DELAY == 0
  46. Eep_ESC_Layout: DB "#L_L_00# " ; ESC layout tag
  47. ELSEIF FETON_DELAY == 5
  48. Eep_ESC_Layout: DB "#L_L_05# "
  49. ELSEIF FETON_DELAY == 10
  50. Eep_ESC_Layout: DB "#L_L_10# "
  51. ELSEIF FETON_DELAY == 15
  52. Eep_ESC_Layout: DB "#L_L_15# "
  53. ELSEIF FETON_DELAY == 20
  54. Eep_ESC_Layout: DB "#L_L_20# "
  55. ELSEIF FETON_DELAY == 25
  56. Eep_ESC_Layout: DB "#L_L_25# "
  57. ELSEIF FETON_DELAY == 30
  58. Eep_ESC_Layout: DB "#L_L_30# "
  59. ELSEIF FETON_DELAY == 40
  60. Eep_ESC_Layout: DB "#L_L_40# "
  61. ELSEIF FETON_DELAY == 50
  62. Eep_ESC_Layout: DB "#L_L_50# "
  63. ELSEIF FETON_DELAY == 70
  64. Eep_ESC_Layout: DB "#L_L_70# "
  65. ELSEIF FETON_DELAY == 90
  66. Eep_ESC_Layout: DB "#L_L_90# "
  67. ENDIF
  68. CSEG AT 1A50h
  69. Eep_ESC_MCU: DB "#BLHELI$EFM8B10#" ; Project and MCU tag (16 Bytes)
  70. ELSE
  71. CSEG AT 1A40h
  72. IF FETON_DELAY == 0
  73. Eep_ESC_Layout: DB "#L_H_00# " ; ESC layout tag
  74. ELSEIF FETON_DELAY == 5
  75. Eep_ESC_Layout: DB "#L_H_05# "
  76. ELSEIF FETON_DELAY == 10
  77. Eep_ESC_Layout: DB "#L_H_10# "
  78. ELSEIF FETON_DELAY == 15
  79. Eep_ESC_Layout: DB "#L_H_15# "
  80. ELSEIF FETON_DELAY == 20
  81. Eep_ESC_Layout: DB "#L_H_20# "
  82. ELSEIF FETON_DELAY == 25
  83. Eep_ESC_Layout: DB "#L_H_25# "
  84. ELSEIF FETON_DELAY == 30
  85. Eep_ESC_Layout: DB "#L_H_30# "
  86. ELSEIF FETON_DELAY == 40
  87. Eep_ESC_Layout: DB "#L_H_40# "
  88. ELSEIF FETON_DELAY == 50
  89. Eep_ESC_Layout: DB "#L_H_50# "
  90. ELSEIF FETON_DELAY == 70
  91. Eep_ESC_Layout: DB "#L_H_70# "
  92. ELSEIF FETON_DELAY == 90
  93. Eep_ESC_Layout: DB "#L_H_90# "
  94. ENDIF
  95. CSEG AT 1A50h
  96. Eep_ESC_MCU: DB "#BLHELI$EFM8B21#" ; Project and MCU tag (16 Bytes)
  97. ENDIF
  98. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  99. TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
  100. TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC
  101. ;**** **** **** **** ****
  102. ; Bootloader definitions
  103. ;**** **** **** **** ****
  104. RTX_PORT EQU P0 ; Receive/Transmit port
  105. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  106. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  107. RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP
  108. RTX_PIN EQU 5 ; RTX pin
  109. SIGNATURE_001 EQU 0E8h ; Device signature
  110. IF MCU_48MHZ == 0
  111. SIGNATURE_002 EQU 0B1h
  112. ELSE
  113. SIGNATURE_002 EQU 0B2h
  114. ENDIF
  115. ;*********************
  116. ; PORT 0 definitions *
  117. ;*********************
  118. ; EQU 7 ;i
  119. ; EQU 6 ;i
  120. Rcp_In EQU 5 ;i
  121. ; EQU 4 ;i
  122. Comp_Com EQU 3 ;i
  123. Mux_A EQU 2 ;i
  124. Mux_B EQU 1 ;i
  125. Mux_C EQU 0 ;i
  126. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  127. P0_INIT EQU 0FFh
  128. P0_PUSHPULL EQU 0
  129. P0_SKIP EQU 0FFh
  130. Get_Rcp_Capture_Values MACRO
  131. anl TCON, #0EFh ; Disable timer0
  132. mov Temp1, TL0 ; Get timer0 values
  133. mov Temp2, TH0
  134. IF MCU_48MHZ == 1
  135. mov Temp3, Timer0_X
  136. jnb TCON_TF0, ($+4) ; Check if interrupt is pending
  137. inc Temp3 ; If it is pending, then timer has already wrapped
  138. ENDIF
  139. mov TL0, #0 ; Reset timer0
  140. mov TH0, #0
  141. IF MCU_48MHZ == 1
  142. mov Timer0_X, #0
  143. ENDIF
  144. orl TCON, #10h ; Enable timer0 again
  145. IF MCU_48MHZ == 1
  146. mov A, Clock_Set_At_48MHz
  147. jnz Get_Rcp_End
  148. clr C
  149. mov A, Temp1
  150. rlc A
  151. mov Temp1, A
  152. mov A, Temp2
  153. rlc A
  154. mov Temp2, A
  155. mov A, Temp3
  156. rlc A
  157. mov Temp3, A
  158. Get_Rcp_End:
  159. ENDIF
  160. ENDM
  161. Initialize_PCA MACRO
  162. mov PCA0CN0, #40h ; PCA enabled
  163. mov PCA0MD, #08h ; PCA clock is system clock
  164. IF FETON_DELAY == 0
  165. IF MCU_48MHZ == 0
  166. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  167. ELSE
  168. mov PCA0PWM, #83h ; PCA ARSEL set and 11bits pwm
  169. ENDIF
  170. mov PCA0CENT, #00h ; Edge aligned pwm
  171. ELSE
  172. IF MCU_48MHZ == 0
  173. mov PCA0PWM, #81h ; PCA ARSEL set and 9bits pwm
  174. ELSE
  175. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  176. ENDIF
  177. mov PCA0CENT, #03h ; Center aligned pwm
  178. ENDIF
  179. ENDM
  180. Set_Pwm_Polarity MACRO
  181. mov PCA0POL, #02h ; Damping inverted, pwm noninverted
  182. ENDM
  183. Enable_Power_Pwm_Module MACRO
  184. IF FETON_DELAY == 0
  185. mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode
  186. ELSE
  187. mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode
  188. ENDIF
  189. ENDM
  190. Enable_Damp_Pwm_Module MACRO
  191. IF FETON_DELAY == 0
  192. mov PCA0CPM1, #00h ; Disable
  193. ELSE
  194. mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode
  195. ENDIF
  196. ENDM
  197. Set_Power_Pwm_Regs MACRO
  198. IF FETON_DELAY == 0
  199. mov PCA0CPL0, Power_Pwm_Reg_L
  200. mov PCA0CPH0, Power_Pwm_Reg_H
  201. ELSE
  202. clr C
  203. mov A, Power_Pwm_Reg_H
  204. rrc A
  205. mov Temp1, A
  206. mov A, Power_Pwm_Reg_L
  207. rrc A
  208. mov PCA0CPL0, A
  209. mov PCA0CPH0, Temp1
  210. ENDIF
  211. ENDM
  212. Set_Damp_Pwm_Regs MACRO
  213. IF FETON_DELAY == 0
  214. mov PCA0CPL1, Damp_Pwm_Reg_L
  215. mov PCA0CPH1, Damp_Pwm_Reg_H
  216. ELSE
  217. clr C
  218. mov A, Damp_Pwm_Reg_H
  219. rrc A
  220. mov Temp1, A
  221. mov A, Damp_Pwm_Reg_L
  222. rrc A
  223. mov PCA0CPL1, A
  224. mov PCA0CPH1, Temp1
  225. ENDIF
  226. ENDM
  227. Clear_COVF_Interrupt MACRO
  228. anl PCA0PWM, #0DFh
  229. ENDM
  230. Clear_CCF_Interrupt MACRO
  231. anl PCA0CN0, #0FEh
  232. ENDM
  233. Enable_COVF_Interrupt MACRO
  234. orl PCA0PWM, #40h
  235. ENDM
  236. Enable_CCF_Interrupt MACRO
  237. orl PCA0CPM0,#01h
  238. ENDM
  239. Disable_COVF_Interrupt MACRO
  240. anl PCA0PWM, #0BFh
  241. ENDM
  242. Disable_CCF_Interrupt MACRO
  243. anl PCA0CPM0,#0FEh
  244. ENDM
  245. ;*********************
  246. ; PORT 1 definitions *
  247. ;*********************
  248. ; EQU 7 ;i
  249. ; EQU 6 ;i
  250. AcomFET EQU 5 ;o
  251. BcomFET EQU 4 ;o
  252. CcomFET EQU 3 ;o
  253. ApwmFET EQU 2 ;o
  254. BpwmFET EQU 1 ;o
  255. CpwmFET EQU 0 ;o
  256. P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
  257. P1_INIT EQU 00h
  258. P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)+(1 SHL CcomFET)
  259. P1_SKIP EQU 3Fh
  260. ApwmFET_on MACRO
  261. setb P1.ApwmFET
  262. IF FETON_DELAY == 0
  263. setb P1.AcomFET
  264. ENDIF
  265. ENDM
  266. ApwmFET_off MACRO
  267. IF FETON_DELAY != 0
  268. clr P1.ApwmFET
  269. ELSE
  270. clr P1.AcomFET
  271. ENDIF
  272. ENDM
  273. BpwmFET_on MACRO
  274. setb P1.BpwmFET
  275. IF FETON_DELAY == 0
  276. setb P1.BcomFET
  277. ENDIF
  278. ENDM
  279. BpwmFET_off MACRO
  280. IF FETON_DELAY != 0
  281. clr P1.BpwmFET
  282. ELSE
  283. clr P1.BcomFET
  284. ENDIF
  285. ENDM
  286. CpwmFET_on MACRO
  287. setb P1.CpwmFET
  288. IF FETON_DELAY == 0
  289. setb P1.CcomFET
  290. ENDIF
  291. ENDM
  292. CpwmFET_off MACRO
  293. IF FETON_DELAY != 0
  294. clr P1.CpwmFET
  295. ELSE
  296. clr P1.CcomFET
  297. ENDIF
  298. ENDM
  299. All_pwmFETs_Off MACRO
  300. IF FETON_DELAY != 0
  301. clr P1.ApwmFET
  302. clr P1.BpwmFET
  303. clr P1.CpwmFET
  304. ELSE
  305. clr P1.AcomFET
  306. clr P1.BcomFET
  307. clr P1.CcomFET
  308. ENDIF
  309. ENDM
  310. AcomFET_on MACRO
  311. IF FETON_DELAY == 0
  312. clr P1.ApwmFET
  313. ENDIF
  314. setb P1.AcomFET
  315. ENDM
  316. AcomFET_off MACRO
  317. clr P1.AcomFET
  318. ENDM
  319. BcomFET_on MACRO
  320. IF FETON_DELAY == 0
  321. clr P1.BpwmFET
  322. ENDIF
  323. setb P1.BcomFET
  324. ENDM
  325. BcomFET_off MACRO
  326. clr P1.BcomFET
  327. ENDM
  328. CcomFET_on MACRO
  329. IF FETON_DELAY == 0
  330. clr P1.CpwmFET
  331. ENDIF
  332. setb P1.CcomFET
  333. ENDM
  334. CcomFET_off MACRO
  335. clr P1.CcomFET
  336. ENDM
  337. All_comFETs_Off MACRO
  338. clr P1.AcomFET
  339. clr P1.BcomFET
  340. clr P1.CcomFET
  341. ENDM
  342. Set_Pwm_A MACRO
  343. IF FETON_DELAY == 0
  344. setb P1.AcomFET
  345. mov P1SKIP, #3Bh
  346. ELSE
  347. mov P1SKIP, #1Bh
  348. ENDIF
  349. ENDM
  350. Set_Pwm_B MACRO
  351. IF FETON_DELAY == 0
  352. setb P1.BcomFET
  353. mov P1SKIP, #3Dh
  354. ELSE
  355. mov P1SKIP, #2Dh
  356. ENDIF
  357. ENDM
  358. Set_Pwm_C MACRO
  359. IF FETON_DELAY == 0
  360. setb P1.CcomFET
  361. mov P1SKIP, #3Eh
  362. ELSE
  363. mov P1SKIP, #36h
  364. ENDIF
  365. ENDM
  366. Set_Pwms_Off MACRO
  367. mov P1SKIP, #7Fh
  368. ENDM
  369. Set_Comp_Phase_A MACRO
  370. mov CMP0MX, #23h ; Set comparator multiplexer to phase A
  371. ENDM
  372. Set_Comp_Phase_B MACRO
  373. mov CMP0MX, #13h ; Set comparator multiplexer to phase B
  374. ENDM
  375. Set_Comp_Phase_C MACRO
  376. mov CMP0MX, #03h ; Set comparator multiplexer to phase C
  377. ENDM
  378. Read_Comp_Out MACRO
  379. mov A, CMP0CN0 ; Read comparator output
  380. ENDM
  381. ;*********************
  382. ; PORT 2 definitions *
  383. ;*********************
  384. DebugPin EQU 0 ;o
  385. P2_PUSHPULL EQU (1 SHL DebugPin)
  386. ;**********************
  387. ; MCU specific macros *
  388. ;**********************
  389. Interrupt_Table_Definition MACRO
  390. CSEG AT 0 ; Code segment start
  391. jmp reset
  392. CSEG AT 03h ; Int0 interrupt
  393. jmp int0_int
  394. IF MCU_48MHZ == 1
  395. CSEG AT 0Bh ; Timer0 overflow interrupt
  396. jmp t0_int
  397. ENDIF
  398. CSEG AT 2Bh ; Timer2 overflow interrupt
  399. jmp t2_int
  400. CSEG AT 5Bh ; Pca interrupt
  401. jmp pca_int
  402. CSEG AT 73h ; Timer3 overflow/compare interrupt
  403. jmp t3_int
  404. ENDM
  405. Initialize_Xbar MACRO
  406. mov XBR2, #40h ; Xbar enabled
  407. mov XBR1, #02h ; CEX0 and CEX1 routed to pins
  408. ENDM
  409. Initialize_Adc MACRO
  410. mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  411. IF MCU_48MHZ == 0
  412. mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1
  413. ELSE
  414. mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1
  415. ENDIF
  416. mov ADC0MX, #10h ; Select temp sensor input
  417. mov ADC0CN0, #80h ; ADC enabled
  418. mov ADC0CN1, #01h ; Common mode buffer enabled
  419. ENDM
  420. Start_Adc MACRO
  421. mov ADC0CN0, #90h ; ADC start
  422. ENDM
  423. Read_Adc_Result MACRO
  424. mov Temp1, ADC0L
  425. mov Temp2, ADC0H
  426. ENDM
  427. Stop_Adc MACRO
  428. ENDM
  429. Set_RPM_Out MACRO
  430. ENDM
  431. Clear_RPM_Out MACRO
  432. ENDM
  433. Set_MCU_Clk_24MHz MACRO
  434. mov CLKSEL, #13h ; Set clock to 24MHz
  435. mov SFRPAGE, #10h
  436. mov PFE0CN, #00h ; Set flash timing for 24MHz
  437. mov SFRPAGE, #00h
  438. mov Clock_Set_At_48MHz, #0
  439. ENDM
  440. Set_MCU_Clk_48MHz MACRO
  441. mov SFRPAGE, #10h
  442. mov PFE0CN, #30h ; Set flash timing for 48MHz
  443. mov SFRPAGE, #00h
  444. mov CLKSEL, #03h ; Set clock to 48MHz
  445. mov Clock_Set_At_48MHz, #1
  446. ENDM
  447. Set_LED_0 MACRO
  448. ENDM
  449. Clear_LED_0 MACRO
  450. ENDM
  451. Set_LED_1 MACRO
  452. ENDM
  453. Clear_LED_1 MACRO
  454. ENDM
  455. Set_LED_2 MACRO
  456. ENDM
  457. Clear_LED_2 MACRO
  458. ENDM
  459. Set_LED_3 MACRO
  460. ENDM
  461. Clear_LED_3 MACRO
  462. ENDM