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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; YEP 7A hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device Atmega168PA
  30. ;*********************
  31. .INCLUDE "m168PAdef.inc"
  32. ;**** **** **** **** ****
  33. ; Fuses must be set to external oscillator = 16Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. .ESEG ; EEprom segment
  39. .ORG 0x40
  40. Eep_ESC_Layout: .DB "#YEP_7A# " ; ESC layout tag
  41. .ORG 0x50
  42. Eep_ESC_MCU: .DB "#BLHELI#Am168PA#" ; Project and MCU tag (16 Bytes)
  43. .EQU HIGH_BEC_VOLTAGE = 0 ; Set to 1 or more if high BEC voltage is supported
  44. .EQU DAMPED_MODE_ENABLE = 0 ; Set to 1 if fully damped mode is supported
  45. .EQU NFETON_DELAY = 65 ; Wait delay from pfets off to nfets on
  46. .EQU PFETON_DELAY = 1 ; Wait delay from nfets off to pfets on
  47. .EQU HIGH_DRIVER_PRECHG_TIME = 0 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  48. .EQU ADC_LIMIT_L = 231 ; 2k/22k divider. Power supply measurement ADC value for which motor power is limited (low byte)
  49. .EQU ADC_LIMIT_H = 0 ; 2k/22k divider. Power supply measurement ADC value for which motor power is limited (2 MSBs)
  50. .EQU TEMP_LIMIT = 0 ; No temp sensor. Temperature measurement ADC value for which main motor power is limited
  51. .EQU TEMP_LIMIT_STEP = 0 ; No temp sensor. Temperature measurement ADC value increment for which main motor power is further limited
  52. ;**** **** **** **** ****
  53. ; ESC specific defaults
  54. ;**** **** **** **** ****
  55. .EQU DEFAULT_PGM_MAIN_SPOOLUP_TIME = 7 ; Main motor spoolup time
  56. .EQU DEFAULT_PGM_MAIN_STARTUP_PWR = 11 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  57. .EQU DEFAULT_PGM_TAIL_STARTUP_PWR = 11 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  58. .EQU DEFAULT_PGM_MULTI_STARTUP_PWR = 11 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  59. .EQU DEFAULT_PGM_MAIN_STARTUP_METHOD = 2 ; 1=Stepped 2=Direct
  60. .EQU DEFAULT_PGM_TAIL_STARTUP_METHOD = 2 ; 1=Stepped 2=Direct
  61. .EQU DEFAULT_PGM_MULTI_STARTUP_METHOD = 2 ; 1=Stepped 2=Direct
  62. ;*********************
  63. ; PORT D definitions *
  64. ;*********************
  65. ;.EQU = 7 ;i
  66. ;.EQU = 6 ;i
  67. ;.EQU = 5 ;i
  68. ;.EQU = 4 ;i
  69. ;.EQU = 3 ;i
  70. .EQU Rcp_In = 2 ;i
  71. ;.EQU = 1 ;i
  72. ;.EQU = 0 ;i
  73. .equ INIT_PD = 0x00
  74. .equ DIR_PD = 0x00
  75. .MACRO Get_Rcp_Capture_Values
  76. lds @0, TCNT1L
  77. lds @1, TCNT1H
  78. .ENDMACRO
  79. .MACRO Read_Rcp_Int
  80. in @0, PIND
  81. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  82. com @0 ; Yes - invert
  83. .ENDMACRO
  84. .MACRO Get_Rcp_Int_Enable_State
  85. in @0, EIMSK ; Get int0 enable state (giving 0 is off, anything else is on)
  86. andi @0, (1<<INT0)
  87. .ENDMACRO
  88. .MACRO Rcp_Int_Enable
  89. ldi @0, (1<<INT0) ; Enable int0
  90. out EIMSK, @0
  91. .ENDMACRO
  92. .MACRO Rcp_Int_Disable
  93. ldi @0, 0 ; Disable int0
  94. out EIMSK, @0
  95. .ENDMACRO
  96. .MACRO Rcp_Int_First
  97. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  98. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  99. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  100. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  101. sts EICRA, @0
  102. .ENDMACRO
  103. .MACRO Rcp_Int_Second
  104. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  105. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  106. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  107. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  108. sts EICRA, @0
  109. .ENDMACRO
  110. .MACRO Rcp_Clear_Int_Flag
  111. clr @0
  112. sbr @0, (1<<INTF0) ; Clear ext0int flag
  113. out EIFR, @0
  114. .ENDMACRO
  115. .MACRO T0_Int_Disable
  116. lds @0, TIMSK0 ; Disable timer0 interrupts
  117. cbr @0, (1<<TOIE0)
  118. sts TIMSK0, @0
  119. .ENDMACRO
  120. .MACRO T0_Int_Enable
  121. lds @0, TIMSK0 ; Enable timer0 interrupts
  122. sbr @0, (1<<TOIE0)
  123. sts TIMSK0, @0
  124. .ENDMACRO
  125. .MACRO T1oca_Clear_Int_Flag
  126. ldi @0, (1<<OCF1A) ; Clear oc1a flag
  127. out TIFR1, @0
  128. .ENDMACRO
  129. .MACRO T1oca_Int_Disable
  130. lds @0, TIMSK1 ; Disable oc1a interrupts
  131. cbr @0, (1<<OCIE1A)
  132. sts TIMSK1, @0
  133. .ENDMACRO
  134. .MACRO T1oca_Int_Enable
  135. lds @0, TIMSK1 ; Enable oc1a interrupts
  136. sbr @0, (1<<OCIE1A)
  137. sts TIMSK1, @0
  138. .ENDMACRO
  139. ;*********************
  140. ; PORT C definitions *
  141. ;*********************
  142. ;.EQU = 7 ; i
  143. ;.EQU = 6 ; i
  144. .EQU Mux_A = 5 ; i
  145. .EQU Mux_B = 4 ; i
  146. .EQU Mux_C = 3 ; i
  147. ;.EQU = 2 ; i
  148. ;.EQU = 1 ; i
  149. .EQU Volt_Ip = 0 ; i
  150. .equ INIT_PC = 0x00
  151. .equ DIR_PC = 0x00
  152. .MACRO AnFET_on
  153. tst Current_Pwm_Limited
  154. breq PC+5
  155. sbrs Flags3, PGM_DIR_REV
  156. sbi PORTB, AnFET
  157. sbrc Flags3, PGM_DIR_REV
  158. sbi PORTB, CnFET
  159. .ENDMACRO
  160. .MACRO AnFET_off
  161. sbrs Flags3, PGM_DIR_REV
  162. cbi PORTB, AnFET
  163. sbrc Flags3, PGM_DIR_REV
  164. cbi PORTB, CnFET
  165. .ENDMACRO
  166. .MACRO BnFET_on
  167. tst Current_Pwm_Limited
  168. breq PC+2
  169. sbi PORTB, BnFET
  170. .ENDMACRO
  171. .MACRO BnFET_off
  172. cbi PORTB, BnFET
  173. .ENDMACRO
  174. .MACRO CnFET_on
  175. tst Current_Pwm_Limited
  176. breq PC+5
  177. sbrs Flags3, PGM_DIR_REV
  178. sbi PORTB, CnFET
  179. sbrc Flags3, PGM_DIR_REV
  180. sbi PORTB, AnFET
  181. .ENDMACRO
  182. .MACRO CnFET_off
  183. sbrs Flags3, PGM_DIR_REV
  184. cbi PORTB, CnFET
  185. sbrc Flags3, PGM_DIR_REV
  186. cbi PORTB, AnFET
  187. .ENDMACRO
  188. .MACRO All_nFETs_Off
  189. cbi PORTB, AnFET
  190. cbi PORTB, BnFET
  191. cbi PORTB, CnFET
  192. .ENDMACRO
  193. .MACRO ApFET_on
  194. sbrs Flags3, PGM_DIR_REV
  195. sbi PORTB, ApFET
  196. sbrc Flags3, PGM_DIR_REV
  197. sbi PORTB, CpFET
  198. .ENDMACRO
  199. .MACRO ApFET_off
  200. sbrs Flags3, PGM_DIR_REV
  201. cbi PORTB, ApFET
  202. sbrc Flags3, PGM_DIR_REV
  203. cbi PORTB, CpFET
  204. .ENDMACRO
  205. .MACRO BpFET_on
  206. sbi PORTB, BpFET
  207. .ENDMACRO
  208. .MACRO BpFET_off
  209. cbi PORTB, BpFET
  210. .ENDMACRO
  211. .MACRO CpFET_on
  212. sbrs Flags3, PGM_DIR_REV
  213. sbi PORTB, CpFET
  214. sbrc Flags3, PGM_DIR_REV
  215. sbi PORTB, ApFET
  216. .ENDMACRO
  217. .MACRO CpFET_off
  218. sbrs Flags3, PGM_DIR_REV
  219. cbi PORTB, CpFET
  220. sbrc Flags3, PGM_DIR_REV
  221. cbi PORTB, ApFET
  222. .ENDMACRO
  223. .MACRO All_pFETs_On
  224. sbi PORTB, ApFET
  225. sbi PORTB, BpFET
  226. sbi PORTB, CpFET
  227. .ENDMACRO
  228. .MACRO All_pFETs_Off
  229. cbi PORTB, ApFET
  230. cbi PORTB, BpFET
  231. cbi PORTB, CpFET
  232. .ENDMACRO
  233. .MACRO Comp_Init
  234. lds @0, ADCSRB ; Set Analog Comparator Multiplexer Enable
  235. sbr @0, (1<<ACME)
  236. sts ADCSRB, @0
  237. .ENDMACRO
  238. .MACRO Set_Comp_Phase_A
  239. sbrs Flags3, PGM_DIR_REV
  240. ldi @0, Mux_A ; Set comparator multiplexer to phase A
  241. sbrc Flags3, PGM_DIR_REV
  242. ldi @0, Mux_C
  243. ori @0, (1<<REFS1)+(1<<REFS0)
  244. sts ADMUX, @0
  245. .ENDMACRO
  246. .MACRO Set_Comp_Phase_B
  247. ldi @0, Mux_B ; Set comparator multiplexer to phase B
  248. ori @0, (1<<REFS1)+(1<<REFS0)
  249. sts ADMUX, @0
  250. .ENDMACRO
  251. .MACRO Set_Comp_Phase_C
  252. sbrs Flags3, PGM_DIR_REV
  253. ldi @0, Mux_C ; Set comparator multiplexer to phase C
  254. sbrc Flags3, PGM_DIR_REV
  255. ldi @0, Mux_A
  256. ori @0, (1<<REFS1)+(1<<REFS0)
  257. sts ADMUX, @0
  258. .ENDMACRO
  259. .MACRO Read_Comp_Out
  260. in @0, ACSR ; Read comparator output
  261. .ENDMACRO
  262. ;*********************
  263. ; PORT B definitions *
  264. ;*********************
  265. ;.EQU = 7 ; i
  266. ;.EQU = 6 ; i
  267. .EQU CnFET = 5 ; o
  268. .EQU BnFET = 4 ; o
  269. .EQU AnFET = 3 ; o
  270. .EQU ApFET = 2 ; o
  271. .EQU CpFET = 1 ; o
  272. .EQU BpFET = 0 ; o
  273. .EQU INIT_PB = 0
  274. .EQU DIR_PB = (1<<AnFET)+(1<<BnFET)+(1<<CnFET)+(1<<ApFET)+(1<<BpFET)+(1<<CpFET)
  275. ;**********************
  276. ; MCU specific macros *
  277. ;**********************
  278. .MACRO Interrupt_Table_Definition
  279. jmp reset
  280. rjmp rcp_int ; ext_int0
  281. nop
  282. nop ; ext_int1
  283. nop
  284. nop ; pci0_int
  285. nop
  286. nop ; pci1_int
  287. nop
  288. nop ; pci2_int
  289. nop
  290. nop ; wdt_int
  291. nop
  292. nop ; t2oca_int
  293. nop
  294. nop ; t2ocb_int
  295. nop
  296. rjmp t2_int ; t2ovfl_int
  297. nop
  298. nop ; icp1_int
  299. nop
  300. rjmp t1oca_int ; t1oca_int
  301. nop
  302. nop ; t1ocb_int
  303. nop
  304. nop ; t1ovfl_int
  305. nop
  306. nop ; t0oca_int
  307. nop
  308. nop ; t0ocb_int
  309. nop
  310. rjmp t0_int ; t0ovfl_int
  311. nop
  312. nop ; spi_int
  313. nop
  314. nop ; urxc
  315. nop
  316. nop ; udre
  317. nop
  318. nop ; utxc
  319. nop
  320. ; nop ; adc_int
  321. ; nop ; eep_int
  322. ; nop ; aci_int
  323. ; nop ; wire2_int
  324. ; nop ; spmc_int
  325. .ENDMACRO
  326. .MACRO Disable_Watchdog
  327. cli ; Disable interrupts
  328. wdr ; Reset watchdog timer
  329. in @0, MCUSR ; Clear WDRF in MCUSR
  330. andi @0, (0xFF & (0<<WDRF))
  331. out MCUSR, @0
  332. lds @0, WDTCSR ; Write logical one to WDCE and WDE
  333. ori @0, (1<<WDCE) | (1<<WDE)
  334. sts WDTCSR, @0
  335. ldi @0, (0<<WDE) ; Turn off WDT
  336. sts WDTCSR, @0
  337. .ENDMACRO
  338. .MACRO Enable_Watchdog
  339. ldi @0, (1<<WDE) ; Turn on WDT
  340. sts WDTCSR, @0
  341. .ENDMACRO
  342. .MACRO Initialize_MCU
  343. .ENDMACRO
  344. .MACRO Initialize_Interrupts
  345. ldi @0, (1<<TOIE0)
  346. out TIFR0, @0 ; Clear interrupts
  347. sts TIMSK0, @0 ; Enable interrupts
  348. ldi @0, (1<<OCIE1A)
  349. out TIFR1, @0 ; Clear interrupts
  350. sts TIMSK1, @0 ; Enable interrupts
  351. ldi @0, (1<<TOIE2)
  352. out TIFR2, @0 ; Clear interrupts
  353. sts TIMSK2, @0 ; Enable interrupts
  354. .ENDMACRO
  355. .MACRO Initialize_Adc
  356. lds @0, ADCSRA ; Set ADCSRA register (1MHz clock)
  357. sbr @0, (1<<ADPS2)
  358. sts ADCSRA, @0
  359. .ENDMACRO
  360. .MACRO Set_Adc_Ip_Volt
  361. cbr Flags1, (1<<ADC_READ_TEMP)
  362. .ENDMACRO
  363. .MACRO Set_Adc_Ip_Temp
  364. sbr Flags1, (1<<ADC_READ_TEMP)
  365. .ENDMACRO
  366. .MACRO Start_Adc
  367. sbrs Flags1, ADC_READ_TEMP
  368. ldi @0, Volt_Ip
  369. sbrc Flags1, ADC_READ_TEMP
  370. ldi @0, Volt_Ip
  371. ori @0, (1<<REFS1)+(1<<REFS0)
  372. sts ADMUX, @0 ; Set ADMUX register (1.1V reference, selected input)
  373. lds @0, ADCSRA
  374. sbr @0, (1<<ADEN) ; Enable ADC
  375. sbr @0, (1<<ADSC) ; Start ADC conversion
  376. sts ADCSRA, @0
  377. .ENDMACRO
  378. .MACRO Get_Adc_Status
  379. lds @0, ADCSRA
  380. .ENDMACRO
  381. .MACRO Read_Adc_Result
  382. lds @0, ADCL
  383. lds @1, ADCH
  384. .ENDMACRO
  385. .MACRO Stop_Adc
  386. lds @0, ADCSRA
  387. cbr @0, (1<<ADEN) ; Disable ADC
  388. sts ADCSRA, @0
  389. .ENDMACRO
  390. .MACRO Set_Timer0_CS0
  391. out TCCR0B, @0
  392. .ENDMACRO
  393. .MACRO Set_Timer1_CS1
  394. sts TCCR1B, @0
  395. .ENDMACRO
  396. .MACRO Set_Timer2_CS2
  397. sts TCCR2B, @0
  398. .ENDMACRO
  399. .MACRO Read_TCNT1L
  400. lds @0, TCNT1L
  401. .ENDMACRO
  402. .MACRO Read_TCNT1H
  403. lds @0, TCNT1H
  404. .ENDMACRO
  405. .MACRO Set_OCR1AL
  406. sts OCR1AL, @0
  407. .ENDMACRO
  408. .MACRO Set_OCR1AH
  409. sts OCR1AH, @0
  410. .ENDMACRO
  411. .MACRO Read_TCNT2
  412. lds @0, TCNT2
  413. .ENDMACRO
  414. .MACRO Set_TCNT2
  415. sts TCNT2, @0
  416. .ENDMACRO
  417. .MACRO Check_Eeprom_Ready
  418. sbic EECR, EEPE
  419. .ENDMACRO
  420. .MACRO Set_Eeprom_Address
  421. out EEARL, @0
  422. out EEARH, @1
  423. .ENDMACRO
  424. .MACRO Start_Eeprom_Write
  425. sbi EECR, EEMPE
  426. sbi EECR, EEPE
  427. .ENDMACRO
  428. .MACRO Prepare_Lock_Or_Fuse_Read
  429. ldi @0, ((1<<BLBSET)+(1<<SELFPRGEN))
  430. out SPMCSR, @0
  431. .ENDMACRO
  432. .MACRO xcall
  433. call @0
  434. .ENDMACRO
  435. .MACRO Set_RPM_Out
  436. .ENDMACRO
  437. .MACRO Clear_RPM_Out
  438. .ENDMACRO