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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; SuperSimple 20A hardware definition file
  26. ;
  27. ; Notes: None
  28. ;
  29. ;**** **** **** **** ****
  30. ;*********************
  31. ; Device Atmega8L
  32. ;*********************
  33. .INCLUDE "m8def.inc"
  34. ;**** **** **** **** ****
  35. ; Fuses must be set to external oscillator = 16Mhz
  36. ;**** **** **** **** ****
  37. ;**** **** **** **** ****
  38. ; Constant definitions
  39. ;**** **** **** **** ****
  40. .ESEG ; EEprom segment
  41. .ORG 0x40
  42. Eep_ESC_Layout: .DB "#SuperS_20A# " ; ESC layout tag
  43. .ORG 0x50
  44. Eep_ESC_MCU: .DB "#BLHELI#Am8L# " ; Project and MCU tag (16 Bytes)
  45. .EQU HIGH_BEC_VOLTAGE = 0 ; Set to 1 or more if high BEC voltage is supported
  46. .EQU DAMPED_MODE_ENABLE = 0 ; Set to 1 if fully damped mode is supported
  47. .EQU NFETON_DELAY = 30 ; Wait delay from pfets off to nfets on
  48. .EQU PFETON_DELAY = 5 ; Wait delay from nfets off to pfets on
  49. .EQU HIGH_DRIVER_PRECHG_TIME = 0 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  50. .EQU ADC_LIMIT_L = 101 ; 4.3k/47k divider. Power supply measurement ADC value for which motor power is limited (low byte)
  51. .EQU ADC_LIMIT_H = 0 ; 4.3k/47k divider. Power supply measurement ADC value for which motor power is limited (2 MSBs)
  52. .EQU TEMP_LIMIT = 0 ; No sensor. Temperature measurement ADC value for which main motor power is limited
  53. .EQU TEMP_LIMIT_STEP = 0 ; No sensor. Temperature measurement ADC value increment for which main motor power is further limited
  54. ;**** **** **** **** ****
  55. ; ESC specific defaults
  56. ;**** **** **** **** ****
  57. .EQU DEFAULT_PGM_MAIN_SPOOLUP_TIME = 10 ; Main motor spoolup time
  58. .EQU DEFAULT_PGM_MAIN_STARTUP_PWR = 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  59. .EQU DEFAULT_PGM_TAIL_STARTUP_PWR = 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  60. .EQU DEFAULT_PGM_MULTI_STARTUP_PWR = 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  61. ;*********************
  62. ; PORT D definitions *
  63. ;*********************
  64. .EQU BpFET = 7 ;o
  65. ;.EQU = 6 ;i
  66. .EQU ApFET = 5 ;o
  67. .EQU CpFET = 4 ;o
  68. .EQU CnFET = 3 ;o
  69. .EQU Rcp_In = 2 ;i
  70. .EQU BnFET = 1 ;o
  71. .EQU AnFET = 0 ;o
  72. .equ INIT_PD = 0x00
  73. .equ DIR_PD = (1<<AnFET)+(1<<BnFET)+(1<<CnFET)+(1<<ApFET)+(1<<BpFET)+(1<<CpFET)
  74. .MACRO Get_Rcp_Capture_Values
  75. in @0, TCNT1L
  76. in @1, TCNT1H
  77. .ENDMACRO
  78. .MACRO Read_Rcp_Int
  79. in @0, PIND
  80. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  81. com @0 ; Yes - invert
  82. .ENDMACRO
  83. .MACRO Get_Rcp_Int_Enable_State
  84. in @0, GICR ; Get int0 enable state (giving 0 is off, anything else is on)
  85. andi @0, (1<<INT0)
  86. .ENDMACRO
  87. .MACRO Rcp_Int_Enable
  88. ldi @0, (1<<INT0) ; Enable int0
  89. out GICR, @0
  90. .ENDMACRO
  91. .MACRO Rcp_Int_Disable
  92. ldi @0, 0 ; Disable int0
  93. out GICR, @0
  94. .ENDMACRO
  95. .MACRO Rcp_Int_First
  96. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  97. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  98. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  99. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  100. out MCUCR, @0
  101. .ENDMACRO
  102. .MACRO Rcp_Int_Second
  103. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  104. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  105. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  106. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  107. out MCUCR, @0
  108. .ENDMACRO
  109. .MACRO Rcp_Clear_Int_Flag
  110. clr @0
  111. sbr @0, (1<<INTF0) ; Clear ext0int flag
  112. out GIFR, @0
  113. .ENDMACRO
  114. .MACRO T0_Int_Disable
  115. in @0, TIMSK ; Disable timer0 interrupts
  116. cbr @0, (1<<TOIE0)
  117. out TIMSK, @0
  118. .ENDMACRO
  119. .MACRO T0_Int_Enable
  120. in @0, TIMSK ; Enable timer0 interrupts
  121. sbr @0, (1<<TOIE0)
  122. out TIMSK, @0
  123. .ENDMACRO
  124. .MACRO T1oca_Clear_Int_Flag
  125. ldi @0, (1<<OCF1A) ; Clear oc1a flag
  126. out TIFR, @0
  127. .ENDMACRO
  128. .MACRO T1oca_Int_Disable
  129. in @0, TIMSK ; Disable oc1a interrupts
  130. cbr @0, (1<<OCIE1A)
  131. out TIMSK, @0
  132. .ENDMACRO
  133. .MACRO T1oca_Int_Enable
  134. in @0, TIMSK ; Enable oc1a interrupts
  135. sbr @0, (1<<OCIE1A)
  136. out TIMSK, @0
  137. .ENDMACRO
  138. ;*********************
  139. ; PORT C definitions *
  140. ;*********************
  141. .EQU Volt_Ip = 7 ; i
  142. ;.EQU = 6 ; i
  143. ;.EQU = 5 ; i
  144. .EQU Mux_C = 4 ; i
  145. .EQU Mux_B = 3 ; i
  146. .EQU Mux_A = 2 ; i
  147. ;.EQU = 1 ; i
  148. ;.EQU = 0 ; i
  149. .equ INIT_PC = 0x00
  150. .equ DIR_PC = 0x00
  151. .MACRO AnFET_on
  152. tst Current_Pwm_Limited
  153. breq PC+5
  154. sbrs Flags3, PGM_DIR_REV
  155. sbi PORTD, AnFET
  156. sbrc Flags3, PGM_DIR_REV
  157. sbi PORTD, CnFET
  158. .ENDMACRO
  159. .MACRO AnFET_off
  160. sbrs Flags3, PGM_DIR_REV
  161. cbi PORTD, AnFET
  162. sbrc Flags3, PGM_DIR_REV
  163. cbi PORTD, CnFET
  164. .ENDMACRO
  165. .MACRO BnFET_on
  166. tst Current_Pwm_Limited
  167. breq PC+2
  168. sbi PORTD, BnFET
  169. .ENDMACRO
  170. .MACRO BnFET_off
  171. cbi PORTD, BnFET
  172. .ENDMACRO
  173. .MACRO CnFET_on
  174. tst Current_Pwm_Limited
  175. breq PC+5
  176. sbrs Flags3, PGM_DIR_REV
  177. sbi PORTD, CnFET
  178. sbrc Flags3, PGM_DIR_REV
  179. sbi PORTD, AnFET
  180. .ENDMACRO
  181. .MACRO CnFET_off
  182. sbrs Flags3, PGM_DIR_REV
  183. cbi PORTD, CnFET
  184. sbrc Flags3, PGM_DIR_REV
  185. cbi PORTD, AnFET
  186. .ENDMACRO
  187. .MACRO All_nFETs_Off
  188. cbi PORTD, AnFET
  189. cbi PORTD, BnFET
  190. cbi PORTD, CnFET
  191. .ENDMACRO
  192. .MACRO ApFET_on
  193. sbrs Flags3, PGM_DIR_REV
  194. sbi PORTD, ApFET
  195. sbrc Flags3, PGM_DIR_REV
  196. sbi PORTD, CpFET
  197. .ENDMACRO
  198. .MACRO ApFET_off
  199. sbrs Flags3, PGM_DIR_REV
  200. cbi PORTD, ApFET
  201. sbrc Flags3, PGM_DIR_REV
  202. cbi PORTD, CpFET
  203. .ENDMACRO
  204. .MACRO BpFET_on
  205. sbi PORTD, BpFET
  206. .ENDMACRO
  207. .MACRO BpFET_off
  208. cbi PORTD, BpFET
  209. .ENDMACRO
  210. .MACRO CpFET_on
  211. sbrs Flags3, PGM_DIR_REV
  212. sbi PORTD, CpFET
  213. sbrc Flags3, PGM_DIR_REV
  214. sbi PORTD, ApFET
  215. .ENDMACRO
  216. .MACRO CpFET_off
  217. sbrs Flags3, PGM_DIR_REV
  218. cbi PORTD, CpFET
  219. sbrc Flags3, PGM_DIR_REV
  220. cbi PORTD, ApFET
  221. .ENDMACRO
  222. .MACRO All_pFETs_On
  223. sbi PORTD, ApFET
  224. sbi PORTD, BpFET
  225. sbi PORTD, CpFET
  226. .ENDMACRO
  227. .MACRO All_pFETs_Off
  228. cbi PORTD, ApFET
  229. cbi PORTD, BpFET
  230. cbi PORTD, CpFET
  231. .ENDMACRO
  232. .MACRO Comp_Init
  233. in @0, SFIOR ; Set Analog Comparator Multiplexer Enable
  234. sbr @0, (1<<ACME)
  235. out SFIOR, @0
  236. .ENDMACRO
  237. .MACRO Set_Comp_Phase_A
  238. sbrs Flags3, PGM_DIR_REV
  239. ldi @0, Mux_A ; Set comparator multiplexer to phase A
  240. sbrc Flags3, PGM_DIR_REV
  241. ldi @0, Mux_C
  242. sbr @0, (1<<REFS1)
  243. sbr @0, (1<<REFS0)
  244. out ADMUX, @0
  245. .ENDMACRO
  246. .MACRO Set_Comp_Phase_B
  247. ldi @0, Mux_B ; Set comparator multiplexer to phase B
  248. sbr @0, (1<<REFS1)
  249. sbr @0, (1<<REFS0)
  250. out ADMUX, @0
  251. .ENDMACRO
  252. .MACRO Set_Comp_Phase_C
  253. sbrs Flags3, PGM_DIR_REV
  254. ldi @0, Mux_C ; Set comparator multiplexer to phase C
  255. sbrc Flags3, PGM_DIR_REV
  256. ldi @0, Mux_A
  257. sbr @0, (1<<REFS1)
  258. sbr @0, (1<<REFS0)
  259. out ADMUX, @0
  260. .ENDMACRO
  261. .MACRO Read_Comp_Out
  262. in @0, ACSR ; Read comparator output
  263. .ENDMACRO
  264. ;*********************
  265. ; PORT B definitions *
  266. ;*********************
  267. ;.EQU = 7 ; i
  268. ;.EQU = 6 ; i
  269. ;.EQU = 5 ; i
  270. .EQU DebugPin = 4 ; o
  271. ;.EQU = 3 ; i
  272. ;.EQU = 2 ; i
  273. ;.EQU = 1 ; i
  274. ;.EQU = 0 ; i
  275. .EQU INIT_PB = 0x00
  276. .EQU DIR_PB = (1<<DebugPin)
  277. ;**********************
  278. ; MCU specific macros *
  279. ;**********************
  280. .MACRO Interrupt_Table_Definition
  281. rjmp reset
  282. rjmp rcp_int ; ext_int0
  283. nop ; ext_int1
  284. nop ; t2oc_int
  285. rjmp t2_int ; t2ovfl_int
  286. nop ; icp1_int
  287. rjmp t1oca_int ; t1oca_int
  288. nop ; t1ocb_int
  289. nop ; t1ovfl_int
  290. rjmp t0_int ; t0ovfl_int
  291. nop ; spi_int
  292. nop ; urxc
  293. nop ; udre
  294. nop ; utxc
  295. ; nop ; adc_int
  296. ; nop ; eep_int
  297. ; nop ; aci_int
  298. ; nop ; wire2_int
  299. ; nop ; spmc_int
  300. .ENDMACRO
  301. .MACRO Disable_Watchdog
  302. cli ; Disable interrupts
  303. wdr ; Reset watchdog timer
  304. in @0, WDTCR ; Write logical one to WDCE and WDE
  305. ori @0, (1<<WDCE)|(1<<WDE)
  306. out WDTCR, @0
  307. ldi @0, (0<<WDE) ; Turn off WDT
  308. out WDTCR, @0
  309. .ENDMACRO
  310. .MACRO Enable_Watchdog
  311. ldi @0, (1<<WDE) ; Turn on WDT
  312. out WDTCR, @0
  313. .ENDMACRO
  314. .MACRO Initialize_MCU
  315. .ENDMACRO
  316. .MACRO Initialize_Interrupts
  317. ldi @0, (1<<TOIE0)+(1<<OCIE1A)+(1<<TOIE2)
  318. out TIFR, @0 ; Clear interrupts
  319. out TIMSK, @0 ; Enable interrupts
  320. .ENDMACRO
  321. .MACRO Initialize_Adc
  322. in @0, ADCSRA ; Set ADCSRA register (1MHz clock)
  323. sbr @0, (1<<ADPS2)
  324. out ADCSRA, @0
  325. .ENDMACRO
  326. .MACRO Set_Adc_Ip_Volt
  327. cbr Flags1, (1<<ADC_READ_TEMP)
  328. .ENDMACRO
  329. .MACRO Set_Adc_Ip_Temp
  330. sbr Flags1, (1<<ADC_READ_TEMP)
  331. .ENDMACRO
  332. .MACRO Start_Adc
  333. sbrs Flags1, ADC_READ_TEMP
  334. ldi @0, Volt_Ip
  335. sbrc Flags1, ADC_READ_TEMP
  336. ldi @0, Volt_Ip ; No temp sensor
  337. sbr @0, (1<<REFS1)
  338. sbr @0, (1<<REFS0)
  339. out ADMUX, @0 ; Set ADMUX register (2.56V reference, selected input)
  340. in @0, ADCSRA
  341. sbr @0, (1<<ADEN) ; Enable ADC
  342. sbr @0, (1<<ADSC) ; Start ADC conversion
  343. out ADCSRA, @0
  344. .ENDMACRO
  345. .MACRO Get_Adc_Status
  346. in @0, ADCSRA
  347. .ENDMACRO
  348. .MACRO Read_Adc_Result
  349. in @0, ADCL
  350. in @1, ADCH
  351. .ENDMACRO
  352. .MACRO Stop_Adc
  353. in @0, ADCSRA
  354. cbr @0, (1<<ADEN) ; Disable ADC
  355. out ADCSRA, @0
  356. .ENDMACRO
  357. .MACRO Set_Timer0_CS0
  358. out TCCR0, @0
  359. .ENDMACRO
  360. .MACRO Set_Timer1_CS1
  361. out TCCR1B, @0
  362. .ENDMACRO
  363. .MACRO Set_Timer2_CS2
  364. out TCCR2, @0
  365. .ENDMACRO
  366. .MACRO Read_TCNT1L
  367. in @0, TCNT1L
  368. .ENDMACRO
  369. .MACRO Read_TCNT1H
  370. in @0, TCNT1H
  371. .ENDMACRO
  372. .MACRO Set_OCR1AL
  373. out OCR1AL, @0
  374. .ENDMACRO
  375. .MACRO Set_OCR1AH
  376. out OCR1AH, @0
  377. .ENDMACRO
  378. .MACRO Read_TCNT2
  379. in @0, TCNT2
  380. .ENDMACRO
  381. .MACRO Set_TCNT2
  382. out TCNT2, @0
  383. .ENDMACRO
  384. .MACRO Check_Eeprom_Ready
  385. sbic EECR, EEWE
  386. .ENDMACRO
  387. .MACRO Set_Eeprom_Address
  388. out EEARL, @0
  389. out EEARH, @1
  390. .ENDMACRO
  391. .MACRO Start_Eeprom_Write
  392. sbi EECR, EEMWE
  393. sbi EECR, EEWE
  394. .ENDMACRO
  395. .MACRO Prepare_Lock_Or_Fuse_Read
  396. ldi @0, ((1<<BLBSET)+(1<<SPMEN))
  397. out SPMCR, @0
  398. .ENDMACRO
  399. .MACRO xcall
  400. rcall @0
  401. .ENDMACRO
  402. .MACRO Set_RPM_Out
  403. .ENDMACRO
  404. .MACRO Clear_RPM_Out
  405. .ENDMACRO