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10 KiB

11 years ago
  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hobbyking UBEC 40A hardware definition file
  26. ;
  27. ; Notes:
  28. ; - On 2S low voltage limiting does not work fully according to spec, as ADC reference drops with sensed voltage
  29. ;
  30. ;**** **** **** **** ****
  31. ;*********************
  32. ; Device Atmega8A
  33. ;*********************
  34. .INCLUDE "m8Adef.inc"
  35. ;**** **** **** **** ****
  36. ; Fuses must be set to external oscillator = 16Mhz
  37. ;**** **** **** **** ****
  38. ;**** **** **** **** ****
  39. ; Constant definitions
  40. ;**** **** **** **** ****
  41. .ESEG ; EEprom segment
  42. .ORG 0x40
  43. Eep_ESC_Layout: .DB "#HK_UBEC_40A# " ; ESC layout tag
  44. .ORG 0x50
  45. Eep_ESC_MCU: .DB "#BLHELI#Am8A# " ; Project and MCU tag (16 Bytes)
  46. .EQU HIGH_BEC_VOLTAGE = 0 ; Set to 1 or more if high BEC voltage is supported
  47. .EQU DAMPED_MODE_ENABLE = 1 ; Set to 1 if fully damped mode is supported
  48. .EQU NFETON_DELAY = 5 ; Wait delay from pfets off to nfets on
  49. .EQU PFETON_DELAY = 5 ; Wait delay from nfets off to pfets on
  50. .EQU HIGH_DRIVER_PRECHG_TIME = 0 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  51. .EQU ADC_LIMIT_L = 116 ; 51k/220k divider. Power supply measurement ADC value for which motor power is limited (low byte)
  52. .EQU ADC_LIMIT_H = 0 ; 51k/220k divider. Power supply measurement ADC value for which motor power is limited (2 MSBs)
  53. .EQU TEMP_LIMIT = 188 ; 1k5/10kNTC. Temperature measurement ADC value for which main motor power is limited
  54. .EQU TEMP_LIMIT_STEP = 14 ; 1k5/10kNTC. Temperature measurement ADC value increment for which main motor power is further limited
  55. ;**** **** **** **** ****
  56. ; ESC specific defaults
  57. ;**** **** **** **** ****
  58. .EQU DEFAULT_PGM_MAIN_SPOOLUP_TIME = 10 ; Main motor spoolup time
  59. .EQU DEFAULT_PGM_MAIN_STARTUP_PWR = 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  60. .EQU DEFAULT_PGM_TAIL_STARTUP_PWR = 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  61. .EQU DEFAULT_PGM_MULTI_STARTUP_PWR = 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  62. ;*********************
  63. ; PORT D definitions *
  64. ;*********************
  65. ;.EQU = 7 ;i
  66. ;.EQU = 6 ;i
  67. .EQU AnFET = 5 ;o
  68. .EQU ApFET = 4 ;o
  69. ;.EQU = 3 ;i
  70. .EQU Rcp_In = 2 ;i
  71. ;.EQU = 1 ;i
  72. ;.EQU = 0 ;i
  73. .equ INIT_PD = 0x00
  74. .equ DIR_PD = (1<<AnFET)+(1<<ApFET)
  75. .MACRO Get_Rcp_Capture_Values
  76. in @0, TCNT1L
  77. in @1, TCNT1H
  78. .ENDMACRO
  79. .MACRO Read_Rcp_Int
  80. in @0, PIND
  81. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  82. com @0 ; Yes - invert
  83. .ENDMACRO
  84. .MACRO Get_Rcp_Int_Enable_State
  85. in @0, GICR ; Get int0 enable state (giving 0 is off, anything else is on)
  86. andi @0, (1<<INT0)
  87. .ENDMACRO
  88. .MACRO Rcp_Int_Enable
  89. ldi @0, (1<<INT0) ; Enable int0
  90. out GICR, @0
  91. .ENDMACRO
  92. .MACRO Rcp_Int_Disable
  93. ldi @0, 0 ; Disable int0
  94. out GICR, @0
  95. .ENDMACRO
  96. .MACRO Rcp_Int_First
  97. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  98. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  99. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  100. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  101. out MCUCR, @0
  102. .ENDMACRO
  103. .MACRO Rcp_Int_Second
  104. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  105. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  106. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  107. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  108. out MCUCR, @0
  109. .ENDMACRO
  110. .MACRO Rcp_Clear_Int_Flag
  111. clr @0
  112. sbr @0, (1<<INTF0) ; Clear ext0int flag
  113. out GIFR, @0
  114. .ENDMACRO
  115. .MACRO T0_Int_Disable
  116. in @0, TIMSK ; Disable timer0 interrupts
  117. cbr @0, (1<<TOIE0)
  118. out TIMSK, @0
  119. .ENDMACRO
  120. .MACRO T0_Int_Enable
  121. in @0, TIMSK ; Enable timer0 interrupts
  122. sbr @0, (1<<TOIE0)
  123. out TIMSK, @0
  124. .ENDMACRO
  125. .MACRO T1oca_Clear_Int_Flag
  126. ldi @0, (1<<OCF1A) ; Clear oc1a flag
  127. out TIFR, @0
  128. .ENDMACRO
  129. .MACRO T1oca_Int_Disable
  130. in @0, TIMSK ; Disable oc1a interrupts
  131. cbr @0, (1<<OCIE1A)
  132. out TIMSK, @0
  133. .ENDMACRO
  134. .MACRO T1oca_Int_Enable
  135. in @0, TIMSK ; Enable oc1a interrupts
  136. sbr @0, (1<<OCIE1A)
  137. out TIMSK, @0
  138. .ENDMACRO
  139. ;*********************
  140. ; PORT C definitions *
  141. ;*********************
  142. .EQU Mux_B = 7 ; i
  143. .EQU Mux_A = 6 ; i
  144. .EQU BpFET = 5 ; i
  145. .EQU BnFET = 4 ; i
  146. .EQU CpFET = 3 ; i
  147. .EQU Volt_Ip = 2 ; i
  148. .EQU Temp_Ip = 1 ; i
  149. .EQU Mux_C = 0 ; i
  150. .equ INIT_PC = 0x00
  151. .equ DIR_PC = (1<<BnFET)+(1<<BpFET)+(1<<CpFET)
  152. .MACRO AnFET_on
  153. tst Current_Pwm_Limited
  154. breq PC+5
  155. sbrs Flags3, PGM_DIR_REV
  156. sbi PORTD, AnFET
  157. sbrc Flags3, PGM_DIR_REV
  158. sbi PORTB, CnFET
  159. .ENDMACRO
  160. .MACRO AnFET_off
  161. sbrs Flags3, PGM_DIR_REV
  162. cbi PORTD, AnFET
  163. sbrc Flags3, PGM_DIR_REV
  164. cbi PORTB, CnFET
  165. .ENDMACRO
  166. .MACRO BnFET_on
  167. tst Current_Pwm_Limited
  168. breq PC+2
  169. sbi PORTC, BnFET
  170. .ENDMACRO
  171. .MACRO BnFET_off
  172. cbi PORTC, BnFET
  173. .ENDMACRO
  174. .MACRO CnFET_on
  175. tst Current_Pwm_Limited
  176. breq PC+5
  177. sbrs Flags3, PGM_DIR_REV
  178. sbi PORTB, CnFET
  179. sbrc Flags3, PGM_DIR_REV
  180. sbi PORTD, AnFET
  181. .ENDMACRO
  182. .MACRO CnFET_off
  183. sbrs Flags3, PGM_DIR_REV
  184. cbi PORTB, CnFET
  185. sbrc Flags3, PGM_DIR_REV
  186. cbi PORTD, AnFET
  187. .ENDMACRO
  188. .MACRO All_nFETs_Off
  189. cbi PORTD, AnFET
  190. cbi PORTC, BnFET
  191. cbi PORTB, CnFET
  192. .ENDMACRO
  193. .MACRO ApFET_on
  194. sbrs Flags3, PGM_DIR_REV
  195. sbi PORTD, ApFET
  196. sbrc Flags3, PGM_DIR_REV
  197. sbi PORTC, CpFET
  198. .ENDMACRO
  199. .MACRO ApFET_off
  200. sbrs Flags3, PGM_DIR_REV
  201. cbi PORTD, ApFET
  202. sbrc Flags3, PGM_DIR_REV
  203. cbi PORTC, CpFET
  204. .ENDMACRO
  205. .MACRO BpFET_on
  206. sbi PORTC, BpFET
  207. .ENDMACRO
  208. .MACRO BpFET_off
  209. cbi PORTC, BpFET
  210. .ENDMACRO
  211. .MACRO CpFET_on
  212. sbrs Flags3, PGM_DIR_REV
  213. sbi PORTC, CpFET
  214. sbrc Flags3, PGM_DIR_REV
  215. sbi PORTD, ApFET
  216. .ENDMACRO
  217. .MACRO CpFET_off
  218. sbrs Flags3, PGM_DIR_REV
  219. cbi PORTC, CpFET
  220. sbrc Flags3, PGM_DIR_REV
  221. cbi PORTD, ApFET
  222. .ENDMACRO
  223. .MACRO All_pFETs_On
  224. sbi PORTD, ApFET
  225. sbi PORTC, BpFET
  226. sbi PORTC, CpFET
  227. .ENDMACRO
  228. .MACRO All_pFETs_Off
  229. cbi PORTD, ApFET
  230. cbi PORTC, BpFET
  231. cbi PORTC, CpFET
  232. .ENDMACRO
  233. .MACRO Comp_Init
  234. in @0, SFIOR ; Set Analog Comparator Multiplexer Enable
  235. sbr @0, (1<<ACME)
  236. out SFIOR, @0
  237. .ENDMACRO
  238. .MACRO Set_Comp_Phase_A
  239. sbrs Flags3, PGM_DIR_REV
  240. ldi @0, Mux_A ; Set comparator multiplexer to phase A
  241. sbrc Flags3, PGM_DIR_REV
  242. ldi @0, Mux_C
  243. out ADMUX, @0
  244. .ENDMACRO
  245. .MACRO Set_Comp_Phase_B
  246. ldi @0, Mux_B ; Set comparator multiplexer to phase B
  247. out ADMUX, @0
  248. .ENDMACRO
  249. .MACRO Set_Comp_Phase_C
  250. sbrs Flags3, PGM_DIR_REV
  251. ldi @0, Mux_C ; Set comparator multiplexer to phase C
  252. sbrc Flags3, PGM_DIR_REV
  253. ldi @0, Mux_A
  254. out ADMUX, @0
  255. .ENDMACRO
  256. .MACRO Read_Comp_Out
  257. in @0, ACSR ; Read comparator output
  258. .ENDMACRO
  259. ;*********************
  260. ; PORT B definitions *
  261. ;*********************
  262. ;.EQU = 7 ; i
  263. ;.EQU = 6 ; i
  264. ;.EQU = 5 ; i
  265. .EQU DebugPin = 4 ; o
  266. ;.EQU = 3 ; i
  267. ;.EQU = 2 ; i
  268. ;.EQU = 1 ; i
  269. .EQU CnFET = 0 ; o
  270. .EQU INIT_PB = 0x00
  271. .EQU DIR_PB = (1<<CnFET)+(1<<DebugPin)
  272. ;**********************
  273. ; MCU specific macros *
  274. ;**********************
  275. .MACRO Interrupt_Table_Definition
  276. rjmp reset
  277. rjmp rcp_int ; ext_int0
  278. nop ; ext_int1
  279. nop ; t2oc_int
  280. rjmp t2_int ; t2ovfl_int
  281. nop ; icp1_int
  282. rjmp t1oca_int ; t1oca_int
  283. nop ; t1ocb_int
  284. nop ; t1ovfl_int
  285. rjmp t0_int ; t0ovfl_int
  286. nop ; spi_int
  287. nop ; urxc
  288. nop ; udre
  289. nop ; utxc
  290. ; nop ; adc_int
  291. ; nop ; eep_int
  292. ; nop ; aci_int
  293. ; nop ; wire2_int
  294. ; nop ; spmc_int
  295. .ENDMACRO
  296. .MACRO Disable_Watchdog
  297. cli ; Disable interrupts
  298. wdr ; Reset watchdog timer
  299. in @0, WDTCR ; Write logical one to WDCE and WDE
  300. ori @0, (1<<WDCE)|(1<<WDE)
  301. out WDTCR, @0
  302. ldi @0, (0<<WDE) ; Turn off WDT
  303. out WDTCR, @0
  304. .ENDMACRO
  305. .MACRO Enable_Watchdog
  306. ldi @0, (1<<WDE) ; Turn on WDT
  307. out WDTCR, @0
  308. .ENDMACRO
  309. .MACRO Initialize_MCU
  310. .ENDMACRO
  311. .MACRO Initialize_Interrupts
  312. ldi @0, (1<<TOIE0)+(1<<OCIE1A)+(1<<TOIE2)
  313. out TIFR, @0 ; Clear interrupts
  314. out TIMSK, @0 ; Enable interrupts
  315. .ENDMACRO
  316. .MACRO Initialize_Adc
  317. in @0, ADCSRA ; Set ADCSRA register (1MHz clock)
  318. sbr @0, (1<<ADPS2)
  319. out ADCSRA, @0
  320. .ENDMACRO
  321. .MACRO Set_Adc_Ip_Volt
  322. cbr Flags1, (1<<ADC_READ_TEMP)
  323. .ENDMACRO
  324. .MACRO Set_Adc_Ip_Temp
  325. sbr Flags1, (1<<ADC_READ_TEMP)
  326. .ENDMACRO
  327. .MACRO Start_Adc
  328. sbrs Flags1, ADC_READ_TEMP
  329. ldi @0, Volt_Ip
  330. sbrc Flags1, ADC_READ_TEMP
  331. ldi @0, Temp_Ip
  332. out ADMUX, @0 ; Set ADMUX register (5V reference, selected input)
  333. in @0, ADCSRA
  334. sbr @0, (1<<ADEN) ; Enable ADC
  335. sbr @0, (1<<ADSC) ; Start ADC conversion
  336. out ADCSRA, @0
  337. .ENDMACRO
  338. .MACRO Get_Adc_Status
  339. in @0, ADCSRA
  340. .ENDMACRO
  341. .MACRO Read_Adc_Result
  342. in @0, ADCL
  343. in @1, ADCH
  344. .ENDMACRO
  345. .MACRO Stop_Adc
  346. in @0, ADCSRA
  347. cbr @0, (1<<ADEN) ; Disable ADC
  348. out ADCSRA, @0
  349. .ENDMACRO
  350. .MACRO Set_Timer0_CS0
  351. out TCCR0, @0
  352. .ENDMACRO
  353. .MACRO Set_Timer1_CS1
  354. out TCCR1B, @0
  355. .ENDMACRO
  356. .MACRO Set_Timer2_CS2
  357. out TCCR2, @0
  358. .ENDMACRO
  359. .MACRO Read_TCNT1L
  360. in @0, TCNT1L
  361. .ENDMACRO
  362. .MACRO Read_TCNT1H
  363. in @0, TCNT1H
  364. .ENDMACRO
  365. .MACRO Set_OCR1AL
  366. out OCR1AL, @0
  367. .ENDMACRO
  368. .MACRO Set_OCR1AH
  369. out OCR1AH, @0
  370. .ENDMACRO
  371. .MACRO Read_TCNT2
  372. in @0, TCNT2
  373. .ENDMACRO
  374. .MACRO Set_TCNT2
  375. out TCNT2, @0
  376. .ENDMACRO
  377. .MACRO Check_Eeprom_Ready
  378. sbic EECR, EEWE
  379. .ENDMACRO
  380. .MACRO Set_Eeprom_Address
  381. out EEARL, @0
  382. out EEARH, @1
  383. .ENDMACRO
  384. .MACRO Start_Eeprom_Write
  385. sbi EECR, EEMWE
  386. sbi EECR, EEWE
  387. .ENDMACRO
  388. .MACRO Prepare_Lock_Or_Fuse_Read
  389. ldi @0, ((1<<BLBSET)+(1<<SPMEN))
  390. out SPMCR, @0
  391. .ENDMACRO
  392. .MACRO xcall
  393. rcall @0
  394. .ENDMACRO
  395. .MACRO Set_RPM_Out
  396. .ENDMACRO
  397. .MACRO Clear_RPM_Out
  398. .ENDMACRO