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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Turnigy Plush Nfet 25A hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device SiLabs F330
  30. ;*********************
  31. $include (c8051f330.inc)
  32. ;**** **** **** **** ****
  33. ; Uses internal calibrated oscillator set to 24Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. CSEG AT 1A40h
  39. Eep_ESC_Layout: DB "#TurnigyNfet25A#" ; ESC layout tag
  40. CSEG AT 1A50h
  41. Eep_ESC_MCU: DB "#BLHELI#F330# " ; Project and MCU tag (16 Bytes)
  42. MCU_50MHZ EQU 0 ; Set to 1 if MCU can run at 50MHz
  43. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  44. PORT3_EXIST EQU 0 ; Set to 1 if MCU has port3
  45. COMP1_USED EQU 0 ; Set to 1 if MCU has comparator 1 and it is being used
  46. LOCK_BYTE_ADDRESS_16K EQU 3FFFh ; Address of lock byte if 16k flash size
  47. LOCK_BYTE_ADDRESS_8K EQU 1DFFh ; Address of lock byte if 8k flash size
  48. HIGH_BEC_VOLTAGE EQU 0 ; Set to 1 or more if high BEC voltage is supported
  49. DAMPED_MODE_ENABLE EQU 1 ; Damped mode enabled
  50. NFETON_DELAY EQU 6 ; Wait delay from pfets off to nfets on
  51. PFETON_DELAY EQU 6 ; Wait delay from nfets off to pfets on
  52. HIGH_DRIVER_PRECHG_TIME EQU 0 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  53. ADC_LIMIT_L EQU 85 ; Power supply measurement ADC value for which main motor power is limited (low byte)
  54. ADC_LIMIT_H EQU 0 ; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
  55. TEMP_LIMIT EQU 109 ; Temperature measurement ADC value for which main motor power is limited (low byte, assuming high byte is 1)
  56. TEMP_LIMIT_STEP EQU 4 ; Temperature measurement ADC value increment for which main motor power is further limited
  57. ;**** **** **** **** ****
  58. ; ESC specific defaults
  59. ;**** **** **** **** ****
  60. DEFAULT_PGM_MAIN_SPOOLUP_TIME EQU 10 ; Main motor spoolup time
  61. DEFAULT_PGM_MAIN_STARTUP_PWR EQU 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  62. DEFAULT_PGM_TAIL_STARTUP_PWR EQU 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  63. DEFAULT_PGM_MULTI_STARTUP_PWR EQU 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  64. ;**** **** **** **** ****
  65. ; Bootloader definitions
  66. ;**** **** **** **** ****
  67. RTX_PORT EQU P0 ; Receive/Transmit port
  68. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  69. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  70. RTX_PIN EQU 5 ; RTX pin
  71. SIGNATURE_001 EQU 0f3h ; Device signature
  72. SIGNATURE_002 EQU 030h
  73. ;*********************
  74. ; PORT 0 definitions *
  75. ;*********************
  76. ; EQU 7 ;i
  77. Mux_C EQU 6 ;i
  78. Rcp_In EQU 5 ;i
  79. ; EQU 4 ;i
  80. Comp_Com EQU 3 ;i
  81. Mux_B EQU 2 ;i
  82. ; EQU 1 ;i
  83. Mux_A EQU 0 ;i
  84. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  85. P0_INIT EQU 0FFh
  86. P0_PUSHPULL EQU 0
  87. P0_SKIP EQU NOT(1 SHL Rcp_In)
  88. MACRO Get_Rcp_Capture_Values
  89. mov Temp1, PCA0CPL0 ; Get PCA capture values
  90. mov Temp2, PCA0CPH0
  91. ENDM
  92. MACRO Read_Rcp_Int
  93. mov A, P0
  94. jnb Flags3.PGM_RCP_PWM_POL, ($+4) ; Is pwm polarity negative?
  95. cpl A ; Yes - invert
  96. ENDM
  97. MACRO Rcp_Int_Enable
  98. orl PCA0CPM0, #01h ; Interrupt enabled
  99. ENDM
  100. MACRO Rcp_Int_Disable
  101. anl PCA0CPM0, #0FEh ; Interrupt disabled
  102. ENDM
  103. MACRO Rcp_Int_First
  104. anl PCA0CPM0, #0CFh
  105. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  106. orl PCA0CPM0, #20h ; Capture rising edge
  107. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  108. orl PCA0CPM0, #10h ; Capture falling edge
  109. ENDM
  110. MACRO Rcp_Int_Second
  111. anl PCA0CPM0, #0CFh
  112. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  113. orl PCA0CPM0, #10h ; Capture falling edge
  114. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  115. orl PCA0CPM0, #20h ; Capture rising edge
  116. ENDM
  117. MACRO Rcp_Clear_Int_Flag
  118. clr CCF0 ; Clear interrupt flag
  119. ENDM
  120. ;*********************
  121. ; PORT 1 definitions *
  122. ;*********************
  123. BnFET EQU 7 ;o
  124. BpFET EQU 6 ;o
  125. AnFET EQU 5 ;o
  126. ApFET EQU 4 ;o
  127. CnFET EQU 3 ;o
  128. CpFET EQU 2 ;o
  129. ; EQU 1 ;i
  130. Adc_Ip EQU 0 ;i
  131. P1_DIGITAL EQU NOT(1 SHL Adc_Ip)
  132. P1_INIT EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL Adc_Ip) ; Setting nFET outputs turn them off. Setting ADC ip sets it tristate
  133. P1_PUSHPULL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  134. P1_SKIP EQU (1 SHL Adc_Ip)
  135. MACRO AnFET_on
  136. mov A, Current_Pwm_Limited
  137. jz ($+12)
  138. jb Flags3.PGM_DIR_REV, ($+5)
  139. clr P1.AnFET
  140. jnb Flags3.PGM_DIR_REV, ($+5)
  141. clr P1.CnFET
  142. ENDM
  143. MACRO AnFET_off
  144. jb Flags3.PGM_DIR_REV, ($+5)
  145. setb P1.AnFET
  146. jnb Flags3.PGM_DIR_REV, ($+5)
  147. setb P1.CnFET
  148. ENDM
  149. MACRO CnFET_on
  150. mov A, Current_Pwm_Limited
  151. jz ($+12)
  152. jb Flags3.PGM_DIR_REV, ($+5)
  153. clr P1.CnFET
  154. jnb Flags3.PGM_DIR_REV, ($+5)
  155. clr P1.AnFET
  156. ENDM
  157. MACRO CnFET_off
  158. jb Flags3.PGM_DIR_REV, ($+5)
  159. setb P1.CnFET
  160. jnb Flags3.PGM_DIR_REV, ($+5)
  161. setb P1.AnFET
  162. ENDM
  163. MACRO BnFET_on
  164. mov A, Current_Pwm_Limited
  165. jz ($+4)
  166. clr P1.BnFET
  167. ENDM
  168. MACRO BnFET_off
  169. setb P1.BnFET
  170. ENDM
  171. MACRO All_nFETs_Off
  172. setb P1.AnFET
  173. setb P1.CnFET
  174. setb P1.BnFET
  175. ENDM
  176. MACRO ApFET_on
  177. jb Flags3.PGM_DIR_REV, ($+5)
  178. setb P1.ApFET
  179. jnb Flags3.PGM_DIR_REV, ($+5)
  180. setb P1.CpFET
  181. ENDM
  182. MACRO ApFET_off
  183. jb Flags3.PGM_DIR_REV, ($+5)
  184. clr P1.ApFET
  185. jnb Flags3.PGM_DIR_REV, ($+5)
  186. clr P1.CpFET
  187. ENDM
  188. MACRO CpFET_on
  189. jb Flags3.PGM_DIR_REV, ($+5)
  190. setb P1.CpFET
  191. jnb Flags3.PGM_DIR_REV, ($+5)
  192. setb P1.ApFET
  193. ENDM
  194. MACRO CpFET_off
  195. jb Flags3.PGM_DIR_REV, ($+5)
  196. clr P1.CpFET
  197. jnb Flags3.PGM_DIR_REV, ($+5)
  198. clr P1.ApFET
  199. ENDM
  200. MACRO BpFET_on
  201. setb P1.BpFET
  202. ENDM
  203. MACRO BpFET_off
  204. clr P1.BpFET
  205. ENDM
  206. MACRO All_pFETs_Off
  207. clr P1.ApFET
  208. clr P1.CpFET
  209. clr P1.BpFET
  210. ENDM
  211. MACRO All_pFETs_On
  212. setb P1.ApFET
  213. setb P1.CpFET
  214. setb P1.BpFET
  215. ENDM
  216. MACRO Set_Comp_Phase_A
  217. jb Flags3.PGM_DIR_REV, ($+6)
  218. mov CPT0MX, #10h ; Set comparator multiplexer to phase A
  219. jnb Flags3.PGM_DIR_REV, ($+6)
  220. mov CPT0MX, #13h
  221. ENDM
  222. MACRO Set_Comp_Phase_C
  223. jb Flags3.PGM_DIR_REV, ($+6)
  224. mov CPT0MX, #13h ; Set comparator multiplexer to phase C
  225. jnb Flags3.PGM_DIR_REV, ($+6)
  226. mov CPT0MX, #10h
  227. ENDM
  228. MACRO Set_Comp_Phase_B
  229. mov CPT0MX, #11h ; Set comparator multiplexer to phase B
  230. ENDM
  231. MACRO Read_Comp_Out
  232. mov A, CPT0CN ; Read comparator output
  233. ENDM
  234. ;*********************
  235. ; PORT 2 definitions *
  236. ;*********************
  237. DebugPin EQU 0 ;o
  238. P2_PUSHPULL EQU (1 SHL DebugPin)
  239. ;**********************
  240. ; MCU specific macros *
  241. ;**********************
  242. MACRO Interrupt_Table_Definition
  243. CSEG AT 0 ; Code segment start
  244. jmp reset
  245. CSEG AT 0Bh ; Timer0 interrupt
  246. jmp t0_int
  247. CSEG AT 2Bh ; Timer2 interrupt
  248. jmp t2_int
  249. CSEG AT 5Bh ; PCA interrupt
  250. jmp pca_int
  251. CSEG AT 73h ; Timer3 interrupt
  252. jmp t3_int
  253. ENDM
  254. MACRO Initialize_Xbar
  255. mov XBR1, #41h ; Xbar enabled, CEX0 routed to pin Rcp_In
  256. ENDM
  257. MACRO Initialize_Adc
  258. mov REF0CN, #0Eh ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  259. mov ADC0CF, #58h ; ADC clock 2MHz
  260. mov AMX0P, #(8+Adc_Ip) ; Select positive input
  261. mov AMX0N, #11h ; Select negative input as ground
  262. mov ADC0CN, #80h ; ADC enabled
  263. ENDM
  264. MACRO Set_Adc_Ip_Volt
  265. mov AMX0P, #(8+Adc_Ip) ; Select positive input
  266. ENDM
  267. MACRO Set_Adc_Ip_Temp
  268. mov AMX0P, #10h ; Select temp sensor input
  269. ENDM
  270. MACRO Start_Adc
  271. mov ADC0CN, #90h ; ADC start
  272. ENDM
  273. MACRO Get_Adc_Status
  274. mov A, ADC0CN
  275. ENDM
  276. MACRO Read_Adc_Result
  277. mov Temp1, ADC0L
  278. mov Temp2, ADC0H
  279. ENDM
  280. MACRO Stop_Adc
  281. ENDM
  282. MACRO Set_RPM_Out
  283. ENDM
  284. MACRO Clear_RPM_Out
  285. ENDM
  286. MACRO Set_MCU_Clk_25MHz
  287. ENDM
  288. MACRO Set_MCU_Clk_50MHz
  289. ENDM