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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Polaris Thunder 100A hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device SiLabs F330
  30. ;*********************
  31. $include (c8051f330.inc)
  32. ;**** **** **** **** ****
  33. ; Uses internal calibrated oscillator set to 24Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. CSEG AT 1A40h
  39. Eep_ESC_Layout: DB "#PolarisTdr100A#" ; ESC layout tag
  40. CSEG AT 1A50h
  41. Eep_ESC_MCU: DB "#BLHELI#F330# " ; Project and MCU tag (16 Bytes)
  42. MCU_50MHZ EQU 0 ; Set to 1 if MCU can run at 50MHz
  43. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  44. PORT3_EXIST EQU 0 ; Set to 1 if MCU has port3
  45. COMP1_USED EQU 0 ; Set to 1 if MCU has comparator 1 and it is being used
  46. LOCK_BYTE_ADDRESS_16K EQU 3FFFh ; Address of lock byte if 16k flash size
  47. LOCK_BYTE_ADDRESS_8K EQU 1DFFh ; Address of lock byte if 8k flash size
  48. HIGH_BEC_VOLTAGE EQU 0 ; Set to 1 or more if high BEC voltage is supported
  49. DAMPED_MODE_ENABLE EQU 0 ; Damped mode disabled
  50. NFETON_DELAY EQU 6 ; Wait delay from pfets off to nfets on
  51. PFETON_DELAY EQU 6 ; Wait delay from nfets off to pfets on
  52. HIGH_DRIVER_PRECHG_TIME EQU 0 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  53. ADC_LIMIT_L EQU 48 ; Power supply measurement ADC value for which main motor power is limited (low byte)
  54. ADC_LIMIT_H EQU 0 ; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
  55. TEMP_LIMIT EQU 109 ; Temperature measurement ADC value for which main motor power is limited (low byte, assuming high byte is 1)
  56. TEMP_LIMIT_STEP EQU 4 ; Temperature measurement ADC value increment for which main motor power is further limited
  57. ;**** **** **** **** ****
  58. ; ESC specific defaults
  59. ;**** **** **** **** ****
  60. DEFAULT_PGM_MAIN_SPOOLUP_TIME EQU 16 ; Main motor spoolup time
  61. DEFAULT_PGM_MAIN_STARTUP_PWR EQU 8 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  62. DEFAULT_PGM_TAIL_STARTUP_PWR EQU 8 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  63. DEFAULT_PGM_MULTI_STARTUP_PWR EQU 8 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  64. ;**** **** **** **** ****
  65. ; Bootloader definitions
  66. ;**** **** **** **** ****
  67. RTX_PORT EQU P0 ; Receive/Transmit port
  68. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  69. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  70. RTX_PIN EQU 7 ; RTX pin
  71. SIGNATURE_001 EQU 0f3h ; Device signature
  72. SIGNATURE_002 EQU 030h
  73. ;*********************
  74. ; PORT 0 definitions *
  75. ;*********************
  76. Rcp_In EQU 7 ;i
  77. Adc_Ip EQU 6 ;i
  78. Mux_C EQU 5 ;i
  79. ; EQU 4 ;i
  80. Mux_B EQU 3 ;i
  81. Comp_Com EQU 2 ;i
  82. Mux_A EQU 1 ;i
  83. ; EQU 0 ;i
  84. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)+(1 SHL Adc_Ip)) AND 0FFh
  85. P0_INIT EQU 0FFh
  86. P0_PUSHPULL EQU 00h
  87. P0_SKIP EQU NOT(1 SHL Rcp_In) AND 0FFh
  88. MACRO Get_Rcp_Capture_Values
  89. mov Temp1, PCA0CPL0 ; Get PCA capture values
  90. mov Temp2, PCA0CPH0
  91. ENDM
  92. MACRO Read_Rcp_Int
  93. mov A, P0
  94. jnb Flags3.PGM_RCP_PWM_POL, ($+4) ; Is pwm polarity negative?
  95. cpl A ; Yes - invert
  96. ENDM
  97. MACRO Rcp_Int_Enable
  98. orl PCA0CPM0, #01h ; Interrupt enabled
  99. ENDM
  100. MACRO Rcp_Int_Disable
  101. anl PCA0CPM0, #0FEh ; Interrupt disabled
  102. ENDM
  103. MACRO Rcp_Int_First
  104. anl PCA0CPM0, #0CFh
  105. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  106. orl PCA0CPM0, #20h ; Capture rising edge
  107. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  108. orl PCA0CPM0, #10h ; Capture falling edge
  109. ENDM
  110. MACRO Rcp_Int_Second
  111. anl PCA0CPM0, #0CFh
  112. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  113. orl PCA0CPM0, #10h ; Capture falling edge
  114. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  115. orl PCA0CPM0, #20h ; Capture rising edge
  116. ENDM
  117. MACRO Rcp_Clear_Int_Flag
  118. clr CCF0 ; Clear interrupt flag
  119. ENDM
  120. ;*********************
  121. ; PORT 1 definitions *
  122. ;*********************
  123. ; EQU 7 ;i
  124. ; EQU 6 ;i
  125. CpFET EQU 5 ;o
  126. BpFET EQU 4 ;o
  127. ApFET EQU 3 ;o
  128. CnFET EQU 2 ;o
  129. BnFET EQU 1 ;o
  130. AnFET EQU 0 ;o
  131. P1_DIGITAL EQU 0FFh
  132. P1_INIT EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET) ; Setting nFET outputs turn them off
  133. P1_PUSHPULL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  134. P1_SKIP EQU 0
  135. MACRO AnFET_on
  136. mov A, Current_Pwm_Limited
  137. jz ($+12)
  138. jb Flags3.PGM_DIR_REV, ($+5)
  139. clr P1.AnFET
  140. jnb Flags3.PGM_DIR_REV, ($+5)
  141. clr P1.CnFET
  142. ENDM
  143. MACRO AnFET_off
  144. jb Flags3.PGM_DIR_REV, ($+5)
  145. setb P1.AnFET
  146. jnb Flags3.PGM_DIR_REV, ($+5)
  147. setb P1.CnFET
  148. ENDM
  149. MACRO BnFET_on
  150. mov A, Current_Pwm_Limited
  151. jz ($+4)
  152. clr P1.BnFET
  153. ENDM
  154. MACRO BnFET_off
  155. setb P1.BnFET
  156. ENDM
  157. MACRO CnFET_on
  158. mov A, Current_Pwm_Limited
  159. jz ($+12)
  160. jb Flags3.PGM_DIR_REV, ($+5)
  161. clr P1.CnFET
  162. jnb Flags3.PGM_DIR_REV, ($+5)
  163. clr P1.AnFET
  164. ENDM
  165. MACRO CnFET_off
  166. jb Flags3.PGM_DIR_REV, ($+5)
  167. setb P1.CnFET
  168. jnb Flags3.PGM_DIR_REV, ($+5)
  169. setb P1.AnFET
  170. ENDM
  171. MACRO All_nFETs_Off
  172. setb P1.AnFET
  173. setb P1.BnFET
  174. setb P1.CnFET
  175. ENDM
  176. MACRO ApFET_on
  177. jb Flags3.PGM_DIR_REV, ($+5)
  178. setb P1.ApFET
  179. jnb Flags3.PGM_DIR_REV, ($+5)
  180. setb P1.CpFET
  181. ENDM
  182. MACRO ApFET_off
  183. jb Flags3.PGM_DIR_REV, ($+5)
  184. clr P1.ApFET
  185. jnb Flags3.PGM_DIR_REV, ($+5)
  186. clr P1.CpFET
  187. ENDM
  188. MACRO BpFET_on
  189. setb P1.BpFET
  190. ENDM
  191. MACRO BpFET_off
  192. clr P1.BpFET
  193. ENDM
  194. MACRO CpFET_on
  195. jb Flags3.PGM_DIR_REV, ($+5)
  196. setb P1.CpFET
  197. jnb Flags3.PGM_DIR_REV, ($+5)
  198. setb P1.ApFET
  199. ENDM
  200. MACRO CpFET_off
  201. jb Flags3.PGM_DIR_REV, ($+5)
  202. clr P1.CpFET
  203. jnb Flags3.PGM_DIR_REV, ($+5)
  204. clr P1.ApFET
  205. ENDM
  206. MACRO All_pFETs_Off
  207. clr P1.ApFET
  208. clr P1.BpFET
  209. clr P1.CpFET
  210. ENDM
  211. MACRO All_pFETs_On
  212. setb P1.ApFET
  213. setb P1.BpFET
  214. setb P1.CpFET
  215. ENDM
  216. MACRO Set_Comp_Phase_A
  217. jb Flags3.PGM_DIR_REV, ($+6)
  218. mov CPT0MX, #01h ; Set comparator multiplexer to phase A
  219. jnb Flags3.PGM_DIR_REV, ($+6)
  220. mov CPT0MX, #21h
  221. ENDM
  222. MACRO Set_Comp_Phase_B
  223. mov CPT0MX, #11h ; Set comparator multiplexer to phase B
  224. ENDM
  225. MACRO Set_Comp_Phase_C
  226. jb Flags3.PGM_DIR_REV, ($+6)
  227. mov CPT0MX, #21h ; Set comparator multiplexer to phase C
  228. jnb Flags3.PGM_DIR_REV, ($+6)
  229. mov CPT0MX, #01h
  230. ENDM
  231. MACRO Read_Comp_Out
  232. mov A, CPT0CN ; Read comparator output
  233. cpl A ; Invert output
  234. ENDM
  235. ;*********************
  236. ; PORT 2 definitions *
  237. ;*********************
  238. DebugPin EQU 0 ;o
  239. P2_PUSHPULL EQU (1 SHL DebugPin)
  240. ;**********************
  241. ; MCU specific macros *
  242. ;**********************
  243. MACRO Interrupt_Table_Definition
  244. CSEG AT 0 ; Code segment start
  245. jmp reset
  246. CSEG AT 0Bh ; Timer0 interrupt
  247. jmp t0_int
  248. CSEG AT 2Bh ; Timer2 interrupt
  249. jmp t2_int
  250. CSEG AT 5Bh ; PCA interrupt
  251. jmp pca_int
  252. CSEG AT 73h ; Timer3 interrupt
  253. jmp t3_int
  254. ENDM
  255. MACRO Initialize_Xbar
  256. mov XBR1, #41h ; Xbar enabled, CEX0 routed to pin Rcp_In
  257. ENDM
  258. MACRO Initialize_Adc
  259. mov REF0CN, #0Eh ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  260. mov ADC0CF, #58h ; ADC clock 2MHz
  261. mov AMX0P, #Adc_Ip ; Select positive input
  262. mov AMX0N, #11h ; Select negative input as ground
  263. mov ADC0CN, #80h ; ADC enabled
  264. ENDM
  265. MACRO Set_Adc_Ip_Volt
  266. mov AMX0P, #Adc_Ip ; Select positive input
  267. ENDM
  268. MACRO Set_Adc_Ip_Temp
  269. mov AMX0P, #10h ; Select temp sensor input
  270. ENDM
  271. MACRO Start_Adc
  272. mov ADC0CN, #90h ; ADC start
  273. ENDM
  274. MACRO Get_Adc_Status
  275. mov A, ADC0CN
  276. ENDM
  277. MACRO Read_Adc_Result
  278. mov Temp1, ADC0L
  279. mov Temp2, ADC0H
  280. ENDM
  281. MACRO Stop_Adc
  282. ENDM
  283. MACRO Set_RPM_Out
  284. ENDM
  285. MACRO Clear_RPM_Out
  286. ENDM
  287. MACRO Set_MCU_Clk_25MHz
  288. ENDM
  289. MACRO Set_MCU_Clk_50MHz
  290. ENDM