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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; FVT_20A hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device SiLabs F330
  30. ;*********************
  31. $include (c8051f330.inc)
  32. ;**** **** **** **** ****
  33. ; Uses internal calibrated oscillator set to 24Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. CSEG AT 1A40h
  39. Eep_ESC_Layout: DB "#Skywalker20A# " ; ESC layout tag
  40. CSEG AT 1A50h
  41. Eep_ESC_MCU: DB "#BLHELI#F330# " ; Project and MCU tag (16 Bytes)
  42. MCU_50MHZ EQU 0 ; Set to 1 if MCU can run at 50MHz
  43. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  44. PORT3_EXIST EQU 0 ; Set to 1 if MCU has port3
  45. COMP1_USED EQU 0 ; Set to 1 if MCU has comparator 1 and it is being used
  46. LOCK_BYTE_ADDRESS_16K EQU 3FFFh ; Address of lock byte if 16k flash size
  47. LOCK_BYTE_ADDRESS_8K EQU 1DFFh ; Address of lock byte if 8k flash size
  48. HIGH_BEC_VOLTAGE EQU 0 ; Set to 1 or more if high BEC voltage is supported
  49. DAMPED_MODE_ENABLE EQU 1 ; Damped mode enabled
  50. NFETON_DELAY EQU 6 ; Wait delay from pfets off to nfets on
  51. PFETON_DELAY EQU 6 ; Wait delay from nfets off to pfets on
  52. HIGH_DRIVER_PRECHG_TIME EQU 15 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  53. ADC_LIMIT_L EQU 85 ; Power supply measurement ADC value for which main motor power is limited (low byte)
  54. ADC_LIMIT_H EQU 0 ; Power supply measurement ADC value for which main motor power is limited (2 msbs)
  55. TEMP_LIMIT EQU 109 ; Temperature measurement ADC value for which main motor power is limited (low byte, assuming high byte is 1)
  56. TEMP_LIMIT_STEP EQU 4 ; Temperature measurement ADC value increment for which main motor power is further limited
  57. BAT_CELLS EQU 7
  58. ;**** **** **** **** ****
  59. ; ESC specific defaults
  60. ;**** **** **** **** ****
  61. DEFAULT_PGM_MAIN_SPOOLUP_TIME EQU 10 ; Main motor spoolup time
  62. DEFAULT_PGM_MAIN_STARTUP_PWR EQU 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  63. DEFAULT_PGM_TAIL_STARTUP_PWR EQU 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  64. DEFAULT_PGM_MULTI_STARTUP_PWR EQU 10 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  65. ;**** **** **** **** ****
  66. ; Bootloader definitions
  67. ;**** **** **** **** ****
  68. RTX_PORT EQU P0 ; Receive/Transmit port
  69. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  70. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  71. RTX_PIN EQU 5 ; RTX pin
  72. SIGNATURE_001 EQU 0f3h ; Device signature
  73. SIGNATURE_002 EQU 030h
  74. ;*********************
  75. ; PORT 0 definitions *
  76. ;*********************
  77. ; EQU 7 ;i
  78. Mux_C EQU 6 ;i
  79. Rcp_In EQU 5 ;i
  80. ; EQU 4 ;i
  81. Comp_Com EQU 3 ;i
  82. Mux_A EQU 2 ;i
  83. ; EQU 1 ;i
  84. Mux_B EQU 0 ;i
  85. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  86. P0_INIT EQU 0FFh
  87. P0_PUSHPULL EQU 0
  88. P0_SKIP EQU NOT(1 SHL Rcp_In) AND 0FFh
  89. Get_Rcp_Capture_Values MACRO
  90. mov Temp1, PCA0CPL0 ; Get PCA capture values
  91. mov Temp2, PCA0CPH0
  92. ENDM
  93. Read_Rcp_Int MACRO
  94. mov A, P0
  95. jnb Flags3.PGM_RCP_PWM_POL, ($+4) ; Is pwm polarity negative?
  96. cpl A ; Yes - invert
  97. ENDM
  98. Rcp_Int_Enable MACRO
  99. orl PCA0CPM0, #01h ; Interrupt enabled
  100. ENDM
  101. Rcp_Int_Disable MACRO
  102. anl PCA0CPM0, #0FEh ; Interrupt disabled
  103. ENDM
  104. Rcp_Int_First MACRO
  105. anl PCA0CPM0, #0CFh ; disable P,N edage capture function
  106. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  107. orl PCA0CPM0, #20h ; Capture rising edge
  108. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  109. orl PCA0CPM0, #10h ; Capture falling edge
  110. ENDM
  111. Rcp_Int_Second MACRO
  112. anl PCA0CPM0, #0CFh
  113. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  114. orl PCA0CPM0, #10h ; Capture falling edge
  115. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  116. orl PCA0CPM0, #20h ; Capture rising edge
  117. ENDM
  118. Rcp_Clear_Int_Flag MACRO
  119. clr CCF0 ; Clear interrupt flag
  120. ENDM
  121. ;*********************
  122. ; PORT 1 definitions *
  123. ;*********************
  124. AnFET EQU 7 ;o
  125. ApFET EQU 6 ;o
  126. BnFET EQU 5 ;o
  127. BpFET EQU 4 ;o
  128. CnFET EQU 3 ;o
  129. CpFET EQU 2 ;o
  130. ; EQU 1 ;i
  131. Adc_Ip EQU 0 ;i
  132. P1_DIGITAL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  133. P1_INIT EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL Adc_Ip) ; Setting nFET outputs turn them off
  134. P1_PUSHPULL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  135. P1_SKIP EQU (1 SHL Adc_Ip)
  136. AnFET_on MACRO
  137. mov A, Current_Pwm_Limited
  138. jz ($+12)
  139. jb Flags3.PGM_DIR_REV, ($+5)
  140. clr P1.AnFET
  141. jnb Flags3.PGM_DIR_REV, ($+5)
  142. clr P1.CnFET
  143. ENDM
  144. AnFET_off MACRO
  145. jb Flags3.PGM_DIR_REV, ($+5)
  146. setb P1.AnFET
  147. jnb Flags3.PGM_DIR_REV, ($+5)
  148. setb P1.CnFET
  149. ENDM
  150. BnFET_on MACRO
  151. mov A, Current_Pwm_Limited
  152. jz ($+4)
  153. clr P1.BnFET
  154. ENDM
  155. BnFET_off MACRO
  156. setb P1.BnFET
  157. ENDM
  158. CnFET_on MACRO
  159. mov A, Current_Pwm_Limited
  160. jz ($+12)
  161. jb Flags3.PGM_DIR_REV, ($+5)
  162. clr P1.CnFET
  163. jnb Flags3.PGM_DIR_REV, ($+5)
  164. clr P1.AnFET
  165. ENDM
  166. CnFET_off MACRO
  167. jb Flags3.PGM_DIR_REV, ($+5)
  168. setb P1.CnFET
  169. jnb Flags3.PGM_DIR_REV, ($+5)
  170. setb P1.AnFET
  171. ENDM
  172. All_nFETs_Off MACRO
  173. setb P1.AnFET
  174. setb P1.BnFET
  175. setb P1.CnFET
  176. ENDM
  177. ApFET_on MACRO
  178. jb Flags3.PGM_DIR_REV, ($+5)
  179. setb P1.ApFET
  180. jnb Flags3.PGM_DIR_REV, ($+5)
  181. setb P1.CpFET
  182. ENDM
  183. ApFET_off MACRO
  184. jb Flags3.PGM_DIR_REV, ($+5)
  185. clr P1.ApFET
  186. jnb Flags3.PGM_DIR_REV, ($+5)
  187. clr P1.CpFET
  188. ENDM
  189. BpFET_on MACRO
  190. setb P1.BpFET
  191. ENDM
  192. BpFET_off MACRO
  193. clr P1.BpFET
  194. ENDM
  195. CpFET_on MACRO
  196. jb Flags3.PGM_DIR_REV, ($+5)
  197. setb P1.CpFET
  198. jnb Flags3.PGM_DIR_REV, ($+5)
  199. setb P1.ApFET
  200. ENDM
  201. CpFET_off MACRO
  202. jb Flags3.PGM_DIR_REV, ($+5)
  203. clr P1.CpFET
  204. jnb Flags3.PGM_DIR_REV, ($+5)
  205. clr P1.ApFET
  206. ENDM
  207. All_pFETs_Off MACRO
  208. clr P1.ApFET
  209. clr P1.BpFET
  210. clr P1.CpFET
  211. ENDM
  212. All_pFETs_On MACRO
  213. setb P1.ApFET
  214. setb P1.BpFET
  215. setb P1.CpFET
  216. ENDM
  217. Set_Comp_Phase_A MACRO
  218. jb Flags3.PGM_DIR_REV, ($+6)
  219. mov CPT0MX, #11h ; Set comparator multiplexer to phase A
  220. jnb Flags3.PGM_DIR_REV, ($+6)
  221. mov CPT0MX, #13h
  222. ENDM
  223. Set_Comp_Phase_B MACRO
  224. mov CPT0MX, #10h ; Set comparator multiplexer to phase B
  225. ENDM
  226. Set_Comp_Phase_C MACRO
  227. jb Flags3.PGM_DIR_REV, ($+6)
  228. mov CPT0MX, #13h ; Set comparator multiplexer to phase C
  229. jnb Flags3.PGM_DIR_REV, ($+6)
  230. mov CPT0MX, #11h
  231. ENDM
  232. Read_Comp_Out MACRO
  233. mov A, CPT0CN ; Read comparator output
  234. ENDM
  235. ;*********************
  236. ; PORT 2 definitions *
  237. ;*********************
  238. DebugPin EQU 0 ;o
  239. P2_PUSHPULL EQU (1 SHL DebugPin)
  240. ;**********************
  241. ; MCU specific macros *
  242. ;**********************
  243. Interrupt_Table_Definition MACRO
  244. CSEG AT 0 ; Code segment start
  245. jmp reset
  246. CSEG AT 0Bh ; Timer0 interrupt
  247. jmp t0_int
  248. CSEG AT 2Bh ; Timer2 interrupt
  249. jmp t2_int
  250. CSEG AT 5Bh ; PCA interrupt
  251. jmp pca_int
  252. CSEG AT 73h ; Timer3 interrupt
  253. jmp t3_int
  254. ENDM
  255. Initialize_Xbar MACRO
  256. mov XBR1, #41h ; Xbar enabled, CEX0 routed to pin Rcp_In
  257. ENDM
  258. Initialize_Adc MACRO
  259. mov REF0CN, #0Eh ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  260. mov ADC0CF, #58h ; ADC clock 2MHz
  261. mov AMX0P, #(8+Adc_Ip) ; Select positive input
  262. mov AMX0N, #11h ; Select negative input as ground
  263. mov ADC0CN, #80h ; ADC enabled
  264. ENDM
  265. Set_Adc_Ip_Volt MACRO
  266. mov AMX0P, #(8+Adc_Ip) ; Select positive input
  267. ENDM
  268. Set_Adc_Ip_Temp MACRO
  269. mov AMX0P, #10h ; Select temp sensor input
  270. ENDM
  271. Start_Adc MACRO
  272. mov ADC0CN, #90h ; ADC start
  273. ENDM
  274. Get_Adc_Status MACRO
  275. mov A, ADC0CN
  276. ENDM
  277. Read_Adc_Result MACRO
  278. mov Temp1, ADC0L
  279. mov Temp2, ADC0H
  280. ENDM
  281. Stop_Adc MACRO
  282. ENDM
  283. Set_RPM_Out MACRO
  284. ENDM
  285. Clear_RPM_Out MACRO
  286. ENDM
  287. Set_MCU_Clk_25MHz MACRO
  288. ENDM
  289. Set_MCU_Clk_50MHz MACRO
  290. ENDM