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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; YEP 7A hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device Atmega168PA
  30. ;*********************
  31. .INCLUDE "m168PAdef.inc"
  32. ;**** **** **** **** ****
  33. ; Fuses must be set to external oscillator = 16Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. .ESEG ; EEprom segment
  39. .ORG 0x40
  40. Eep_ESC_Layout: .DB "#YEP_7A# " ; ESC layout tag
  41. .ORG 0x50
  42. Eep_ESC_MCU: .DB "#BLHELI#Am168PA#" ; Project and MCU tag (16 Bytes)
  43. .EQU HIGH_BEC_VOLTAGE = 0 ; Set to 1 or more if high BEC voltage is supported
  44. .EQU DAMPED_MODE_ENABLE = 0 ; Set to 1 if fully damped mode is supported
  45. .EQU NFETON_DELAY = 65 ; Wait delay from pfets off to nfets on
  46. .EQU PFETON_DELAY = 5 ; Wait delay from nfets off to pfets on
  47. .EQU ADC_LIMIT_L = 231 ; 2k/22k divider. Power supply measurement ADC value for which motor power is limited (low byte)
  48. .EQU ADC_LIMIT_H = 0 ; 2k/22k divider. Power supply measurement ADC value for which motor power is limited (2 MSBs)
  49. .EQU TEMP_LIMIT = 0 ; No temp sensor. Temperature measurement ADC value for which main motor power is limited
  50. .EQU TEMP_LIMIT_STEP = 0 ; No temp sensor. Temperature measurement ADC value increment for which main motor power is further limited
  51. ;**** **** **** **** ****
  52. ; ESC specific defaults
  53. ;**** **** **** **** ****
  54. .EQU DEFAULT_PGM_MAIN_SPOOLUP_TIME = 7 ; Main motor spoolup time
  55. .EQU DEFAULT_PGM_MAIN_STARTUP_PWR = 11 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  56. .EQU DEFAULT_PGM_TAIL_STARTUP_PWR = 11 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  57. .EQU DEFAULT_PGM_MULTI_STARTUP_PWR = 11 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  58. .EQU DEFAULT_PGM_MAIN_STARTUP_METHOD = 2 ; 1=Stepped 2=Direct
  59. .EQU DEFAULT_PGM_TAIL_STARTUP_METHOD = 2 ; 1=Stepped 2=Direct
  60. .EQU DEFAULT_PGM_MULTI_STARTUP_METHOD = 2 ; 1=Stepped 2=Direct
  61. ;*********************
  62. ; PORT D definitions *
  63. ;*********************
  64. ;.EQU = 7 ;i
  65. ;.EQU = 6 ;i
  66. ;.EQU = 5 ;i
  67. ;.EQU = 4 ;i
  68. ;.EQU = 3 ;i
  69. .EQU Rcp_In = 2 ;i
  70. ;.EQU = 1 ;i
  71. ;.EQU = 0 ;i
  72. .equ INIT_PD = 0x00
  73. .equ DIR_PD = 0x00
  74. .MACRO Get_Rcp_Capture_Values
  75. lds @0, TCNT1L
  76. lds @1, TCNT1H
  77. .ENDMACRO
  78. .MACRO Read_Rcp_Int
  79. in @0, PIND
  80. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  81. com @0 ; Yes - invert
  82. .ENDMACRO
  83. .MACRO Get_Rcp_Int_Enable_State
  84. in @0, EIMSK ; Get int0 enable state (giving 0 is off, anything else is on)
  85. andi @0, (1<<INT0)
  86. .ENDMACRO
  87. .MACRO Rcp_Int_Enable
  88. ldi @0, (1<<INT0) ; Enable int0
  89. out EIMSK, @0
  90. .ENDMACRO
  91. .MACRO Rcp_Int_Disable
  92. ldi @0, 0 ; Disable int0
  93. out EIMSK, @0
  94. .ENDMACRO
  95. .MACRO Rcp_Int_First
  96. ldi @0, (1<<ISC01)+(1<<ISC00); Default - set next int0 to rising
  97. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  98. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  99. sts EICRA, @0
  100. .ENDMACRO
  101. .MACRO Rcp_Int_Second
  102. ldi @0, (1<<ISC01) ; Default - set next int0 to falling
  103. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  104. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  105. sts EICRA, @0
  106. .ENDMACRO
  107. .MACRO Rcp_Clear_Int_Flag
  108. clr @0
  109. sbr @0, (1<<INTF0) ; Clear ext0int flag
  110. out EIFR, @0
  111. .ENDMACRO
  112. .MACRO T0_Int_Disable
  113. lds @0, TIMSK0 ; Disable timer0 interrupts
  114. cbr @0, (1<<TOIE0)
  115. sts TIMSK0, @0
  116. .ENDMACRO
  117. .MACRO T0_Int_Enable
  118. lds @0, TIMSK0 ; Enable timer0 interrupts
  119. sbr @0, (1<<TOIE0)
  120. sts TIMSK0, @0
  121. .ENDMACRO
  122. .MACRO T1oca_Clear_Int_Flag
  123. ldi @0, (1<<OCF1A) ; Clear oc1a flag
  124. out TIFR1, @0
  125. .ENDMACRO
  126. .MACRO T1oca_Int_Disable
  127. lds @0, TIMSK1 ; Disable oc1a interrupts
  128. cbr @0, (1<<OCIE1A)
  129. sts TIMSK1, @0
  130. .ENDMACRO
  131. .MACRO T1oca_Int_Enable
  132. lds @0, TIMSK1 ; Enable oc1a interrupts
  133. sbr @0, (1<<OCIE1A)
  134. sts TIMSK1, @0
  135. .ENDMACRO
  136. .MACRO T2_Clear_Int_Flag
  137. clr @0
  138. sbr @0, (1<<TOV2) ; Clear tov2 flag
  139. out TIFR2, @0
  140. .ENDMACRO
  141. ;*********************
  142. ; PORT C definitions *
  143. ;*********************
  144. ;.EQU = 7 ; i
  145. ;.EQU = 6 ; i
  146. .EQU Mux_A = 5 ; i
  147. .EQU Mux_B = 4 ; i
  148. .EQU Mux_C = 3 ; i
  149. ;.EQU = 2 ; i
  150. ;.EQU = 1 ; i
  151. .EQU Volt_Ip = 0 ; i
  152. .equ INIT_PC = 0x00
  153. .equ DIR_PC = 0x00
  154. .MACRO AnFET_on
  155. sbi PORTB, AnFET
  156. .ENDMACRO
  157. .MACRO AnFET_off
  158. cbi PORTB, AnFET
  159. .ENDMACRO
  160. .MACRO BnFET_on
  161. sbi PORTB, BnFET
  162. .ENDMACRO
  163. .MACRO BnFET_off
  164. cbi PORTB, BnFET
  165. .ENDMACRO
  166. .MACRO CnFET_on
  167. sbi PORTB, CnFET
  168. .ENDMACRO
  169. .MACRO CnFET_off
  170. cbi PORTB, CnFET
  171. .ENDMACRO
  172. .MACRO All_nFETs_Off
  173. cbi PORTB, AnFET
  174. cbi PORTB, BnFET
  175. cbi PORTB, CnFET
  176. .ENDMACRO
  177. .MACRO ApFET_on
  178. sbi PORTB, ApFET
  179. .ENDMACRO
  180. .MACRO ApFET_off
  181. cbi PORTB, ApFET
  182. .ENDMACRO
  183. .MACRO BpFET_on
  184. sbi PORTB, BpFET
  185. .ENDMACRO
  186. .MACRO BpFET_off
  187. cbi PORTB, BpFET
  188. .ENDMACRO
  189. .MACRO CpFET_on
  190. sbi PORTB, CpFET
  191. .ENDMACRO
  192. .MACRO CpFET_off
  193. cbi PORTB, CpFET
  194. .ENDMACRO
  195. .MACRO All_pFETs_On
  196. sbi PORTB, ApFET
  197. sbi PORTB, BpFET
  198. sbi PORTB, CpFET
  199. .ENDMACRO
  200. .MACRO All_pFETs_Off
  201. cbi PORTB, ApFET
  202. cbi PORTB, BpFET
  203. cbi PORTB, CpFET
  204. .ENDMACRO
  205. .MACRO Damping_FET_On
  206. lds @0, DampingFET
  207. sbrc @0, 0
  208. sbi PORTB, ApFET
  209. sbrc @0, 1
  210. sbi PORTB, BpFET
  211. sbrc @0, 2
  212. sbi PORTB, CpFET
  213. .ENDM
  214. .MACRO Comp_Init
  215. lds @0, ADCSRB ; Toggle Analog Comparator Multiplexer Enable
  216. cbr @0, (1<<ACME)
  217. sts ADCSRB, @0
  218. Read_Comp_Out @0
  219. lds @0, ADCSRB
  220. sbr @0, (1<<ACME)
  221. sts ADCSRB, @0
  222. .ENDMACRO
  223. .MACRO Set_Comp_Phase_A
  224. ldi @0, Mux_A ; Set comparator multiplexer to phase A
  225. ori @0, (1<<REFS1)+(1<<REFS0)
  226. sts ADMUX, @0
  227. .ENDMACRO
  228. .MACRO Set_Comp_Phase_B
  229. ldi @0, Mux_B ; Set comparator multiplexer to phase B
  230. ori @0, (1<<REFS1)+(1<<REFS0)
  231. sts ADMUX, @0
  232. .ENDMACRO
  233. .MACRO Set_Comp_Phase_C
  234. ldi @0, Mux_C ; Set comparator multiplexer to phase C
  235. ori @0, (1<<REFS1)+(1<<REFS0)
  236. sts ADMUX, @0
  237. .ENDMACRO
  238. .MACRO Read_Comp_Out
  239. in @0, ACSR ; Read comparator output
  240. .ENDMACRO
  241. ;*********************
  242. ; PORT B definitions *
  243. ;*********************
  244. ;.EQU = 7 ; i
  245. ;.EQU = 6 ; i
  246. .EQU CnFET = 5 ; o
  247. .EQU BnFET = 4 ; o
  248. .EQU AnFET = 3 ; o
  249. .EQU ApFET = 2 ; o
  250. .EQU CpFET = 1 ; o
  251. .EQU BpFET = 0 ; o
  252. .EQU INIT_PB = 0
  253. .EQU DIR_PB = (1<<AnFET)+(1<<BnFET)+(1<<CnFET)+(1<<ApFET)+(1<<BpFET)+(1<<CpFET)
  254. ;**********************
  255. ; MCU specific macros *
  256. ;**********************
  257. .MACRO Interrupt_Table_Definition
  258. jmp reset
  259. rjmp rcp_int ; ext_int0
  260. nop
  261. nop ; ext_int1
  262. nop
  263. nop ; pci0_int
  264. nop
  265. nop ; pci1_int
  266. nop
  267. nop ; pci2_int
  268. nop
  269. nop ; wdt_int
  270. nop
  271. nop ; t2oca_int
  272. nop
  273. nop ; t2ocb_int
  274. nop
  275. rjmp t2_int ; t2ovfl_int
  276. nop
  277. nop ; icp1_int
  278. nop
  279. rjmp t1oca_int ; t1oca_int
  280. nop
  281. nop ; t1ocb_int
  282. nop
  283. nop ; t1ovfl_int
  284. nop
  285. nop ; t0oca_int
  286. nop
  287. nop ; t0ocb_int
  288. nop
  289. rjmp t0_int ; t0ovfl_int
  290. nop
  291. nop ; spi_int
  292. nop
  293. nop ; urxc
  294. nop
  295. nop ; udre
  296. nop
  297. nop ; utxc
  298. nop
  299. ; nop ; adc_int
  300. ; nop ; eep_int
  301. ; nop ; aci_int
  302. ; nop ; wire2_int
  303. ; nop ; spmc_int
  304. .ENDMACRO
  305. .MACRO Disable_Watchdog
  306. cli ; Disable interrupts
  307. wdr ; Reset watchdog timer
  308. in @0, MCUSR ; Clear WDRF in MCUSR
  309. andi @0, (0xFF & (0<<WDRF))
  310. out MCUSR, @0
  311. lds @0, WDTCSR ; Write logical one to WDCE and WDE
  312. ori @0, (1<<WDCE) | (1<<WDE)
  313. sts WDTCSR, @0
  314. ldi @0, (0<<WDE) ; Turn off WDT
  315. sts WDTCSR, @0
  316. .ENDMACRO
  317. .MACRO Enable_Watchdog
  318. ldi @0, (1<<WDE) ; Turn on WDT
  319. sts WDTCSR, @0
  320. .ENDMACRO
  321. .MACRO Initialize_MCU
  322. .ENDMACRO
  323. .MACRO Initialize_Interrupts
  324. ldi @0, (1<<TOIE0)
  325. out TIFR0, @0 ; Clear interrupts
  326. sts TIMSK0, @0 ; Enable interrupts
  327. ldi @0, (1<<OCIE1A)
  328. out TIFR1, @0 ; Clear interrupts
  329. sts TIMSK1, @0 ; Enable interrupts
  330. ldi @0, (1<<TOIE2)
  331. out TIFR2, @0 ; Clear interrupts
  332. sts TIMSK2, @0 ; Enable interrupts
  333. .ENDMACRO
  334. .MACRO Initialize_Adc
  335. ldi @0, Volt_Ip
  336. ori @0, (1<<REFS1)+(1<<REFS0)
  337. sts ADMUX, @0 ; Set ADMUX register
  338. lds @0, ADCSRA ; Set ADCSRA register (1MHz clock)
  339. sbr @0, (1<<ADPS2)
  340. sbr @0, (1<<ADEN) ; Enable ADC
  341. sts ADCSRA, @0
  342. .ENDMACRO
  343. .MACRO Set_Adc_Ip_Volt
  344. cbr Flags1, (1<<ADC_READ_TEMP)
  345. .ENDMACRO
  346. .MACRO Set_Adc_Ip_Temp
  347. sbr Flags1, (1<<ADC_READ_TEMP)
  348. .ENDMACRO
  349. .MACRO Start_Adc
  350. ldi @0, Volt_Ip
  351. sbrc Flags1, ADC_READ_TEMP
  352. ldi @0, Volt_Ip
  353. ori @0, (1<<REFS1)+(1<<REFS0)
  354. sts ADMUX, @0 ; Set ADMUX register (1.1V reference, selected input)
  355. lds @0, ADCSRA
  356. sbr @0, (1<<ADEN) ; Enable ADC
  357. sbr @0, (1<<ADSC) ; Start ADC conversion
  358. sts ADCSRA, @0
  359. .ENDMACRO
  360. .MACRO Get_Adc_Status
  361. lds @0, ADCSRA
  362. .ENDMACRO
  363. .MACRO Read_Adc_Result
  364. lds @0, ADCL
  365. lds @1, ADCH
  366. .ENDMACRO
  367. .MACRO Stop_Adc
  368. lds @0, ADCSRA
  369. cbr @0, (1<<ADEN) ; Disable ADC
  370. sts ADCSRA, @0
  371. .ENDMACRO
  372. .MACRO Set_Timer0_CS0
  373. out TCCR0B, @0
  374. .ENDMACRO
  375. .MACRO Set_Timer1_CS1
  376. sts TCCR1B, @0
  377. .ENDMACRO
  378. .MACRO Set_Timer2_CS2
  379. sts TCCR2B, @0
  380. .ENDMACRO
  381. .MACRO Read_TCNT1L
  382. lds @0, TCNT1L
  383. .ENDMACRO
  384. .MACRO Read_TCNT1H
  385. lds @0, TCNT1H
  386. .ENDMACRO
  387. .MACRO Set_OCR1AL
  388. sts OCR1AL, @0
  389. .ENDMACRO
  390. .MACRO Set_OCR1AH
  391. sts OCR1AH, @0
  392. .ENDMACRO
  393. .MACRO Read_TCNT2
  394. lds @0, TCNT2
  395. .ENDMACRO
  396. .MACRO Set_TCNT2
  397. sts TCNT2, @0
  398. .ENDMACRO
  399. .MACRO Check_Eeprom_Ready
  400. sbic EECR, EEPE
  401. .ENDMACRO
  402. .MACRO Set_Eeprom_Address
  403. out EEARL, @0
  404. out EEARH, @1
  405. .ENDMACRO
  406. .MACRO Start_Eeprom_Write
  407. sbi EECR, EEMPE
  408. sbi EECR, EEPE
  409. .ENDMACRO
  410. .MACRO Prepare_Lock_Or_Fuse_Read
  411. ldi @0, ((1<<BLBSET)+(1<<SELFPRGEN))
  412. out SPMCSR, @0
  413. .ENDMACRO
  414. .MACRO xcall
  415. call @0
  416. .ENDMACRO
  417. .MACRO Set_RPM_Out
  418. .ENDMACRO
  419. .MACRO Clear_RPM_Out
  420. .ENDMACRO