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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Turnigy K-Force 120A HV hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device SiLabs F310
  30. ;*********************
  31. $include (c8051f310.inc)
  32. ;**** **** **** **** ****
  33. ; Uses internal calibrated oscillator set to 24Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. CSEG AT 1A40h
  39. Eep_ESC_Layout: DB "#TgyKF120AHV# " ; ESC layout tag
  40. CSEG AT 1A50h
  41. Eep_ESC_MCU: DB "#BLHELI#F310# " ; Project and MCU tag (16 Bytes)
  42. MCU_50MHZ EQU 0 ; Set to 1 if MCU can run at 50MHz
  43. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  44. PORT3_EXIST EQU 1 ; Set to 1 if MCU has port3
  45. COMP1_USED EQU 1 ; Set to 1 if MCU has comparator 1 and it is being used
  46. LOCK_BYTE_ADDRESS_16K EQU 3DFFh ; Address of lock byte if 16k flash size
  47. LOCK_BYTE_ADDRESS_8K EQU 1FFFh ; Address of lock byte if 8k flash size
  48. HIGH_BEC_VOLTAGE EQU 0 ; Set to 1 or more if high BEC voltage is supported
  49. DAMPED_MODE_ENABLE EQU 0 ; Damped mode disabled
  50. NFETON_DELAY EQU 10 ; Wait delay from pfets off to nfets on
  51. PFETON_DELAY EQU 10 ; Wait delay from nfets off to pfets on
  52. HIGH_DRIVER_PRECHG_TIME EQU 0 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  53. ADC_LIMIT_L EQU 48 ; Power supply measurement ADC value for which main motor power is limited (low byte)
  54. ADC_LIMIT_H EQU 0 ; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
  55. TEMP_LIMIT EQU 168 ; Temperature measurement ADC value for which main motor power is limited (low byte, assuming high byte is 1)
  56. TEMP_LIMIT_STEP EQU 5 ; Temperature measurement ADC value increment for which main motor power is further limited
  57. ;**** **** **** **** ****
  58. ; ESC specific defaults
  59. ;**** **** **** **** ****
  60. DEFAULT_PGM_MAIN_SPOOLUP_TIME EQU 16 ; Main motor spoolup time
  61. DEFAULT_PGM_MAIN_STARTUP_PWR EQU 7 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  62. DEFAULT_PGM_TAIL_STARTUP_PWR EQU 7 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  63. DEFAULT_PGM_MULTI_STARTUP_PWR EQU 7 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  64. ;**** **** **** **** ****
  65. ; Bootloader definitions
  66. ;**** **** **** **** ****
  67. RTX_PORT EQU P0 ; Receive/Transmit port
  68. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  69. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  70. RTX_PIN EQU 3 ; RTX pin
  71. SIGNATURE_001 EQU 0f3h ; Device signature
  72. SIGNATURE_002 EQU 010h
  73. ;*********************
  74. ; PORT 0 definitions *
  75. ;*********************
  76. ; EQU 7 ;i
  77. ; EQU 6 ;i
  78. ; EQU 5 ;i
  79. ; EQU 4 ;i
  80. Rcp_In EQU 3 ;i
  81. ; EQU 2 ;i
  82. ; EQU 1 ;i
  83. Vref EQU 0 ;i
  84. P0_DIGITAL EQU NOT(1 SHL Vref)
  85. P0_INIT EQU 0FFh
  86. P0_PUSHPULL EQU 0
  87. P0_SKIP EQU NOT(1 SHL Rcp_In) AND 0FFh
  88. MACRO Get_Rcp_Capture_Values
  89. mov Temp1, PCA0CPL0 ; Get PCA capture values
  90. mov Temp2, PCA0CPH0
  91. ENDM
  92. MACRO Read_Rcp_Int
  93. mov A, P0
  94. jnb Flags3.PGM_RCP_PWM_POL, ($+4) ; Is pwm polarity negative?
  95. cpl A ; Yes - invert
  96. ENDM
  97. MACRO Rcp_Int_Enable
  98. orl PCA0CPM0, #01h ; Interrupt enabled
  99. ENDM
  100. MACRO Rcp_Int_Disable
  101. anl PCA0CPM0, #0FEh ; Interrupt disabled
  102. ENDM
  103. MACRO Rcp_Int_First
  104. anl PCA0CPM0, #0CFh
  105. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  106. orl PCA0CPM0, #20h ; Capture rising edge
  107. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  108. orl PCA0CPM0, #10h ; Capture falling edge
  109. ENDM
  110. MACRO Rcp_Int_Second
  111. anl PCA0CPM0, #0CFh
  112. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  113. orl PCA0CPM0, #10h ; Capture falling edge
  114. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  115. orl PCA0CPM0, #20h ; Capture rising edge
  116. ENDM
  117. MACRO Rcp_Clear_Int_Flag
  118. clr CCF0 ; Clear interrupt flag
  119. ENDM
  120. ;*********************
  121. ; PORT 1 definitions *
  122. ;*********************
  123. CnFET EQU 7 ;o
  124. CpFET EQU 6 ;o
  125. BnFET EQU 5 ;o
  126. BpFET EQU 4 ;o
  127. AnFET EQU 3 ;o
  128. ApFET EQU 2 ;o
  129. Adc_Ip EQU 1 ;i
  130. ; EQU 0 ;i
  131. P1_DIGITAL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  132. P1_INIT EQU (1 SHL Adc_Ip)
  133. P1_PUSHPULL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  134. P1_SKIP EQU 0
  135. ;*********************
  136. ; PORT 2 definitions *
  137. ;*********************
  138. ; EQU 7 ;i
  139. Mux_C EQU 6 ;i
  140. ; EQU 5 ;i
  141. Mux_B EQU 4 ;i
  142. CompCom EQU 3 ;i
  143. Mux_A EQU 2 ;i
  144. LED EQU 1 ;o
  145. ; EQU 0 ;i
  146. P2_DIGITAL EQU (1 SHL LED)
  147. P2_INIT EQU 0FDh
  148. P2_PUSHPULL EQU 02h
  149. P2_SKIP EQU 0
  150. MACRO AnFET_on
  151. mov A, Current_Pwm_Limited
  152. jz ($+12)
  153. jb Flags3.PGM_DIR_REV, ($+5)
  154. setb P1.AnFET
  155. jnb Flags3.PGM_DIR_REV, ($+5)
  156. setb P1.CnFET
  157. ENDM
  158. MACRO AnFET_off
  159. jb Flags3.PGM_DIR_REV, ($+5)
  160. clr P1.AnFET
  161. jnb Flags3.PGM_DIR_REV, ($+5)
  162. clr P1.CnFET
  163. ENDM
  164. MACRO BnFET_on
  165. mov A, Current_Pwm_Limited
  166. jz ($+4)
  167. setb P1.BnFET
  168. ENDM
  169. MACRO BnFET_off
  170. clr P1.BnFET
  171. ENDM
  172. MACRO CnFET_on
  173. mov A, Current_Pwm_Limited
  174. jz ($+12)
  175. jb Flags3.PGM_DIR_REV, ($+5)
  176. setb P1.CnFET
  177. jnb Flags3.PGM_DIR_REV, ($+5)
  178. setb P1.AnFET
  179. ENDM
  180. MACRO CnFET_off
  181. jb Flags3.PGM_DIR_REV, ($+5)
  182. clr P1.CnFET
  183. jnb Flags3.PGM_DIR_REV, ($+5)
  184. clr P1.AnFET
  185. ENDM
  186. MACRO All_nFETs_Off
  187. clr P1.AnFET
  188. clr P1.BnFET
  189. clr P1.CnFET
  190. ENDM
  191. MACRO ApFET_on
  192. jb Flags3.PGM_DIR_REV, ($+5)
  193. setb P1.ApFET
  194. jnb Flags3.PGM_DIR_REV, ($+5)
  195. setb P1.CpFET
  196. ENDM
  197. MACRO ApFET_off
  198. jb Flags3.PGM_DIR_REV, ($+5)
  199. clr P1.ApFET
  200. jnb Flags3.PGM_DIR_REV, ($+5)
  201. clr P1.CpFET
  202. ENDM
  203. MACRO BpFET_on
  204. setb P1.BpFET
  205. ENDM
  206. MACRO BpFET_off
  207. clr P1.BpFET
  208. ENDM
  209. MACRO CpFET_on
  210. jb Flags3.PGM_DIR_REV, ($+5)
  211. setb P1.CpFET
  212. jnb Flags3.PGM_DIR_REV, ($+5)
  213. setb P1.ApFET
  214. ENDM
  215. MACRO CpFET_off
  216. jb Flags3.PGM_DIR_REV, ($+5)
  217. clr P1.CpFET
  218. jnb Flags3.PGM_DIR_REV, ($+5)
  219. clr P1.ApFET
  220. ENDM
  221. MACRO All_pFETs_Off
  222. clr P1.ApFET
  223. clr P1.BpFET
  224. clr P1.CpFET
  225. ENDM
  226. MACRO All_pFETs_On
  227. setb P1.ApFET
  228. setb P1.BpFET
  229. setb P1.CpFET
  230. ENDM
  231. MACRO Set_Comp_Phase_A
  232. jb Flags3.PGM_DIR_REV, ($+6)
  233. mov CPT1MX, #22h ; Set comparator multiplexer to phase A
  234. jnb Flags3.PGM_DIR_REV, ($+6)
  235. mov CPT1MX, #23h
  236. ENDM
  237. MACRO Set_Comp_Phase_B
  238. mov CPT0MX, #33h ; Set comparator multiplexer to phase B
  239. mov CPT1MX, #00h ; Set mux to identifyable value
  240. ENDM
  241. MACRO Set_Comp_Phase_C
  242. jb Flags3.PGM_DIR_REV, ($+6)
  243. mov CPT1MX, #23h ; Set comparator multiplexer to phase C
  244. jnb Flags3.PGM_DIR_REV, ($+6)
  245. mov CPT1MX, #22h
  246. ENDM
  247. MACRO Read_Comp_Out
  248. mov A, CPT1MX
  249. jnz read_comp1
  250. mov A, CPT0CN ; Read comparator 0 output
  251. jmp read_comp_exit
  252. read_comp1:
  253. mov A, CPT1CN ; Read comparator 1 output
  254. read_comp_exit:
  255. ENDM
  256. ;*********************
  257. ; PORT 3 definitions *
  258. ;*********************
  259. ; EQU 4 ;i
  260. ; EQU 3 ;i
  261. ; EQU 2 ;i
  262. ; EQU 1 ;i
  263. DebugPin EQU 0 ;o
  264. P3_DIGITAL EQU 0FFh
  265. P3_INIT EQU 0FFh
  266. P3_PUSHPULL EQU (1 SHL DebugPin)
  267. ;**********************
  268. ; MCU specific macros *
  269. ;**********************
  270. MACRO Interrupt_Table_Definition
  271. CSEG AT 0 ; Code segment start
  272. jmp reset
  273. CSEG AT 0Bh ; Timer0 interrupt
  274. jmp t0_int
  275. CSEG AT 2Bh ; Timer2 interrupt
  276. jmp t2_int
  277. CSEG AT 5Bh ; PCA interrupt
  278. jmp pca_int
  279. CSEG AT 73h ; Timer3 interrupt
  280. jmp t3_int
  281. ENDM
  282. MACRO Initialize_Xbar
  283. mov XBR1, #41h ; Xbar enabled, CEX0 routed to pin Rcp_In
  284. ENDM
  285. MACRO Initialize_Adc
  286. mov REF0CN, #0Eh ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  287. mov ADC0CF, #58h ; ADC clock 2MHz
  288. mov AMX0P, #Adc_Ip ; Select positive input
  289. mov AMX0N, #1Fh ; Select negative input as ground
  290. mov ADC0CN, #80h ; ADC enabled
  291. ENDM
  292. MACRO Set_Adc_Ip_Volt
  293. mov AMX0P, #Adc_Ip ; Select positive input
  294. ENDM
  295. MACRO Set_Adc_Ip_Temp
  296. mov AMX0P, #1Eh ; Select temp sensor input
  297. ENDM
  298. MACRO Start_Adc
  299. mov ADC0CN, #90h ; ADC start
  300. ENDM
  301. MACRO Get_Adc_Status
  302. mov A, ADC0CN
  303. ENDM
  304. MACRO Read_Adc_Result
  305. mov Temp1, ADC0L
  306. mov Temp2, ADC0H
  307. ENDM
  308. MACRO Stop_Adc
  309. ENDM
  310. MACRO Set_RPM_Out
  311. ENDM
  312. MACRO Clear_RPM_Out
  313. ENDM
  314. MACRO Set_MCU_Clk_25MHz
  315. ENDM
  316. MACRO Set_MCU_Clk_50MHz
  317. ENDM