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11 years ago
  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hobbyking UBEC 30A hardware definition file
  26. ;
  27. ; Notes:
  28. ; - On 2S low voltage limiting does not work fully according to spec, as ADC reference drops with sensed voltage
  29. ; - High side is slow to go on (10s of us) but fast to go off
  30. ;
  31. ;**** **** **** **** ****
  32. ;*********************
  33. ; Device Atmega8A
  34. ;*********************
  35. .INCLUDE "m8Adef.inc"
  36. ;**** **** **** **** ****
  37. ; Fuses must be set to external oscillator = 16Mhz
  38. ;**** **** **** **** ****
  39. ;**** **** **** **** ****
  40. ; Constant definitions
  41. ;**** **** **** **** ****
  42. .ESEG ; EEprom segment
  43. .ORG 0x40
  44. Eep_ESC_Layout: .DB "#HK_UBEC_30A# " ; ESC layout tag
  45. .ORG 0x50
  46. Eep_ESC_MCU: .DB "#BLHELI#Am8A# " ; Project and MCU tag (16 Bytes)
  47. .EQU HIGH_BEC_VOLTAGE = 0 ; Set to 1 or more if high BEC voltage is supported
  48. .EQU DAMPED_MODE_ENABLE = 1 ; Set to 1 if fully damped mode is supported
  49. .EQU NFETON_DELAY = 5 ; Wait delay from pfets off to nfets on
  50. .EQU PFETON_DELAY = 5 ; Wait delay from nfets off to pfets on
  51. .EQU HIGH_DRIVER_PRECHG_TIME = 6 ; Time between commutations use to precharge the high side driver (for all nfet ESCs)
  52. .EQU ADC_LIMIT_L = 116 ; 51k/220k divider. Power supply measurement ADC value for which motor power is limited (low byte)
  53. .EQU ADC_LIMIT_H = 0 ; 51k/220k divider. Power supply measurement ADC value for which motor power is limited (2 MSBs)
  54. .EQU TEMP_LIMIT = 122 ; 820/3k3NTC. Temperature measurement ADC value for which main motor power is limited
  55. .EQU TEMP_LIMIT_STEP = 11 ; 820/3k3NTC. Temperature measurement ADC value increment for which main motor power is further limited
  56. ;**** **** **** **** ****
  57. ; ESC specific defaults
  58. ;**** **** **** **** ****
  59. .EQU DEFAULT_PGM_MAIN_SPOOLUP_TIME = 10 ; Main motor spoolup time
  60. .EQU DEFAULT_PGM_MAIN_STARTUP_PWR = 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  61. .EQU DEFAULT_PGM_TAIL_STARTUP_PWR = 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  62. .EQU DEFAULT_PGM_MULTI_STARTUP_PWR = 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  63. ;*********************
  64. ; PORT D definitions *
  65. ;*********************
  66. ;.EQU = 7 ;i
  67. ;.EQU = 6 ;i
  68. .EQU AnFET = 5 ;o
  69. .EQU ApFET = 4 ;o
  70. ;.EQU = 3 ;i
  71. .EQU Rcp_In = 2 ;i
  72. ;.EQU = 1 ;i
  73. ;.EQU = 0 ;i
  74. .equ INIT_PD = (1<<ApFET)
  75. .equ DIR_PD = (1<<AnFET)+(1<<ApFET)
  76. .MACRO Get_Rcp_Capture_Values
  77. in @0, TCNT1L
  78. in @1, TCNT1H
  79. .ENDMACRO
  80. .MACRO Read_Rcp_Int
  81. in @0, PIND
  82. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  83. com @0 ; Yes - invert
  84. .ENDMACRO
  85. .MACRO Get_Rcp_Int_Enable_State
  86. in @0, GICR ; Get int0 enable state (giving 0 is off, anything else is on)
  87. andi @0, (1<<INT0)
  88. .ENDMACRO
  89. .MACRO Rcp_Int_Enable
  90. ldi @0, (1<<INT0) ; Enable int0
  91. out GICR, @0
  92. .ENDMACRO
  93. .MACRO Rcp_Int_Disable
  94. ldi @0, 0 ; Disable int0
  95. out GICR, @0
  96. .ENDMACRO
  97. .MACRO Rcp_Int_First
  98. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  99. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  100. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  101. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  102. out MCUCR, @0
  103. .ENDMACRO
  104. .MACRO Rcp_Int_Second
  105. sbrs Flags3, PGM_RCP_PWM_POL ; Is pwm polarity positive?
  106. ldi @0, (1<<ISC01) ; Yes - set next int0 to falling
  107. sbrc Flags3, PGM_RCP_PWM_POL ; Is pwm polarity negative?
  108. ldi @0, (1<<ISC01)+(1<<ISC00); Yes - set next int0 to rising
  109. out MCUCR, @0
  110. .ENDMACRO
  111. .MACRO Rcp_Clear_Int_Flag
  112. clr @0
  113. sbr @0, (1<<INTF0) ; Clear ext0int flag
  114. out GIFR, @0
  115. .ENDMACRO
  116. .MACRO T0_Int_Disable
  117. in @0, TIMSK ; Disable timer0 interrupts
  118. cbr @0, (1<<TOIE0)
  119. out TIMSK, @0
  120. .ENDMACRO
  121. .MACRO T0_Int_Enable
  122. in @0, TIMSK ; Enable timer0 interrupts
  123. sbr @0, (1<<TOIE0)
  124. out TIMSK, @0
  125. .ENDMACRO
  126. .MACRO T1oca_Clear_Int_Flag
  127. ldi @0, (1<<OCF1A) ; Clear oc1a flag
  128. out TIFR, @0
  129. .ENDMACRO
  130. .MACRO T1oca_Int_Disable
  131. in @0, TIMSK ; Disable oc1a interrupts
  132. cbr @0, (1<<OCIE1A)
  133. out TIMSK, @0
  134. .ENDMACRO
  135. .MACRO T1oca_Int_Enable
  136. in @0, TIMSK ; Enable oc1a interrupts
  137. sbr @0, (1<<OCIE1A)
  138. out TIMSK, @0
  139. .ENDMACRO
  140. ;*********************
  141. ; PORT C definitions *
  142. ;*********************
  143. .EQU Mux_B = 7 ; i
  144. .EQU Mux_A = 6 ; i
  145. .EQU BpFET = 5 ; i
  146. .EQU BnFET = 4 ; i
  147. .EQU CpFET = 3 ; i
  148. .EQU Volt_Ip = 2 ; i
  149. .EQU Temp_Ip = 1 ; i
  150. .EQU Mux_C = 0 ; i
  151. .equ INIT_PC = (1<<BpFET)+(1<<CpFET)
  152. .equ DIR_PC = (1<<BnFET)+(1<<BpFET)+(1<<CpFET)
  153. .MACRO AnFET_on
  154. tst Current_Pwm_Limited
  155. breq PC+5
  156. sbrs Flags3, PGM_DIR_REV
  157. sbi PORTD, AnFET
  158. sbrc Flags3, PGM_DIR_REV
  159. sbi PORTB, CnFET
  160. .ENDMACRO
  161. .MACRO AnFET_off
  162. sbrs Flags3, PGM_DIR_REV
  163. cbi PORTD, AnFET
  164. sbrc Flags3, PGM_DIR_REV
  165. cbi PORTB, CnFET
  166. .ENDMACRO
  167. .MACRO BnFET_on
  168. tst Current_Pwm_Limited
  169. breq PC+2
  170. sbi PORTC, BnFET
  171. .ENDMACRO
  172. .MACRO BnFET_off
  173. cbi PORTC, BnFET
  174. .ENDMACRO
  175. .MACRO CnFET_on
  176. tst Current_Pwm_Limited
  177. breq PC+5
  178. sbrs Flags3, PGM_DIR_REV
  179. sbi PORTB, CnFET
  180. sbrc Flags3, PGM_DIR_REV
  181. sbi PORTD, AnFET
  182. .ENDMACRO
  183. .MACRO CnFET_off
  184. sbrs Flags3, PGM_DIR_REV
  185. cbi PORTB, CnFET
  186. sbrc Flags3, PGM_DIR_REV
  187. cbi PORTD, AnFET
  188. .ENDMACRO
  189. .MACRO All_nFETs_Off
  190. cbi PORTD, AnFET
  191. cbi PORTC, BnFET
  192. cbi PORTB, CnFET
  193. .ENDMACRO
  194. .MACRO ApFET_on
  195. sbrs Flags3, PGM_DIR_REV
  196. cbi PORTD, ApFET
  197. sbrc Flags3, PGM_DIR_REV
  198. cbi PORTC, CpFET
  199. .ENDMACRO
  200. .MACRO ApFET_off
  201. sbrs Flags3, PGM_DIR_REV
  202. sbi PORTD, ApFET
  203. sbrc Flags3, PGM_DIR_REV
  204. sbi PORTC, CpFET
  205. .ENDMACRO
  206. .MACRO BpFET_on
  207. cbi PORTC, BpFET
  208. .ENDMACRO
  209. .MACRO BpFET_off
  210. sbi PORTC, BpFET
  211. .ENDMACRO
  212. .MACRO CpFET_on
  213. sbrs Flags3, PGM_DIR_REV
  214. cbi PORTC, CpFET
  215. sbrc Flags3, PGM_DIR_REV
  216. cbi PORTD, ApFET
  217. .ENDMACRO
  218. .MACRO CpFET_off
  219. sbrs Flags3, PGM_DIR_REV
  220. sbi PORTC, CpFET
  221. sbrc Flags3, PGM_DIR_REV
  222. sbi PORTD, ApFET
  223. .ENDMACRO
  224. .MACRO All_pFETs_On
  225. cbi PORTD, ApFET
  226. cbi PORTC, BpFET
  227. cbi PORTC, CpFET
  228. .ENDMACRO
  229. .MACRO All_pFETs_Off
  230. sbi PORTD, ApFET
  231. sbi PORTC, BpFET
  232. sbi PORTC, CpFET
  233. .ENDMACRO
  234. .MACRO Comp_Init
  235. in @0, SFIOR ; Set Analog Comparator Multiplexer Enable
  236. sbr @0, (1<<ACME)
  237. out SFIOR, @0
  238. .ENDMACRO
  239. .MACRO Set_Comp_Phase_A
  240. sbrs Flags3, PGM_DIR_REV
  241. ldi @0, Mux_A ; Set comparator multiplexer to phase A
  242. sbrc Flags3, PGM_DIR_REV
  243. ldi @0, Mux_C
  244. out ADMUX, @0
  245. .ENDMACRO
  246. .MACRO Set_Comp_Phase_B
  247. ldi @0, Mux_B ; Set comparator multiplexer to phase B
  248. out ADMUX, @0
  249. .ENDMACRO
  250. .MACRO Set_Comp_Phase_C
  251. sbrs Flags3, PGM_DIR_REV
  252. ldi @0, Mux_C ; Set comparator multiplexer to phase C
  253. sbrc Flags3, PGM_DIR_REV
  254. ldi @0, Mux_A
  255. out ADMUX, @0
  256. .ENDMACRO
  257. .MACRO Read_Comp_Out
  258. in @0, ACSR ; Read comparator output
  259. .ENDMACRO
  260. ;*********************
  261. ; PORT B definitions *
  262. ;*********************
  263. ;.EQU = 7 ; i
  264. ;.EQU = 6 ; i
  265. ;.EQU = 5 ; i
  266. .EQU DebugPin = 4 ; o
  267. ;.EQU = 3 ; i
  268. ;.EQU = 2 ; i
  269. ;.EQU = 1 ; i
  270. .EQU CnFET = 0 ; o
  271. .EQU INIT_PB = 0x00
  272. .EQU DIR_PB = (1<<CnFET)+(1<<DebugPin)
  273. ;**********************
  274. ; MCU specific macros *
  275. ;**********************
  276. .MACRO Interrupt_Table_Definition
  277. rjmp reset
  278. rjmp rcp_int ; ext_int0
  279. nop ; ext_int1
  280. nop ; t2oc_int
  281. rjmp t2_int ; t2ovfl_int
  282. nop ; icp1_int
  283. rjmp t1oca_int ; t1oca_int
  284. nop ; t1ocb_int
  285. nop ; t1ovfl_int
  286. rjmp t0_int ; t0ovfl_int
  287. nop ; spi_int
  288. nop ; urxc
  289. nop ; udre
  290. nop ; utxc
  291. ; nop ; adc_int
  292. ; nop ; eep_int
  293. ; nop ; aci_int
  294. ; nop ; wire2_int
  295. ; nop ; spmc_int
  296. .ENDMACRO
  297. .MACRO Disable_Watchdog
  298. cli ; Disable interrupts
  299. wdr ; Reset watchdog timer
  300. in @0, WDTCR ; Write logical one to WDCE and WDE
  301. ori @0, (1<<WDCE)|(1<<WDE)
  302. out WDTCR, @0
  303. ldi @0, (0<<WDE) ; Turn off WDT
  304. out WDTCR, @0
  305. .ENDMACRO
  306. .MACRO Enable_Watchdog
  307. ldi @0, (1<<WDE) ; Turn on WDT
  308. out WDTCR, @0
  309. .ENDMACRO
  310. .MACRO Initialize_MCU
  311. .ENDMACRO
  312. .MACRO Initialize_Interrupts
  313. ldi @0, (1<<TOIE0)+(1<<OCIE1A)+(1<<TOIE2)
  314. out TIFR, @0 ; Clear interrupts
  315. out TIMSK, @0 ; Enable interrupts
  316. .ENDMACRO
  317. .MACRO Initialize_Adc
  318. in @0, ADCSRA ; Set ADCSRA register (1MHz clock)
  319. sbr @0, (1<<ADPS2)
  320. out ADCSRA, @0
  321. .ENDMACRO
  322. .MACRO Set_Adc_Ip_Volt
  323. cbr Flags1, (1<<ADC_READ_TEMP)
  324. .ENDMACRO
  325. .MACRO Set_Adc_Ip_Temp
  326. sbr Flags1, (1<<ADC_READ_TEMP)
  327. .ENDMACRO
  328. .MACRO Start_Adc
  329. sbrs Flags1, ADC_READ_TEMP
  330. ldi @0, Volt_Ip
  331. sbrc Flags1, ADC_READ_TEMP
  332. ldi @0, Temp_Ip
  333. out ADMUX, @0 ; Set ADMUX register (5V reference, selected input)
  334. in @0, ADCSRA
  335. sbr @0, (1<<ADEN) ; Enable ADC
  336. sbr @0, (1<<ADSC) ; Start ADC conversion
  337. out ADCSRA, @0
  338. .ENDMACRO
  339. .MACRO Get_Adc_Status
  340. in @0, ADCSRA
  341. .ENDMACRO
  342. .MACRO Read_Adc_Result
  343. in @0, ADCL
  344. in @1, ADCH
  345. .ENDMACRO
  346. .MACRO Stop_Adc
  347. in @0, ADCSRA
  348. cbr @0, (1<<ADEN) ; Disable ADC
  349. out ADCSRA, @0
  350. .ENDMACRO
  351. .MACRO Set_Timer0_CS0
  352. out TCCR0, @0
  353. .ENDMACRO
  354. .MACRO Set_Timer1_CS1
  355. out TCCR1B, @0
  356. .ENDMACRO
  357. .MACRO Set_Timer2_CS2
  358. out TCCR2, @0
  359. .ENDMACRO
  360. .MACRO Read_TCNT1L
  361. in @0, TCNT1L
  362. .ENDMACRO
  363. .MACRO Read_TCNT1H
  364. in @0, TCNT1H
  365. .ENDMACRO
  366. .MACRO Set_OCR1AL
  367. out OCR1AL, @0
  368. .ENDMACRO
  369. .MACRO Set_OCR1AH
  370. out OCR1AH, @0
  371. .ENDMACRO
  372. .MACRO Read_TCNT2
  373. in @0, TCNT2
  374. .ENDMACRO
  375. .MACRO Set_TCNT2
  376. out TCNT2, @0
  377. .ENDMACRO
  378. .MACRO Check_Eeprom_Ready
  379. sbic EECR, EEWE
  380. .ENDMACRO
  381. .MACRO Set_Eeprom_Address
  382. out EEARL, @0
  383. out EEARH, @1
  384. .ENDMACRO
  385. .MACRO Start_Eeprom_Write
  386. sbi EECR, EEMWE
  387. sbi EECR, EEWE
  388. .ENDMACRO
  389. .MACRO Prepare_Lock_Or_Fuse_Read
  390. ldi @0, ((1<<BLBSET)+(1<<SPMEN))
  391. out SPMCR, @0
  392. .ENDMACRO
  393. .MACRO xcall
  394. rcall @0
  395. .ENDMACRO
  396. .MACRO Set_RPM_Out
  397. .ENDMACRO
  398. .MACRO Clear_RPM_Out
  399. .ENDMACRO