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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Hardware definition file "V"
  26. ; Cc X RC X MC CC MB MA X Ap Ac Bp X X Bc Cp
  27. ;
  28. ;**** **** **** **** ****
  29. ;*********************
  30. ; Device SiLabs EFM8BB1x/2x
  31. ;*********************
  32. IF MCU_48MHZ == 0
  33. $include (SI_EFM8BB1_Defs.inc)
  34. ELSE
  35. $include (SI_EFM8BB2_Defs.inc)
  36. ENDIF
  37. ;**** **** **** **** ****
  38. ; Uses internal calibrated oscillator set to 24/48Mhz
  39. ;**** **** **** **** ****
  40. ;**** **** **** **** ****
  41. ; Constant definitions
  42. ;**** **** **** **** ****
  43. IF MCU_48MHZ == 0
  44. CSEG AT 1A40h
  45. IF FETON_DELAY == 0
  46. Eep_ESC_Layout: DB "#V_L_00# " ; ESC layout tag
  47. ELSEIF FETON_DELAY == 5
  48. Eep_ESC_Layout: DB "#V_L_05# "
  49. ELSEIF FETON_DELAY == 10
  50. Eep_ESC_Layout: DB "#V_L_10# "
  51. ELSEIF FETON_DELAY == 15
  52. Eep_ESC_Layout: DB "#V_L_15# "
  53. ELSEIF FETON_DELAY == 20
  54. Eep_ESC_Layout: DB "#V_L_20# "
  55. ELSEIF FETON_DELAY == 25
  56. Eep_ESC_Layout: DB "#V_L_25# "
  57. ELSEIF FETON_DELAY == 30
  58. Eep_ESC_Layout: DB "#V_L_30# "
  59. ELSEIF FETON_DELAY == 40
  60. Eep_ESC_Layout: DB "#V_L_40# "
  61. ELSEIF FETON_DELAY == 50
  62. Eep_ESC_Layout: DB "#V_L_50# "
  63. ELSEIF FETON_DELAY == 70
  64. Eep_ESC_Layout: DB "#V_L_70# "
  65. ELSEIF FETON_DELAY == 90
  66. Eep_ESC_Layout: DB "#V_L_90# "
  67. ENDIF
  68. CSEG AT 1A50h
  69. Eep_ESC_MCU: DB "#BLHELI$EFM8B10#" ; Project and MCU tag (16 Bytes)
  70. ELSE
  71. CSEG AT 1A40h
  72. IF FETON_DELAY == 0
  73. Eep_ESC_Layout: DB "#V_H_00# " ; ESC layout tag
  74. ELSEIF FETON_DELAY == 5
  75. Eep_ESC_Layout: DB "#V_H_05# "
  76. ELSEIF FETON_DELAY == 10
  77. Eep_ESC_Layout: DB "#V_H_10# "
  78. ELSEIF FETON_DELAY == 15
  79. Eep_ESC_Layout: DB "#V_H_15# "
  80. ELSEIF FETON_DELAY == 20
  81. Eep_ESC_Layout: DB "#V_H_20# "
  82. ELSEIF FETON_DELAY == 25
  83. Eep_ESC_Layout: DB "#V_H_25# "
  84. ELSEIF FETON_DELAY == 30
  85. Eep_ESC_Layout: DB "#V_H_30# "
  86. ELSEIF FETON_DELAY == 40
  87. Eep_ESC_Layout: DB "#V_H_40# "
  88. ELSEIF FETON_DELAY == 50
  89. Eep_ESC_Layout: DB "#V_H_50# "
  90. ELSEIF FETON_DELAY == 70
  91. Eep_ESC_Layout: DB "#V_H_70# "
  92. ELSEIF FETON_DELAY == 90
  93. Eep_ESC_Layout: DB "#V_H_90# "
  94. ENDIF
  95. CSEG AT 1A50h
  96. Eep_ESC_MCU: DB "#BLHELI$EFM8B21#" ; Project and MCU tag (16 Bytes)
  97. ENDIF
  98. TEMP_LIMIT EQU 49 ; Temperature measurement ADC value for which main motor power is limited at 80degC (low byte, assuming high byte is 1)
  99. TEMP_LIMIT_STEP EQU 9 ; Temperature measurement ADC value increment for another 10degC
  100. ;**** **** **** **** ****
  101. ; Bootloader definitions
  102. ;**** **** **** **** ****
  103. RTX_PORT EQU P0 ; Receive/Transmit port
  104. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  105. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  106. RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP
  107. RTX_PIN EQU 5 ; RTX pin
  108. SIGNATURE_001 EQU 0E8h ; Device signature
  109. IF MCU_48MHZ == 0
  110. SIGNATURE_002 EQU 0B1h
  111. ELSE
  112. SIGNATURE_002 EQU 0B2h
  113. ENDIF
  114. ;*********************
  115. ; PORT 0 definitions *
  116. ;*********************
  117. CcomFET EQU 7 ;o
  118. ; EQU 6 ;i
  119. Rcp_In EQU 5 ;i
  120. ; EQU 4 ;i
  121. Mux_C EQU 3 ;i
  122. Comp_Com EQU 2 ;i
  123. Mux_B EQU 1 ;i
  124. Mux_A EQU 0 ;i
  125. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com))
  126. P0_INIT EQU NOT(1 SHL CcomFET)
  127. P0_PUSHPULL EQU (1 SHL CcomFET)
  128. P0_SKIP EQU 0FFh
  129. Get_Rcp_Capture_Values MACRO
  130. anl TCON, #0EFh ; Disable timer0
  131. mov Temp1, TL0 ; Get timer0 values
  132. mov Temp2, TH0
  133. IF MCU_48MHZ == 1
  134. mov Temp3, Timer0_X
  135. jnb TCON_TF0, ($+4) ; Check if interrupt is pending
  136. inc Temp3 ; If it is pending, then timer has already wrapped
  137. ENDIF
  138. mov TL0, #0 ; Reset timer0
  139. mov TH0, #0
  140. IF MCU_48MHZ == 1
  141. mov Timer0_X, #0
  142. ENDIF
  143. orl TCON, #10h ; Enable timer0 again
  144. IF MCU_48MHZ == 1
  145. mov A, Clock_Set_At_48MHz
  146. jnz Get_Rcp_End
  147. clr C
  148. mov A, Temp1
  149. rlc A
  150. mov Temp1, A
  151. mov A, Temp2
  152. rlc A
  153. mov Temp2, A
  154. mov A, Temp3
  155. rlc A
  156. mov Temp3, A
  157. Get_Rcp_End:
  158. ENDIF
  159. ENDM
  160. Decode_Dshot_2Msb MACRO
  161. movx A, @DPTR
  162. mov Temp6, A
  163. clr C
  164. subb A, Temp5 ; Subtract previous timestamp
  165. clr C
  166. subb A, Temp1
  167. jc t1_int_msb_fail ; Check that bit is longer than minimum
  168. subb A, Temp1 ; Check if bit is zero or one
  169. mov A, Temp4 ; Shift bit into data byte
  170. rlc A
  171. mov Temp4, A
  172. inc DPL ; Next bit
  173. movx A, @DPTR
  174. mov Temp5, A
  175. clr C
  176. subb A, Temp6
  177. clr C
  178. subb A, Temp1
  179. jc t1_int_msb_fail
  180. subb A, Temp1
  181. mov A, Temp4
  182. rlc A
  183. mov Temp4, A
  184. inc DPL
  185. ENDM
  186. Decode_Dshot_2Lsb MACRO
  187. movx A, @DPTR
  188. mov Temp6, A
  189. clr C
  190. subb A, Temp5 ; Subtract previous timestamp
  191. clr C
  192. subb A, Temp1
  193. jc t1_int_lsb_fail ; Check that bit is longer than minimum
  194. subb A, Temp1 ; Check if bit is zero or one
  195. mov A, Temp3 ; Shift bit into data byte
  196. rlc A
  197. mov Temp3, A
  198. inc DPL ; Next bit
  199. movx A, @DPTR
  200. mov Temp5, A
  201. clr C
  202. subb A, Temp6
  203. clr C
  204. subb A, Temp1
  205. jc t1_int_lsb_fail
  206. subb A, Temp1
  207. mov A, Temp3
  208. rlc A
  209. mov Temp3, A
  210. inc DPL
  211. ENDM
  212. Initialize_PCA MACRO
  213. mov PCA0CN0, #40h ; PCA enabled
  214. mov PCA0MD, #08h ; PCA clock is system clock
  215. IF FETON_DELAY == 0
  216. IF MCU_48MHZ == 0
  217. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  218. ELSE
  219. mov PCA0PWM, #83h ; PCA ARSEL set and 11bits pwm
  220. ENDIF
  221. mov PCA0CENT, #00h ; Edge aligned pwm
  222. ELSE
  223. IF MCU_48MHZ == 0
  224. mov PCA0PWM, #81h ; PCA ARSEL set and 9bits pwm
  225. ELSE
  226. mov PCA0PWM, #82h ; PCA ARSEL set and 10bits pwm
  227. ENDIF
  228. mov PCA0CENT, #03h ; Center aligned pwm
  229. ENDIF
  230. ENDM
  231. Set_Pwm_Polarity MACRO
  232. IF FETON_DELAY == 0
  233. mov PCA0POL, #00h ; Pwm noninverted
  234. ELSE
  235. mov PCA0POL, #01h ; Damping inverted, pwm noninverted
  236. ENDIF
  237. ENDM
  238. Enable_Power_Pwm_Module MACRO
  239. IF FETON_DELAY == 0
  240. mov PCA0CPM0, #4Ah ; Enable comparator of module, enable match, set pwm mode
  241. ELSE
  242. mov PCA0CPM1, #42h ; Enable comparator of module, set pwm mode
  243. ENDIF
  244. ENDM
  245. Enable_Damp_Pwm_Module MACRO
  246. IF FETON_DELAY == 0
  247. mov PCA0CPM1, #00h ; Disable
  248. ELSE
  249. mov PCA0CPM0, #42h ; Enable comparator of module, set pwm mode
  250. ENDIF
  251. ENDM
  252. Set_Power_Pwm_Regs MACRO
  253. IF FETON_DELAY == 0
  254. mov PCA0CPL0, Power_Pwm_Reg_L
  255. mov PCA0CPH0, Power_Pwm_Reg_H
  256. ELSE
  257. clr C
  258. mov A, Power_Pwm_Reg_H
  259. rrc A
  260. mov Temp1, A
  261. mov A, Power_Pwm_Reg_L
  262. rrc A
  263. mov PCA0CPL1, A
  264. mov PCA0CPH1, Temp1
  265. ENDIF
  266. ENDM
  267. Set_Damp_Pwm_Regs MACRO
  268. IF FETON_DELAY == 0
  269. mov PCA0CPL1, Damp_Pwm_Reg_L
  270. mov PCA0CPH1, Damp_Pwm_Reg_H
  271. ELSE
  272. clr C
  273. mov A, Damp_Pwm_Reg_H
  274. rrc A
  275. mov Temp1, A
  276. mov A, Damp_Pwm_Reg_L
  277. rrc A
  278. mov PCA0CPL0, A
  279. mov PCA0CPH0, Temp1
  280. ENDIF
  281. ENDM
  282. Clear_COVF_Interrupt MACRO
  283. anl PCA0PWM, #0DFh
  284. ENDM
  285. Clear_CCF_Interrupt MACRO
  286. anl PCA0CN0, #0FEh
  287. ENDM
  288. Enable_COVF_Interrupt MACRO
  289. orl PCA0PWM, #40h
  290. ENDM
  291. Enable_CCF_Interrupt MACRO
  292. orl PCA0CPM0,#01h
  293. ENDM
  294. Disable_COVF_Interrupt MACRO
  295. anl PCA0PWM, #0BFh
  296. ENDM
  297. Disable_CCF_Interrupt MACRO
  298. anl PCA0CPM0,#0FEh
  299. ENDM
  300. ;*********************
  301. ; PORT 1 definitions *
  302. ;*********************
  303. ; EQU 7 ;i
  304. ApwmFET EQU 6 ;i
  305. AcomFET EQU 5 ;i
  306. BpwmFET EQU 4 ;o
  307. ; EQU 3 ;o
  308. ; EQU 2 ;o
  309. BcomFET EQU 1 ;o
  310. CpwmFET EQU 0 ;o
  311. P1_DIGITAL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)
  312. P1_INIT EQU 00h
  313. P1_PUSHPULL EQU (1 SHL ApwmFET)+(1 SHL BpwmFET)+(1 SHL CpwmFET)+(1 SHL AcomFET)+(1 SHL BcomFET)
  314. P1_SKIP EQU 7Fh
  315. ApwmFET_on MACRO
  316. setb P1.ApwmFET
  317. IF FETON_DELAY == 0
  318. setb P1.AcomFET
  319. ENDIF
  320. ENDM
  321. ApwmFET_off MACRO
  322. IF FETON_DELAY != 0
  323. clr P1.ApwmFET
  324. ELSE
  325. clr P1.AcomFET
  326. ENDIF
  327. ENDM
  328. BpwmFET_on MACRO
  329. setb P1.BpwmFET
  330. IF FETON_DELAY == 0
  331. setb P1.BcomFET
  332. ENDIF
  333. ENDM
  334. BpwmFET_off MACRO
  335. IF FETON_DELAY != 0
  336. clr P1.BpwmFET
  337. ELSE
  338. clr P1.BcomFET
  339. ENDIF
  340. ENDM
  341. CpwmFET_on MACRO
  342. setb P1.CpwmFET
  343. IF FETON_DELAY == 0
  344. setb P0.CcomFET
  345. ENDIF
  346. ENDM
  347. CpwmFET_off MACRO
  348. IF FETON_DELAY != 0
  349. clr P1.CpwmFET
  350. ELSE
  351. clr P0.CcomFET
  352. ENDIF
  353. ENDM
  354. All_pwmFETs_Off MACRO
  355. IF FETON_DELAY != 0
  356. clr P1.ApwmFET
  357. clr P1.BpwmFET
  358. clr P1.CpwmFET
  359. ELSE
  360. clr P1.AcomFET
  361. clr P1.BcomFET
  362. clr P0.CcomFET
  363. ENDIF
  364. ENDM
  365. AcomFET_on MACRO
  366. IF FETON_DELAY == 0
  367. clr P1.ApwmFET
  368. ENDIF
  369. setb P1.AcomFET
  370. ENDM
  371. AcomFET_off MACRO
  372. clr P1.AcomFET
  373. ENDM
  374. BcomFET_on MACRO
  375. IF FETON_DELAY == 0
  376. clr P1.BpwmFET
  377. ENDIF
  378. setb P1.BcomFET
  379. ENDM
  380. BcomFET_off MACRO
  381. clr P1.BcomFET
  382. ENDM
  383. CcomFET_on MACRO
  384. IF FETON_DELAY == 0
  385. clr P1.CpwmFET
  386. ENDIF
  387. setb P0.CcomFET
  388. ENDM
  389. CcomFET_off MACRO
  390. clr P0.CcomFET
  391. ENDM
  392. All_comFETs_Off MACRO
  393. clr P1.AcomFET
  394. clr P1.BcomFET
  395. clr P0.CcomFET
  396. ENDM
  397. Set_Pwm_A MACRO
  398. IF FETON_DELAY == 0
  399. setb P1.AcomFET
  400. mov P0SKIP, #0FFh
  401. mov P1SKIP, #3Fh
  402. ELSE
  403. mov P0SKIP, #0FFh
  404. mov P1SKIP, #1Fh
  405. ENDIF
  406. ENDM
  407. Set_Pwm_B MACRO
  408. IF FETON_DELAY == 0
  409. setb P1.BcomFET
  410. mov P0SKIP, #0FFh
  411. mov P1SKIP, #6Fh
  412. ELSE
  413. mov P0SKIP, #0FFh
  414. mov P1SKIP, #6Dh
  415. endif
  416. ENDM
  417. Set_Pwm_C MACRO
  418. IF FETON_DELAY == 0
  419. setb P0.CcomFET
  420. mov P0SKIP, #0FFh
  421. mov P1SKIP, #7Fh
  422. ELSE
  423. mov P0SKIP, #7Fh
  424. mov P1SKIP, #7Eh
  425. endif
  426. ENDM
  427. Set_Pwms_Off MACRO
  428. mov P0SKIP, #0FFh
  429. mov P1SKIP, #7Fh
  430. ENDM
  431. Set_Comp_Phase_A MACRO
  432. mov CMP0MX, #02h ; Set comparator multiplexer to phase A
  433. ENDM
  434. Set_Comp_Phase_B MACRO
  435. mov CMP0MX, #12h ; Set comparator multiplexer to phase B
  436. ENDM
  437. Set_Comp_Phase_C MACRO
  438. mov CMP0MX, #32h ; Set comparator multiplexer to phase C
  439. ENDM
  440. Read_Comp_Out MACRO
  441. mov A, CMP0CN0 ; Read comparator output
  442. ENDM
  443. ;*********************
  444. ; PORT 2 definitions *
  445. ;*********************
  446. DebugPin EQU 0 ;o
  447. P2_PUSHPULL EQU (1 SHL DebugPin)
  448. ;**********************
  449. ; MCU specific macros *
  450. ;**********************
  451. Interrupt_Table_Definition MACRO
  452. CSEG AT 0 ; Code segment start
  453. jmp reset
  454. CSEG AT 03h ; Int0 interrupt
  455. jmp int0_int
  456. IF MCU_48MHZ == 1
  457. CSEG AT 0Bh ; Timer0 overflow interrupt
  458. jmp t0_int
  459. ENDIF
  460. CSEG AT 13h ; Int1 interrupt
  461. jmp int1_int
  462. CSEG AT 1Bh ; Timer1 overflow interrupt
  463. jmp t1_int
  464. CSEG AT 2Bh ; Timer2 overflow interrupt
  465. jmp t2_int
  466. CSEG AT 5Bh ; Pca interrupt
  467. jmp pca_int
  468. CSEG AT 73h ; Timer3 overflow/compare interrupt
  469. jmp t3_int
  470. ENDM
  471. Initialize_Xbar MACRO
  472. mov XBR2, #40h ; Xbar enabled
  473. mov XBR1, #02h ; CEX0 and CEX1 routed to pins
  474. ENDM
  475. Initialize_Comparator MACRO
  476. mov CMP0CN0, #80h ; Comparator enabled, no hysteresis
  477. mov CMP0MD, #00h ; Comparator response time 100ns
  478. ENDM
  479. Initialize_Adc MACRO
  480. mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  481. IF MCU_48MHZ == 0
  482. mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1
  483. ELSE
  484. mov ADC0CF, #0B9h ; ADC clock 2MHz, PGA gain 1
  485. ENDIF
  486. mov ADC0MX, #10h ; Select temp sensor input
  487. mov ADC0CN0, #80h ; ADC enabled
  488. mov ADC0CN1, #01h ; Common mode buffer enabled
  489. ENDM
  490. Start_Adc MACRO
  491. mov ADC0CN0, #90h ; ADC start
  492. ENDM
  493. Read_Adc_Result MACRO
  494. mov Temp1, ADC0L
  495. mov Temp2, ADC0H
  496. ENDM
  497. Stop_Adc MACRO
  498. ENDM
  499. Set_RPM_Out MACRO
  500. ENDM
  501. Clear_RPM_Out MACRO
  502. ENDM
  503. Set_MCU_Clk_24MHz MACRO
  504. mov CLKSEL, #13h ; Set clock to 24MHz
  505. mov SFRPAGE, #10h
  506. mov PFE0CN, #00h ; Set flash timing for 24MHz
  507. mov SFRPAGE, #00h
  508. mov Clock_Set_At_48MHz, #0
  509. ENDM
  510. Set_MCU_Clk_48MHz MACRO
  511. mov SFRPAGE, #10h
  512. mov PFE0CN, #30h ; Set flash timing for 48MHz
  513. mov SFRPAGE, #00h
  514. mov CLKSEL, #03h ; Set clock to 48MHz
  515. mov Clock_Set_At_48MHz, #1
  516. ENDM
  517. Set_LED_0 MACRO
  518. ENDM
  519. Clear_LED_0 MACRO
  520. ENDM
  521. Set_LED_1 MACRO
  522. ENDM
  523. Clear_LED_1 MACRO
  524. ENDM
  525. Set_LED_2 MACRO
  526. ENDM
  527. Clear_LED_2 MACRO
  528. ENDM
  529. Set_LED_3 MACRO
  530. ENDM
  531. Clear_LED_3 MACRO
  532. ENDM