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  1. ;**** **** **** **** ****
  2. ;
  3. ; BLHeli program for controlling brushless motors in helicopters and multirotors
  4. ;
  5. ; Copyright 2011, 2012 Steffen Skaug
  6. ; This program is distributed under the terms of the GNU General Public License
  7. ;
  8. ; This file is part of BLHeli.
  9. ;
  10. ; BLHeli is free software: you can redistribute it and/or modify
  11. ; it under the terms of the GNU General Public License as published by
  12. ; the Free Software Foundation, either version 3 of the License, or
  13. ; (at your option) any later version.
  14. ;
  15. ; BLHeli is distributed in the hope that it will be useful,
  16. ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. ; GNU General Public License for more details.
  19. ;
  20. ; You should have received a copy of the GNU General Public License
  21. ; along with BLHeli. If not, see <http://www.gnu.org/licenses/>.
  22. ;
  23. ;**** **** **** **** ****
  24. ;
  25. ; Flycolor Fairy 30A hardware definition file
  26. ;
  27. ;**** **** **** **** ****
  28. ;*********************
  29. ; Device SiLabs F850
  30. ;*********************
  31. $include (c8051f850.inc)
  32. ;**** **** **** **** ****
  33. ; Uses internal calibrated oscillator set to 24Mhz
  34. ;**** **** **** **** ****
  35. ;**** **** **** **** ****
  36. ; Constant definitions
  37. ;**** **** **** **** ****
  38. CSEG AT 1A40h
  39. Eep_ESC_Layout: DB "#FC_Fairy_30A# " ; ESC layout tag
  40. CSEG AT 1A50h
  41. Eep_ESC_MCU: DB "#BLHELI#F850# " ; Project and MCU tag (16 Bytes)
  42. MCU_48MHZ EQU 0 ; Set to 1 if MCU can run at 48MHz
  43. ONE_S_CAPABLE EQU 0 ; Set to 1 if ESC can operate at 1S
  44. PORT3_EXIST EQU 0 ; Set to 1 if MCU has port3
  45. COMP1_USED EQU 0 ; Set to 1 if MCU has comparator 1 and it is being used
  46. LOCK_BYTE_ADDRESS_16K EQU 3FFFh ; Address of lock byte if 16k flash size
  47. LOCK_BYTE_ADDRESS_8K EQU 1FFFh ; Address of lock byte if 8k flash size
  48. HIGH_BEC_VOLTAGE EQU 0 ; Set to 1 or more if high BEC voltage is supported
  49. DAMPED_MODE_ENABLE EQU 1 ; Damped mode enabled
  50. NFETON_DELAY EQU 6 ; Wait delay from pfets off to nfets on
  51. PFETON_DELAY EQU 1 ; Wait delay from nfets off to pfets on
  52. ADC_LIMIT_L EQU 85 ; Power supply measurement ADC value for which main motor power is limited (low byte)
  53. ADC_LIMIT_H EQU 0 ; Power supply measurement ADC value for which main motor power is limited (2 MSBs)
  54. TEMP_LIMIT EQU 103 ; Temperature measurement ADC value for which main motor power is limited (low byte, assuming high byte is 1)
  55. TEMP_LIMIT_STEP EQU 4 ; Temperature measurement ADC value increment for which main motor power is further limited
  56. ;**** **** **** **** ****
  57. ; ESC specific defaults
  58. ;**** **** **** **** ****
  59. DEFAULT_PGM_MAIN_SPOOLUP_TIME EQU 10 ; Main motor spoolup time
  60. DEFAULT_PGM_MAIN_STARTUP_PWR EQU 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  61. DEFAULT_PGM_TAIL_STARTUP_PWR EQU 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  62. DEFAULT_PGM_MULTI_STARTUP_PWR EQU 9 ; 1=0.031 2=0.047 3=0.063 4=0.094 5=0.125 6=0.188 7=0.25 8=0.38 9=0.50 10=0.75 11=1.00 12=1.25 13=1.50
  63. ;**** **** **** **** ****
  64. ; Bootloader definitions
  65. ;**** **** **** **** ****
  66. RTX_PORT EQU P0 ; Receive/Transmit port
  67. RTX_MDOUT EQU P0MDOUT ; Set to 1 for PUSHPULL
  68. RTX_MDIN EQU P0MDIN ; Set to 1 for DIGITAL
  69. RTX_SKIP EQU P0SKIP ; Set to 1 for SKIP
  70. RTX_PIN EQU 5 ; RTX pin
  71. SIGNATURE_001 EQU 0f8h ; Device signature
  72. SIGNATURE_002 EQU 050h
  73. ;*********************
  74. ; PORT 0 definitions *
  75. ;*********************
  76. ; EQU 7 ;i (Temp)
  77. Adc_Ip EQU 6 ;i
  78. Rcp_In EQU 5 ;i
  79. ; EQU 4 ;i (Rcp 1k)
  80. Mux_C EQU 3 ;i
  81. Mux_B EQU 2 ;i
  82. Mux_A EQU 1 ;i
  83. Comp_Com EQU 0 ;i
  84. P0_DIGITAL EQU NOT((1 SHL Mux_A)+(1 SHL Mux_B)+(1 SHL Mux_C)+(1 SHL Comp_Com)+(1 SHL Adc_Ip))
  85. P0_INIT EQU 0FFh
  86. P0_PUSHPULL EQU 0
  87. P0_SKIP EQU NOT(1 SHL Rcp_In) AND 0FFh
  88. MACRO Get_Rcp_Capture_Values
  89. mov Temp1, PCA0CPL0 ; Get PCA capture values
  90. mov Temp2, PCA0CPH0
  91. ENDM
  92. MACRO Read_Rcp_Int
  93. mov A, P0
  94. jnb Flags3.PGM_RCP_PWM_POL, ($+4) ; Is pwm polarity negative?
  95. cpl A ; Yes - invert
  96. ENDM
  97. MACRO Rcp_Int_Enable
  98. orl PCA0CPM0, #01h ; Interrupt enabled
  99. ENDM
  100. MACRO Rcp_Int_Disable
  101. anl PCA0CPM0, #0FEh ; Interrupt disabled
  102. ENDM
  103. MACRO Rcp_Int_First
  104. anl PCA0CPM0, #0CFh
  105. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  106. orl PCA0CPM0, #20h ; Capture rising edge
  107. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  108. orl PCA0CPM0, #10h ; Capture falling edge
  109. ENDM
  110. MACRO Rcp_Int_Second
  111. anl PCA0CPM0, #0CFh
  112. jb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity positive?
  113. orl PCA0CPM0, #10h ; Capture falling edge
  114. jnb Flags3.PGM_RCP_PWM_POL, ($+6) ; Is pwm polarity negative?
  115. orl PCA0CPM0, #20h ; Capture rising edge
  116. ENDM
  117. MACRO Rcp_Clear_Int_Flag
  118. clr CCF0 ; Clear interrupt flag
  119. ENDM
  120. ;*********************
  121. ; PORT 1 definitions *
  122. ;*********************
  123. ; EQU 7 ;i
  124. ; EQU 6 ;i
  125. CnFET EQU 5 ;o
  126. CpFET EQU 4 ;o
  127. BnFET EQU 3 ;o
  128. BpFET EQU 2 ;o
  129. AnFET EQU 1 ;o
  130. ApFET EQU 0 ;o
  131. P1_DIGITAL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  132. P1_INIT EQU (1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  133. P1_PUSHPULL EQU (1 SHL AnFET)+(1 SHL BnFET)+(1 SHL CnFET)+(1 SHL ApFET)+(1 SHL BpFET)+(1 SHL CpFET)
  134. P1_SKIP EQU 0
  135. MACRO AnFET_on
  136. setb P1.AnFET
  137. ENDM
  138. MACRO AnFET_off
  139. clr P1.AnFET
  140. ENDM
  141. MACRO BnFET_on
  142. setb P1.BnFET
  143. ENDM
  144. MACRO BnFET_off
  145. clr P1.BnFET
  146. ENDM
  147. MACRO CnFET_on
  148. setb P1.CnFET
  149. ENDM
  150. MACRO CnFET_off
  151. clr P1.CnFET
  152. ENDM
  153. MACRO All_nFETs_Off
  154. clr P1.AnFET
  155. clr P1.BnFET
  156. clr P1.CnFET
  157. ENDM
  158. MACRO ApFET_on
  159. clr P1.ApFET
  160. ENDM
  161. MACRO ApFET_off
  162. setb P1.ApFET
  163. ENDM
  164. MACRO BpFET_on
  165. clr P1.BpFET
  166. ENDM
  167. MACRO BpFET_off
  168. setb P1.BpFET
  169. ENDM
  170. MACRO CpFET_on
  171. clr P1.CpFET
  172. ENDM
  173. MACRO CpFET_off
  174. setb P1.CpFET
  175. ENDM
  176. MACRO All_pFETs_Off
  177. setb P1.ApFET
  178. setb P1.BpFET
  179. setb P1.CpFET
  180. ENDM
  181. MACRO Brake_FETs_On
  182. AnFET_on
  183. BnFET_on
  184. CnFET_on
  185. ENDM
  186. MACRO Damping_FET_On
  187. mov A, DampingFET
  188. cpl A
  189. anl P1, A
  190. ENDM
  191. MACRO Set_Comp_Phase_A
  192. mov CPT0MX, #01h ; Set comparator multiplexer to phase A
  193. ENDM
  194. MACRO Set_Comp_Phase_B
  195. mov CPT0MX, #02h ; Set comparator multiplexer to phase B
  196. ENDM
  197. MACRO Set_Comp_Phase_C
  198. mov CPT0MX, #03h ; Set comparator multiplexer to phase C
  199. ENDM
  200. MACRO Read_Comp_Out
  201. mov A, CPT0CN ; Read comparator output
  202. ENDM
  203. ;*********************
  204. ; PORT 2 definitions *
  205. ;*********************
  206. DebugPin EQU 0 ;o
  207. P2_PUSHPULL EQU (1 SHL DebugPin)
  208. ;**********************
  209. ; MCU specific macros *
  210. ;**********************
  211. MACRO Interrupt_Table_Definition
  212. CSEG AT 0 ; Code segment start
  213. jmp reset
  214. CSEG AT 0Bh ; Timer0 interrupt
  215. jmp t0_int
  216. CSEG AT 2Bh ; Timer2 interrupt
  217. jmp t2_int
  218. CSEG AT 5Bh ; PCA interrupt
  219. jmp pca_int
  220. CSEG AT 73h ; Timer3 interrupt
  221. jmp t3_int
  222. ENDM
  223. MACRO Initialize_Xbar
  224. mov XBR2, #40h ; Xbar enabled
  225. mov XBR1, #01h ; CEX0 routed to pin Rcp_In
  226. ENDM
  227. MACRO Initialize_Adc
  228. mov REF0CN, #0Ch ; Set vdd (3.3V) as reference. Enable temp sensor and bias
  229. mov ADC0CF, #59h ; ADC clock 2MHz, PGA gain 1
  230. mov ADC0MX, #Adc_Ip; Select ADC input
  231. mov ADC0CN0, #80h ; ADC enabled
  232. mov ADC0CN1, #01h ; Common mode buffer enabled
  233. ENDM
  234. MACRO Set_Adc_Ip_Volt
  235. mov ADC0MX, #Adc_Ip; Select ADC input
  236. ENDM
  237. MACRO Set_Adc_Ip_Temp
  238. mov ADC0MX, #10h ; Select temp sensor input
  239. ENDM
  240. MACRO Start_Adc
  241. mov ADC0CN0, #90h ; ADC start
  242. ENDM
  243. MACRO Read_Adc_Result
  244. mov Temp1, ADC0L
  245. mov Temp2, ADC0H
  246. ENDM
  247. MACRO Stop_Adc
  248. ENDM
  249. MACRO Set_RPM_Out
  250. ENDM
  251. MACRO Clear_RPM_Out
  252. ENDM
  253. MACRO Set_MCU_Clk_24MHz
  254. ENDM
  255. MACRO Set_MCU_Clk_48MHz
  256. ENDM